Context Navigation

PE.vhd @ 43

Last change on this file since 43 was 41, checked in by rolagamo, 12 years ago
Ceci est la version stable avant optimisation
File size: 16.4 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 21:20:54 07/16/2012
6	-- Design Name:
7	-- Module Name: PE - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	library NocLib ;
23	library Std;
24	--use IEEE.STD_LOGIC_ARITH.ALL;
25	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	use NocLib.CoreTypes.all;
27	use work.Packet_type.all;
28	use work.MPI_RMA.all;
29	-- synthesis translate_off
30	use std.textio.all;
31	-- synthesis translate_on
32	use IEEE.NUMERIC_STD.ALL;
33
34
35	entity PE is
36	Generic (DestId : natural:=0 );
37	Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0);
38	Instruction_en : out STD_LOGIC;
39	Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
40	clk : in STD_LOGIC;
41	reset : in STD_LOGIC;
42	Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0);
44	Core_RAM_WE : in STD_LOGIC;
45	Core_RAM_EN : in STD_LOGIC;
46	--Core_RAM_ENB : in STD_LOGIC;
47	Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
48	Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
49	Core_Hold_req : in STD_LOGIC;
50	Core_Hold_Ack : out STD_LOGIC);
51	end PE;
52
53	architecture Behavioral of PE is
54	COMPONENT RAM_v
55	generic (width : positive;size :positive);
56	PORT(
57	clka : IN std_logic;
58	clkb : IN std_logic;
59	wea : IN std_logic;
60	ena : IN std_logic;
61	enb : IN std_logic;
62	addra : IN std_logic_vector;
63	addrb : IN std_logic_vector;
64	dia : IN std_logic_vector;
65	dob : OUT std_logic_vector
66	);
67	END COMPONENT;
68	--données du programme PE
69	--signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0');
70	signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0';
71	signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic;
72	signal pe_instr_en,pe_hold_ack: std_logic:='0';
73	signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
74	signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
75	signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
76	signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
77	signal sram : typ_dpram;
78
79	signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0);
80	signal dpid,dpid_i : natural range 0 to 15:=DestId;
81	signal MyRank :std_logic_vector(3 downto 0);
82	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
83	signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée
84	signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO
85	signal Lib_Init : std_logic; -- l'initialisation est terminée
86	--signaux pour la gestion de la MAE
87	type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate, putdata,getdata,WinCompleted,finalize,st_timeout);
88	signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
89	signal count,count_i : natural range 0 to 15:=0;
90
91
92	signal RunState : typ_mae;
93	signal Ram_busy :std_logic:='0';
94	begin
95	Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN)
96	PORT MAP(
97	clka =>clk,
98	clkb => clk,
99	wea => ram_we,
100	ena => ram_ena,
101	enb => ram_enb,
102	addra => ram_addra,
103	addrb =>ram_addrb,
104	dia => ram_din,
105	dob => ram_do
106	);
107	--================================================================
108	--MUX de la RAM
109
110	Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr,
111	Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do,
112	Pe_ram_din,Pe_ram_we )
113	begin
114	case ramsel is
115
116	when '1' =>
117	ram_addra <= Core_ram_address_wr ;
118	ram_addrb <= Core_ram_address_rd ;
119	ram_ena <= Core_ram_en;
120	ram_enb <= Core_ram_en;
121	ram_we<= Core_ram_we;
122	ram_din <= Core_ram_data_in;
123	pe_ram_do<=(others=>'Z');
124	Core_ram_data_out<=ram_do;
125
126	when others =>
127	ram_addra <= pe_ram_addra;
128	ram_addrb <= pe_ram_addrb;
129	ram_ena <= pe_ram_ena;
130	ram_enb <= pe_ram_enb;
131	ram_we<= pe_ram_we;
132	ram_din <=pe_ram_din;
133	Core_ram_data_out<=(others=>'Z');
134	pe_ram_do<=ram_do;
135	end case ;
136	end process ;
137
138
139
140	Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --******A changer ********
141	--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce
142	-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!!
143	instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));
144
145	dpid<=dpid_i;
146
147	Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié
148	Lib_init<=Core_Pushout(4); -- Initialized
149	-- pe_hold_req<=Core_hold_req;
150	--Core_hold_ack<=pe_hold_ack;
151
152	hold:process (Core_Hold_Req,clk,reset)
153	begin
154	if rising_edge(clk) then
155	if reset='1' then
156	Core_Hold_Ack<='0';
157	else
158	if Core_Hold_Req='1' then
159
160	ramsel<=not(ram_busy);
161	Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération
162	Pe_hold_ack<=not(ram_busy);
163	else
164	Core_Hold_Ack<='0';
165	ramsel<='0';
166	Pe_hold_ack<='0';
167
168	end if;
169	end if;
170	end if;
171	end process hold;
172	--=======================================================================
173
174
175
176	--=======================================================================
177	--MAE du PE
178	--=======================================================================
179
180	pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do)
181
182	constant DATAPTR : natural :=256;
183	variable bfill,destrank,pid,mport : natural range 0 to 15;
184	variable fsrc,ret : natural range 0 to 15:=0;
185	variable timeout,ct,dlen : natural range 0 to 255;
186	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
187	variable mywin : Mpi_win;
188	variable iack : std_logic:='0';
189	variable adresse,adresse_rd :natural range 0 to 65536;
190	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
191	--=======================================================
192	--variables pour la création du fichier de résultats
193	-- synthesis translate_off
194	type char_file is file of character;
195	file f: text;
196	variable status :file_open_status ;
197	variable char_count: integer range 0 to 65536 := 0;
198	variable str: string (1 to 79) ;
199	variable L: line;
200	variable fopened: std_logic:='0';
201	-- synthesis translate_on
202	--======================================================
203	begin
204	--=== Partie combinatoire du process ===================================
205
206	--=== Fin de la partie combinatoire du process ==========================
207
208
209
210	--end loop;
211
212	if (clk'event and clk='1') then
213	Libr.Instr_ack<=Core_pushout(0);
214	Libr.InitOk<=Core_pushout(4);
215	Libr.Hold_Req<=Core_Hold_req;
216	Libr.Hold_Ack<=Pe_Hold_Ack;
217	Libr.RamSel<=RamSel;
218	sram.data_out<=PE_ram_do;
219
220	if reset='1' then
221	RunState<=start;
222
223	else
224
225	Libr.Instr_ack<=Core_pushout(0);
226	Libr.InitOk<=Core_pushout(4);
227	Libr.Hold_Req<=Core_Hold_req;
228	Libr.Hold_Ack<=Pe_Hold_Ack;
229	Libr.RamSel<=RamSel;
230	sram.data_out<=PE_ram_do;
231	case RunState is
232	when start =>
233	Dcount<=0;
234	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
235	RunState<=Fillmem;
236	end if;
237	Ram_busy<='0';
238	PE_Instr_En<='0';
239	iack:='0';
240	adresse:=DATAPTR;
241
242	adresse_rd:=0;
243	timeout:=0;
244	dcount<=0;
245	-- synthesis translate_off
246	if fopened='0' then
247	file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE);
248	--while not endfile(c_file_handle) loop
249	--end if;
250
251	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
252	--report l.all;
253	-- writeline (f, l) ;
254	fopened:='1';
255	end if;
256	-- synthesis translate_on
257	when Fillmem =>
258	if Ramsel='0' then
259
260
261
262	PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
263	PE_Instr_En<='0';
264	dcount<=dcount+1;
265
266	if dcount=200 then
267	bfill:=bfill+1;
268
269	if bfill=4 then
270	RunState<=InitApp;
271	else
272	RunState<=nextfill;
273	end if;
274	else
275	adresse:=adresse+1;
276	RunState<=Fillmem;
277	end if;
278	else -- attente de la libéraion de la mémoire
279	timeout:=timeout+1;
280	if timeout=100 then
281	RunState<=st_timeout;
282	end if;
283
284	end if;
285	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
286	adresse:=200*bfill;
287	dcount<=0;
288	ct:=0;
289	RunState<=Fillmem;
290	PE_Instr_En<='0';
291	when InitApp =>
292	--code pour Init
293	dlen:=251;
294	if ct=0 then
295	-- synthesis translate_off
296	write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & time'image(now)));
297
298	report l.all;
299	writeline (f, l) ;
300	-- synthesis translate_on
301	end if;
302	pMPI_Init(ct,Libr,Clk,SRam);
303	PE_Instr_EN<=Libr.instr_en;
304	adresse:=to_integer(unsigned(sram.addr_wr));
305	adresse_rd:=to_integer(unsigned(sram.addr_rd));
306	PE_ram_din<=sram.data_in;
307
308	--if Libr.InitOk='1' then
309	if ct=0 then
310	RunState<=GetRank;
311	-- synthesis translate_off
312	write (l,string'("Dlen; ;INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
313	report l.all;
314	writeline (f, l) ;
315	-- synthesis translate_on
316	end if;
317
318
319
320	when GetRank =>
321	if ct=0 then
322	-- synthesis translate_off
323	write (l,string'("Dlen; ;Rank1 " & integer'image(Dlen) & "; ; started ; " & time'image(now)));
324	report l.all;
325	writeline (f, l) ;
326	-- synthesis translate_on
327	end if;
328	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
329	adresse_rd:=to_integer(unsigned(sram.addr_rd));
330	if ct=0 then
331	RunState<=PutData;
332	-- synthesis translate_off
333	write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
334	report l.all;
335	writeline (f, l) ;
336	-- synthesis translate_on
337	end if;
338
339
340	when Wincreate =>
341
342
343	when putdata => --construire le packet pour le Put
344
345	--dlen:=251; ---
346	if ct=0 then
347	-- synthesis translate_off
348	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));
349	report l.all;
350	writeline (f, l) ;
351	-- synthesis translate_on
352	end if;
353	if unsigned(MyRank) = 0 then
354	Destrank:=2;
355
356	elsif unsigned(MyRank) = 1 then
357	Destrank:=0;
358	elsif unsigned(MyRank) = 2 then
359	Destrank:=1;
360	elsif unsigned(MyRank) = 3 then
361	Destrank:=2;
362	else
363	DestRank:=0;
364	end if;
365
366	SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
367	DestAdr:=X"2000";
368	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
369
370	adresse:=to_integer(unsigned(sram.addr_wr));
371	adresse_rd:=to_integer(unsigned(sram.addr_rd));
372	PE_Instr_EN<=Libr.instr_en;
373	PE_ram_din<=sram.data_in;
374	dcount<=ct;
375
376	if ct=0 then
377	RunState<=GetData;
378	-- synthesis translate_off
379	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now);
380	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & time'image(now)));
381	report l.all;
382	writeline (f, l) ;
383	-- synthesis translate_on
384	end if;
385
386
387	when getdata => --positionnement du mot de longueur des données
388	--dlen:=251; ---
389	if ct=0 then
390	-- synthesis translate_off
391	write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & time'image(now)));
392	report l.all;
393	writeline (f, l) ;
394	-- synthesis translate_on
395	end if;
396
397	SrcAdr:=X"0120";
398	DestAdr:=X"4000";
399	if unsigned(MyRank) /= 2 then
400	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
401	else
402	RunState<=wincompleted;
403	end if;
404	adresse:=to_integer(unsigned(sram.addr_wr));
405	adresse_rd:=to_integer(unsigned(sram.addr_rd));
406	PE_Instr_EN<=Libr.instr_en;
407	PE_ram_din<=sram.data_in;
408	dcount<=ct;
409
410	if ct=0 then
411	RunState<=wincompleted;
412	-- synthesis translate_off
413	assert ct/=0 report "GET_END " & integer'image(destrank)
414	severity Warning ;
415	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
416	report l.all;
417
418	writeline (f, l) ;
419	-- synthesis translate_on
420	end if;
421
422	when WinCompleted =>
423	if ct=0 then
424	-- synthesis translate_off
425	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));
426	report l.all;
427	writeline (f, l) ;
428	-- synthesis translate_on
429	end if;
430	pMPI_Win_wait(ct,Libr,sram,MyWin );
431	adresse:=to_integer(unsigned(sram.addr_wr));
432	adresse_rd:=to_integer(unsigned(sram.addr_rd));
433	if ct=0 then
434	RunState<=finalize;
435	-- synthesis translate_off
436	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
437	report l.all;
438	writeline (f, l) ;
439	-- synthesis translate_on
440
441	end if;
442
443
444	when finalize =>
445	if ct=0 then
446	-- synthesis translate_off
447	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));
448	report l.all;
449	writeline (f, l) ;
450	-- synthesis translate_on
451	end if;
452
453	if ct=0 then
454	RunState<=start;
455	-- synthesis translate_off
456	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));
457	report l.all;
458	writeline (f, l) ;
459	file_close(f);
460	-- synthesis translate_on
461	end if;
462
463	when st_timeout =>
464
465	--if ram_busy='1' then
466	RunState<=start;
467	--end if
468
469	RunState<=start;
470	end case;
471	pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
472	pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
473	end if;
474	end if;
475
476	end process pPutGet;
477
478	majPutGet:process (RunState,pe_ram_do,sram,Lib_Init)
479
480	begin
481	case RunState is
482	when start =>
483
484	PE_Ram_we<='0';
485	PE_Ram_ena<='0';
486	PE_Ram_enb<='0';
487	--PE_Instr_En<='0';
488
489	when fillmem =>
490	PE_Ram_we<='1';
491	PE_Ram_ena<='1';
492
493	PE_Ram_enb<='0';
494	--PE_Instr_En<='0';
495	when nextfill =>
496	PE_Ram_we<='1';
497	PE_Ram_ena<='1';
498	PE_Ram_enb<='0';
499
500	when InitApp =>
501	-- PE_Ram_we<='1';
502	-- PE_Ram_ena<='1';
503	-- PE_Ram_enb<='0';
504	PE_Ram_we<=sram.we;
505	PE_Ram_ena<=sram.ena;
506	PE_Ram_enb<=sram.enb;
507
508
509	when GetRank =>
510
511	PE_Ram_we<=sram.we;
512	PE_Ram_ena<=sram.ena;
513	PE_Ram_enb<=sram.enb;
514	when WinCreate =>
515
516	PE_Ram_we<=sram.we;
517	PE_Ram_ena<=sram.ena;
518	PE_Ram_enb<=sram.enb;
519
520
521	--positionnement du mot de longueur des données
522
523
524	when putdata =>
525	srcadr0<=X"00";
526	srcadr1<=X"01";
527	destadr0<=X"00";
528	destadr1<=X"02";
529	PE_Ram_we<=sram.we;
530	PE_Ram_ena<=sram.ena;
531	PE_Ram_enb<=sram.enb;
532
533	when getdata =>
534	PE_Ram_we<=sram.we;
535	PE_Ram_ena<=sram.ena;
536	PE_Ram_enb<=sram.enb;
537
538	when Wincompleted =>
539	PE_Ram_we<=sram.we;
540	PE_Ram_ena<=sram.ena;
541	PE_Ram_enb<=sram.enb;
542
543	when finalize =>
544
545	PE_Ram_we<='0';
546	PE_Ram_ena<='0';
547	PE_Ram_enb<='0';
548
549
550	when st_timeout =>
551	PE_Ram_we<='0';
552	PE_Ram_ena<='0';
553	PE_Ram_enb<='0';
554
555
556	end case;
557
558	end process majPutGet ;
559	end Behavioral;
560

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd @ 43

Download in other formats: