[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 18:33:31 03/05/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: RAM_32_32 - Behavioral |
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| 8 | -- Project Name: MPI_Core |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: permet de stocker les données locales de la librairie MPI |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | --use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity RAM_v is |
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| 34 | generic(width : positive:=32; Size:positive:=16); |
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| 35 | Port ( clka, clkb : in std_logic; |
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| 36 | wea : in std_logic; |
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| 37 | ena, enb : in std_logic; |
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| 38 | addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse |
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| 39 | dia : in std_logic_vector(width-1 downto 0); |
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| 40 | dob : out std_logic_vector(width-1 downto 0)); |
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| 41 | end RAM_v; |
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| 42 | |
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| 43 | architecture Behavioral of RAM_v is |
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| 44 | signal Lra,Lrb :std_logic:='0'; |
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| 45 | signal sel : std_logic_vector(1 downto 0); |
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| 46 | signal doa,dout : std_logic_vector(width-1 downto 0); |
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[41] | 47 | type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); |
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[15] | 48 | signal RAM: ram_type; |
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| 49 | begin |
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| 50 | process (clka) |
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| 51 | begin |
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| 52 | if clka'event and clka = '1' then |
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| 53 | if ena = '1' then |
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| 54 | if wea = '1' then |
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| 55 | RAM(conv_integer(addra)) <= dia; |
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| 56 | end if; |
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| 57 | |
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| 58 | doa<=RAM(conv_integer(addrb)); |
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| 59 | Lra<='1'; |
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| 60 | else |
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| 61 | if lrb='1' then |
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| 62 | Lra<='0'; |
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| 63 | end if; |
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| 64 | end if; |
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| 65 | end if; |
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| 66 | end process; |
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| 67 | |
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| 68 | |
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| 69 | process (clkb) |
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| 70 | begin |
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| 71 | if clkb'event and clkb = '1' then |
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| 72 | if enb = '1' then |
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| 73 | Lrb<='1'; |
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| 74 | dout <= RAM(conv_integer(addrb)) ; |
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| 75 | else |
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| 76 | if Lra='1' then |
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| 77 | Lrb<='0'; |
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| 78 | end if; |
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| 79 | end if; |
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| 80 | end if; |
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| 81 | end process; |
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| 82 | |
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| 83 | sel<=(Lra,Lrb); |
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| 84 | With sel select |
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| 85 | dob <=dout when "11", |
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| 86 | doa when "10", |
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| 87 | dout when "01", |
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| 88 | dout when "00", |
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| 89 | dout when others; |
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| 90 | |
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| 91 | end Behavioral; |
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| 92 | |
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