source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MultiMPITest.xreport

Last change on this file was 41, checked in by rolagamo, 12 years ago

Ceci est la version stable avant optimisation
File size: 21.0 KB
Line 
1<?xml version='1.0' encoding='UTF-8'?>
2<report-views version="2.0" >
3 <header>
4  <DateModified>2012-12-20T15:14:17</DateModified>
5  <ModuleName>SWITCH_GEN</ModuleName>
6  <SummaryTimeStamp>2012-12-19T17:00:46</SummaryTimeStamp>
7  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
8  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
9  <DateInitialized>2012-12-09T12:18:32</DateInitialized>
10  <EnableMessageFiltering>false</EnableMessageFiltering>
11 </header>
12 <body>
13  <viewgroup label="Design Overview" >
14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >
15    <toc-item title="Design Overview" target="Design Overview" />
16    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
17    <toc-item title="Performance Summary" target="Performance Summary" />
18    <toc-item title="Failing Constraints" target="Failing Constraints" />
19    <toc-item title="Detailed Reports" target="Detailed Reports" />
20    <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" />
21    <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" />
22    <table-item tableState="ExpandedTable" tableKey="DeviceUtilizationSummary" />
23    <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" />
24   </view>
25   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SWITCH_GEN_envsettings.html" label="System Settings" />
26   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" showConstraints="0" label="IOB Properties" />
27   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
28   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
29   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
30   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Pinout Report" />
31   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Clock Report" />
32   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
33   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
34   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
35  </viewgroup>
36  <viewgroup label="XPS Errors and Warnings" >
37   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
38   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
39   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
40   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
41  </viewgroup>
42  <viewgroup label="XPS Reports" >
43   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
44   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
45   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
46   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
47   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SWITCH_GEN.log" label="System Log File" />
48  </viewgroup>
49  <viewgroup label="Errors and Warnings" >
50   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
51   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" collate="1" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
52   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
53   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
54   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
55   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
56   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
57   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
58   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
59   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
60   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
61  </viewgroup>
62  <viewgroup label="Detailed Reports" >
63   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
64    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
65    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
66    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
67    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
68    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
69    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
70    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
71    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
72    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
73    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
74    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
75    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
76    <toc-item title="Partition Report" target="   Partition Report     " />
77    <toc-item title="Final Report" target="   Final Report   " />
78    <toc-item title="Design Summary" target="   Design Summary   " />
79    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
80    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
81    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
82    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
83    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
84    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
85    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
86    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
87    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
88   </view>
89   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
90   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
91   <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
92    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
93    <toc-item title="Command Line" target="Command Line:" />
94    <toc-item title="Partition Status" target="Partition Implementation Status" />
95    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
96   </view>
97   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
98    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
99    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
100    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
101    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
102    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
103    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
104    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
105    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
106    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
107    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
108    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
109    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
110    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
111    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
112   </view>
113   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
114    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
115    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
116    <toc-item title="Router Information" target="Starting Router" />
117    <toc-item title="Partition Status" target="Partition Implementation Status" />
118    <toc-item title="Clock Report" target="Generating Clock Report" />
119    <toc-item title="Timing Results" target="Timing Score:" />
120    <toc-item title="Final Summary" target="Peak Memory Usage:" />
121   </view>
122   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
123    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
124    <toc-item title="Timing Report Description" target="Device,package,speed:" />
125    <toc-item title="Informational Messages" target="INFO:" />
126    <toc-item title="Warning Messages" target="WARNING:" />
127    <toc-item title="Timing Constraints" target="Timing constraint:" />
128    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
129    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
130    <toc-item title="Timing Summary" target="Timing summary:" />
131    <toc-item title="Trace Settings" target="Trace Settings:" />
132   </view>
133   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
134    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
135    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
136    <toc-item title="Pin Resources" target="** Pin Resources **" />
137    <toc-item title="Global Resources" target="** Global Control Resources **" />
138   </view>
139   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
140    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
141    <toc-item title="Performance Summary" target="Performance Summary:" />
142   </view>
143   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
144    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
145    <toc-item title="Power summary" target="Power summary" />
146    <toc-item title="Thermal summary" target="Thermal summary" />
147   </view>
148   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
149    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
150    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
151    <toc-item title="Final Summary" target="DRC detected" />
152   </view>
153  </viewgroup>
154  <viewgroup label="Secondary Reports" >
155   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
156   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
157    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
158   </view>
159   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
160    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
161   </view>
162   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
163   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
164    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
165    <toc-item title="Design Information" target="Design Information" />
166    <toc-item title="Design Summary" target="Design Summary" />
167   </view>
168   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
169   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" >
170    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
171    <toc-item title="Timing Report Description" target="Device,package,speed:" />
172    <toc-item title="Informational Messages" target="INFO:" />
173    <toc-item title="Warning Messages" target="WARNING:" />
174    <toc-item title="Timing Constraints" target="Timing constraint:" />
175    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
176    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
177    <toc-item title="Timing Summary" target="Timing summary:" />
178    <toc-item title="Trace Settings" target="Trace Settings:" />
179   </view>
180   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
181   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" >
182    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
183   </view>
184   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
185    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
186   </view>
187   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
188    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
189   </view>
190   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >
191    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
192   </view>
193   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
194   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
195   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >
197    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
198   </view>
199   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
200   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
202    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
203   </view>
204   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
205    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
206    <toc-item title="Component" target="Component " />
207   </view>
208   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
209    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
210    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
211   </view>
212   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
213    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
214    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
215   </view>
216   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
217   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
218   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
219  </viewgroup>
220 </body>
221</report-views>
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