Ignore:
Timestamp:
Dec 20, 2012, 3:42:20 PM (12 years ago)
Author:
rolagamo
Message:

Ceci est la version stable avant optimisation

File:
1 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MultiMPITest.xreport

    r39 r41  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2012-12-05T03:48:30</DateModified>
    5   <ModuleName>MultiMPITest</ModuleName>
    6   <SummaryTimeStamp>2012-11-05T16:48:15</SummaryTimeStamp>
     4  <DateModified>2012-12-20T15:14:17</DateModified>
     5  <ModuleName>SWITCH_GEN</ModuleName>
     6  <SummaryTimeStamp>2012-12-19T17:00:46</SummaryTimeStamp>
    77  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
    88  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
    9   <DateInitialized>2012-11-05T16:59:29</DateInitialized>
     9  <DateInitialized>2012-12-09T12:18:32</DateInitialized>
    1010  <EnableMessageFiltering>false</EnableMessageFiltering>
    1111 </header>
    1212 <body>
    1313  <viewgroup label="Design Overview" >
    14    <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="MultiMPITest_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >
     14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="true" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" ExpandClockNets="true" ExpandWarnings="true" >
    1515    <toc-item title="Design Overview" target="Design Overview" />
    1616    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    … …  
    1818    <toc-item title="Failing Constraints" target="Failing Constraints" />
    1919    <toc-item title="Detailed Reports" target="Detailed Reports" />
    20    </view>
    21    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="MultiMPITest_envsettings.html" label="System Settings" />
    22    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="MultiMPITest_map.xrpt" label="IOB Properties" />
    23    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="MultiMPITest_map.xrpt" label="Control Set Information" />
    24    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="MultiMPITest_map.xrpt" label="Module Level Utilization" />
    25    <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="MultiMPITest.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
    26    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="MultiMPITest_par.xrpt" label="Pinout Report" />
    27    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="MultiMPITest_par.xrpt" showConstraints="0" label="Clock Report" />
    28    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="MultiMPITest.twx" label="Static Timing" />
    29    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MultiMPITest_html/fit/report.htm" label="CPLD Fitter Report" />
    30    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MultiMPITest_html/tim/report.htm" label="CPLD Timing Report" />
     20    <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" />
     21    <table-item tableState="CollapsedTable" tableKey="CurrentWarnings" />
     22    <table-item tableState="ExpandedTable" tableKey="DeviceUtilizationSummary" />
     23    <table-item tableState="CollapsedTable" tableKey="DeviceUtilizationSummary" />
     24   </view>
     25   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SWITCH_GEN_envsettings.html" label="System Settings" />
     26   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" showConstraints="0" label="IOB Properties" />
     27   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
     28   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
     29   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
     30   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Pinout Report" />
     31   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" showConstraints="0" label="Clock Report" />
     32   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
     33   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
     34   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
    3135  </viewgroup>
    3236  <viewgroup label="XPS Errors and Warnings" >
    … …  
    4145   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
    4246   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
    43    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="MultiMPITest.log" label="System Log File" />
     47   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SWITCH_GEN.log" label="System Log File" />
    4448  </viewgroup>
    4549  <viewgroup label="Errors and Warnings" >
    … …  
    5761  </viewgroup>
    5862  <viewgroup label="Detailed Reports" >
    59    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="MultiMPITest.syr" label="Synthesis Report" >
     63   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
    6064    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
    6165    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
    … …  
    8387    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
    8488   </view>
    85    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.srr" label="Synplify Report" />
    86    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.prec_log" label="Precision Report" />
    87    <view inputState="Synthesized" program="ngdbuild" type="Report" file="MultiMPITest.bld" label="Translation Report" >
     89   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
     90   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
     91   <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
    8892    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    8993    <toc-item title="Command Line" target="Command Line:" />
    … …  
    9195    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
    9296   </view>
    93    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest_map.mrp" label="Map Report" >
     97   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
    9498    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    9599    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    … …  
    107111    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
    108112   </view>
    109    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.par" label="Place and Route Report" >
     113   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
    110114    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    111115    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    … …  
    116120    <toc-item title="Final Summary" target="Peak Memory Usage:" />
    117121   </view>
    118    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.twr" label="Post-PAR Static Timing Report" >
     122   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
    119123    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    120124    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    127131    <toc-item title="Trace Settings" target="Trace Settings:" />
    128132   </view>
    129    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.rpt" label="CPLD Fitter Report (Text)" >
     133   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
    130134    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    131135    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    … …  
    133137    <toc-item title="Global Resources" target="** Global Control Resources **" />
    134138   </view>
    135    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.tim" label="CPLD Timing Report (Text)" >
     139   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
    136140    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    137141    <toc-item title="Performance Summary" target="Performance Summary:" />
    138142   </view>
    139    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="MultiMPITest.pwr" label="Power Report" >
     143   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
    140144    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    141145    <toc-item title="Power summary" target="Power summary" />
    142146    <toc-item title="Thermal summary" target="Thermal summary" />
    143147   </view>
    144    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.bgn" label="Bitgen Report" >
     148   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
    145149    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    146150    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    … …  
    150154  <viewgroup label="Secondary Reports" >
    151155   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
    152    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/MultiMPITest_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    153     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    154    </view>
    155    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/MultiMPITest_translate.nlf" label="Post-Translate Simulation Model Report" >
    156     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    157    </view>
    158    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
    159    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MultiMPITest_map.map" label="Map Log File" >
     156   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
     157    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     158   </view>
     159   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
     160    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     161   </view>
     162   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
     163   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
    160164    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    161165    <toc-item title="Design Information" target="Design Information" />
    … …  
    163167   </view>
    164168   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
    165    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_preroute.twr" label="Post-Map Static Timing Report" >
     169   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" >
    166170    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    167171    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    174178    <toc-item title="Trace Settings" target="Trace Settings:" />
    175179   </view>
    176    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/MultiMPITest_map.nlf" label="Post-Map Simulation Model Report" />
    177    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_map.psr" label="Physical Synthesis Report" >
    178     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    179    </view>
    180    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="MultiMPITest_pad.txt" label="Pad Report" >
    181     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    182    </view>
    183    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MultiMPITest.unroutes" label="Unroutes Report" >
    184     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    185    </view>
    186    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    187     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    188    </view>
    189    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.grf" label="Guide Results Report" />
    190    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.dly" label="Asynchronous Delay Report" />
    191    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.clk_rgn" label="Clock Region Report" />
    192    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.tsi" label="Post-Place and Route Constraints Interaction Report" >
    193     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    194    </view>
    195    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    196    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/MultiMPITest_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    197    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_sta.nlf" label="Primetime Netlist Report" >
    198     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    199    </view>
    200    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.ibs" label="IBIS Model" >
     180   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
     181   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" >
     182    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     183   </view>
     184   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
     185    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     186   </view>
     187   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
     188    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     189   </view>
     190   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     191    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     192   </view>
     193   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
     194   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
     195   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >
     197    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     198   </view>
     199   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     200   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
     202    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     203   </view>
     204   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
    201205    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    202206    <toc-item title="Component" target="Component " />
    203207   </view>
    204    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lck" label="Back-annotate Pin Report" >
     208   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
    205209    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    206210    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    207211   </view>
    208    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lpc" label="Locked Pin Constraints" >
     212   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
    209213    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    210214    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    211215   </view>
    212    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/MultiMPITest_timesim.nlf" label="Post-Fit Simulation Model Report" />
     216   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
    213217   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    214218   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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