1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer:GAMOM /KIEGAING |
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4 | -- |
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5 | -- Create Date: 08:12:29 06/16/2011 |
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6 | -- Design Name: |
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7 | -- Module Name: EX1_FSM - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: Ce module est chargé de recevoir les instructions du programme MPI et |
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12 | -- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC |
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13 | -- (GET) |
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14 | -- |
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15 | -- Dependencies: |
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16 | -- |
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17 | -- Revision: 09/07/2012 |
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18 | -- Revision 0.03 - File updated |
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19 | -- Additional Comments: |
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20 | -- |
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21 | ---------------------------------------------------------------------------------- |
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22 | library IEEE; |
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23 | use IEEE.STD_LOGIC_1164.ALL; |
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24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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26 | library NocLib ; |
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27 | use Work.Packet_type.ALL; |
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28 | USE ieee.numeric_std.ALL; |
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29 | |
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30 | |
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31 | use NocLib.CoreTypes.all; |
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32 | ---- Uncomment the following library declaration if instantiating |
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33 | ---- any Xilinx primitives in this code. |
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34 | --library UNISIM; |
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35 | --use UNISIM.VComponents.all; |
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36 | |
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37 | entity EX1_FSM is |
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38 | -- parametres generiques du module : |
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39 | |
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40 | |
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41 | Port ( |
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42 | --instruction_available : in STD_LOGIC; |
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43 | clk : in STD_LOGIC; |
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44 | reset : in STD_LOGIC; |
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45 | |
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46 | instruction_en : in std_logic:='0'; -- active le module instruction |
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47 | pid : in std_logic_vector(3 downto 0) ; -- id du processeur |
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48 | nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 |
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49 | Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module |
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50 | AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application |
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51 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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52 | Initialized:in std_logic ; -- état de la Lib |
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53 | -- Accès au Fifo d'instructions |
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54 | priority_rotation : out STD_LOGIC:='0'; |
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55 | fifo_rd_en : out STD_LOGIC:='0'; |
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56 | fifo_empty : in STD_LOGIC; |
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57 | fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); |
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58 | fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service |
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59 | |
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60 | -- Accès au réseau sur puce |
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61 | switch_port_in_full : in std_logic; |
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62 | switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'Z'); |
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63 | switch_port_in_wr_en : out STD_LOGIC:='0'; |
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64 | -- Accès à la mémoire RAM du PE |
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65 | ram_data_in : in std_logic_vector(7 downto 0); |
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66 | ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); |
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67 | ram_rd,ram_wr : out std_logic:='0'; |
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68 | ram_address : out std_logic_vector(15 downto 0):=(others=>'Z'); |
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69 | |
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70 | dma_wr_request : OUT std_logic:='0'; |
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71 | dma_rd_request : OUT std_logic:='0'; |
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72 | dma_wr_grant : in STD_LOGIC; |
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73 | dma_rd_grant : in STD_LOGIC); |
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74 | end EX1_FSM; |
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75 | |
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76 | architecture Behavioral of EX1_FSM is |
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77 | -- definition du type etat pour le codage des etats des fsm |
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78 | type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, |
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79 | decode_packet_type2, read_status1,read_status2,execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4, |
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80 | execute_get1, execute_get2,execute_get3,execute_get4, execute_put1, execute_put2, execute_put3, execute_put4,execute_put5, |
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81 | execute_init1,execute_init2,execute_init3); |
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82 | -- machine a etat du module |
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83 | signal ex1_state_mach : fsm_states; |
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84 | |
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85 | -- les variables utilisées dans la fsm |
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86 | |
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87 | signal data_to_send : std_logic_vector(Word-1 downto 0); |
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88 | signal packet_type : std_logic_vector(3 downto 0); |
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89 | --signal dpid : std_logic_vector(3 downto 0); |
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90 | signal pid_counter : std_logic_vector(3 downto 0); |
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91 | signal packet_length : std_logic_vector(Word-1 downto 0); |
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92 | signal src_address : std_logic_vector(ADRLEN-1 downto 0); |
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93 | signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; |
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94 | --signal res_address : std_logic_vector(15 downto 0); |
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95 | signal dest_address : std_logic_vector(ADRLEN-1 downto 0); |
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96 | signal n : std_logic_vector(3 downto 0); |
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97 | signal len : std_logic_vector(Word-1 downto 0); |
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98 | |
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99 | begin |
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100 | -- connection des signaux avec les ports |
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101 | ram_address <= src_address; |
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102 | |
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103 | -- processus de transistion entre les etats |
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104 | fsm_nst_logic : process(clk) |
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105 | variable tempval : std_logic_vector(Word-1 downto 0); |
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106 | begin |
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107 | if rising_edge(clk) then |
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108 | if reset = '1' then |
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109 | ex1_state_mach <= fifo_select; |
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110 | else |
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111 | case ex1_state_mach is |
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112 | when fifo_select => if instruction_en='1' and fifo_empty ='0' then |
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113 | ex1_state_mach <= fetch_packet_type; |
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114 | else |
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115 | ex1_state_mach <= fifo_select; |
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116 | end if; |
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117 | --lecture du registre status de la mib MPI |
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118 | when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put |
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119 | ex1_state_mach <= read_status2; |
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120 | else |
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121 | ex1_state_mach <= read_status1; |
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122 | end if; |
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123 | src_address<=std_logic_vector(to_unsigned(core_base_adr,16)); |
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124 | when read_status2 => |
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125 | ex1_state_mach <= fifo_select; |
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126 | when fetch_packet_type => if fifo_empty ='1' then |
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127 | ex1_state_mach <= fifo_select; |
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128 | else |
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129 | packet_type <= fifo_data_out(7 downto 4); |
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130 | data_to_send <= fifo_data_out; |
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131 | ex1_state_mach <= decode_packet_type; |
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132 | end if; |
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133 | when decode_packet_type => |
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134 | if packet_type = MPI_PUT then |
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135 | packet_length <= fifo_data_out + 4; |
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136 | n <= "0000"; |
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137 | ex1_state_mach <= fetch_addresses; |
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138 | elsif packet_type = MPI_GET then |
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139 | len <= fifo_data_out; |
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140 | n <= "0000"; |
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141 | ex1_state_mach <= fetch_addresses; |
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142 | elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then |
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143 | packet_length <= "00000011"; -- = 3 |
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144 | pid_counter <= "0000"; |
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145 | ex1_state_mach <= execute_barrier1; |
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146 | elsif packet_type = MPI_INIT then |
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147 | ex1_state_mach<=execute_init1; |
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148 | else -- packet non reconnu |
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149 | if fifo_empty = '1' then |
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150 | ex1_state_mach <= fifo_select; |
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151 | else |
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152 | packet_type <= fifo_data_out(7 downto 4); --lire le prochain paquet |
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153 | data_to_send <= fifo_data_out; |
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154 | ex1_state_mach <= decode_packet_type;-- pas necessaire mais plus sure |
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155 | end if; |
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156 | end if; |
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157 | |
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158 | when fetch_addresses => if fifo_empty = '0' and n = 0 then |
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159 | src_address(15 downto 8) <= fifo_data_out; |
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160 | n <= n + 1; |
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161 | ex1_state_mach <= fetch_addresses; |
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162 | elsif fifo_empty = '0' and n = 1 then |
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163 | src_address(7 downto 0) <= fifo_data_out; |
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164 | n <= n + 1; |
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165 | ex1_state_mach <= fetch_addresses; |
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166 | elsif fifo_empty = '0' and n = 2 then |
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167 | dest_address(15 downto 8) <= fifo_data_out; |
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168 | n <= n + 1; |
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169 | ex1_state_mach <= fetch_addresses; |
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170 | elsif fifo_empty = '0' and n = 3 then |
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171 | dest_address(7 downto 0) <= fifo_data_out; |
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172 | n <= "0000"; |
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173 | ex1_state_mach <= decode_packet_type2; |
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174 | elsif fifo_empty='1' then |
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175 | ex1_state_mach <= fetch_addresses; --attendre les données manquantes |
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176 | else |
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177 | ex1_state_mach <= fifo_select; |
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178 | end if; |
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179 | when decode_packet_type2 => if packet_type = MPI_PUT then |
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180 | ex1_state_mach <= execute_put1; |
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181 | elsif packet_type = MPI_GET then |
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182 | ex1_state_mach <= execute_get1; |
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183 | end if; |
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184 | -- execution du mpi put |
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185 | when execute_put1 => if dma_rd_grant = '1' then |
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186 | ex1_state_mach <= execute_put2; |
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187 | else |
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188 | ex1_state_mach <= execute_put1; |
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189 | end if; |
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190 | Wr_ok<='0'; |
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191 | when execute_put2 => if switch_port_in_full = '0' and n = 0 then |
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192 | data_to_send <= packet_length; |
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193 | n <= n + 1; |
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194 | ex1_state_mach <= execute_put2; |
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195 | elsif switch_port_in_full = '0' and n = 1 then |
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196 | data_to_send <= dest_address(15 downto 8); |
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197 | n <= n + 1; |
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198 | ex1_state_mach <= execute_put2; |
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199 | elsif switch_port_in_full = '0' and n = 2 then |
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200 | data_to_send <= dest_address(7 downto 0); |
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201 | n <= n +1; |
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202 | ex1_state_mach <= execute_put2; |
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203 | elsif switch_port_in_full = '0' and n = 3 then |
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204 | packet_length <= packet_length - 4; |
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205 | ex1_state_mach <= execute_put3; |
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206 | Wr_ok<='0'; |
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207 | else |
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208 | ex1_state_mach <= execute_put2; |
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209 | end if; |
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210 | when execute_put3 => if unsigned(packet_length)>0 then |
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211 | if switch_port_in_full = '0' then |
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212 | packet_length <= packet_length - 1; |
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213 | src_address <= src_address + 1; |
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214 | ex1_state_mach <= execute_put3; |
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215 | Wr_Ok<='1'; |
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216 | else |
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217 | Wr_Ok<='0'; |
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218 | end if; |
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219 | else |
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220 | Wr_Ok<='0'; |
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221 | ex1_state_mach <= execute_put4; |
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222 | end if; |
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223 | when execute_put4 => if dma_rd_grant = '1' then -- fin du mpi_put |
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224 | ex1_state_mach <= execute_put5; |
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225 | n<="0000"; |
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226 | data_to_send<="00000001"; |
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227 | else |
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228 | ex1_state_mach <= execute_put4; |
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229 | end if; |
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230 | rd_ok<='1'; |
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231 | wr_ok<='0'; |
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232 | src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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233 | |
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234 | when execute_put5 => if n <6 then |
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235 | |
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236 | dma_wr<='1'; --demander un accès exclusif au bus |
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237 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
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238 | else |
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239 | dma_wr<='0'; |
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240 | dma_rd<='0'; |
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241 | end if; |
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242 | |
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243 | if n=0 then |
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244 | if dma_rd_grant='1' then |
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245 | n<=n+1; |
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246 | |
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247 | end if; |
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248 | rd_ok<='1'; |
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249 | wr_ok<='0'; |
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250 | dma_wr<='1'; |
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251 | dma_rd<='1'; |
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252 | elsif n=1 then |
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253 | if dma_rd_grant='1' then |
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254 | n<=n+1; |
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255 | dma_wr<='1'; |
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256 | end if; |
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257 | rd_ok<='1'; |
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258 | wr_ok<='0'; |
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259 | |
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260 | dma_rd<='1'; |
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261 | elsif n=2 then |
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262 | if dma_rd_grant='1' and dma_wr_grant='1' then |
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263 | n<=n+1; |
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264 | tempval:=Ram_data_in; |
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265 | src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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266 | if fifo_src='0' then -- c'est un put qui est exécuté |
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267 | tempval(5):='1'; -- SET du bit DSENT |
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268 | else -- c'est un Get qui est exécuté |
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269 | tempval(2):='0'; --annuler le sending après un GET |
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270 | end if; |
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271 | data_to_send<=tempval; |
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272 | rd_ok<='0'; |
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273 | wr_ok<='1'; |
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274 | dma_wr<='1'; |
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275 | dma_rd<='1'; |
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276 | else |
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277 | rd_ok<='1'; |
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278 | wr_ok<='0'; |
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279 | dma_rd<='0'; --libérer le bus et revenir en arrière |
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280 | dma_wr<='0'; |
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281 | n<=n-1; |
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282 | end if; |
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283 | elsif n=3 then |
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284 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
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285 | n<=n+1; |
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286 | |
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287 | src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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288 | end if; |
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289 | rd_ok<='0'; |
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290 | wr_ok<='1'; |
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291 | dma_wr<='1'; |
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292 | dma_rd<='1'; |
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293 | elsif n=4 then |
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294 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
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295 | n<=n+1; |
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296 | |
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297 | src_address<=std_logic_vector(to_unsigned(core_put_adr+6,16)); |
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298 | |
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299 | end if; |
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300 | rd_ok<='0'; |
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301 | wr_ok<='1'; |
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302 | dma_wr<='1'; |
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303 | dma_rd<='0'; |
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304 | elsif n=5 then |
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305 | if dma_wr_grant = '1' then |
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306 | n<=n+1; |
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307 | |
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308 | -- SET du bit DSENT |
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309 | data_to_send<="00000001"; |
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310 | end if; |
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311 | rd_ok<='0'; |
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312 | wr_ok<='1'; |
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313 | dma_wr<='1'; |
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314 | dma_rd<='0'; |
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315 | elsif n=6 then |
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316 | n<="0000"; |
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317 | ex1_state_mach <= fifo_select; |
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318 | rd_ok<='0'; |
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319 | wr_ok<='0'; |
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320 | dma_wr<='0'; |
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321 | dma_rd<='0'; |
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322 | end if; |
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323 | |
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324 | |
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325 | when execute_get1 => if switch_port_in_full = '0' and n = 0 then -- execution du mpi get |
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326 | data_to_send <= "00001000"; -- longueur du paquet sur le réseau ? |
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327 | n <= n + 1; |
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328 | ex1_state_mach <= execute_get1; |
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329 | elsif switch_port_in_full = '0' and n = 1 then |
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330 | data_to_send <= "0000"&pid; -- Rang source |
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331 | n <= n + 1; |
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332 | ex1_state_mach <= execute_get1; |
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333 | elsif switch_port_in_full = '0' and n = 2 then |
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334 | data_to_send <= len; |
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335 | n <= n + 1; |
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336 | ex1_state_mach <= execute_get1; |
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337 | elsif switch_port_in_full = '0' and n = 3 then |
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338 | data_to_send <= src_address(15 downto 8); |
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339 | n <= n + 1; |
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340 | ex1_state_mach <= execute_get1; |
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341 | elsif switch_port_in_full = '0' and n = 4 then |
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342 | data_to_send <= src_address(7 downto 0); |
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343 | n <= n + 1; |
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344 | ex1_state_mach <= execute_get1; |
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345 | elsif switch_port_in_full = '0' and n = 5 then |
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346 | data_to_send <= dest_address(15 downto 8); |
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347 | n <= n + 1; |
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348 | ex1_state_mach <= execute_get1; |
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349 | elsif switch_port_in_full = '0' and n = 6 then |
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350 | data_to_send <= dest_address(7 downto 0); |
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351 | n <= n + 1; |
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352 | ex1_state_mach <= execute_get1; |
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353 | elsif switch_port_in_full = '0' and n = 7 then |
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354 | ex1_state_mach <= execute_get2; |
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355 | n<="0000"; |
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356 | else |
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357 | ex1_state_mach <= execute_get1; |
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358 | end if; |
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359 | when execute_get2 => if dma_wr_grant = '1' then |
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360 | ex1_state_mach <= execute_get3; |
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361 | src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16)); |
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362 | data_to_send<="00000001"; |
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363 | else |
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364 | ex1_state_mach <= execute_get2; |
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365 | wr_ok<='1'; |
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366 | end if; |
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367 | |
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368 | when execute_get3 => if dma_wr_grant = '1' then -- fin du post de mpi_get |
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369 | ex1_state_mach <= execute_get4; |
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370 | n<="0000"; |
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371 | data_to_send<="00000001"; |
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372 | wr_ok<='0'; |
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373 | rd_ok<='1'; |
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374 | else |
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375 | ex1_state_mach <= execute_get3; |
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376 | end if; |
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377 | src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16)); |
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378 | when execute_get4 => if n=0 then |
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379 | |
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380 | if dma_rd_grant='1' then |
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381 | n<=n+1; |
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382 | |
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383 | end if; |
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384 | rd_ok<='1'; |
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385 | wr_ok<='0'; |
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386 | dma_wr<='1'; |
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387 | dma_rd<='1'; |
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388 | elsif n=1 then |
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389 | src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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390 | if dma_rd_grant='1' then |
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391 | n<=n+1; |
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392 | |
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393 | end if; |
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394 | rd_ok<='1'; |
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395 | wr_ok<='0'; |
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396 | dma_wr<='1'; |
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397 | dma_rd<='1'; |
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398 | elsif n=2 then |
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399 | if dma_rd_grant='1' then |
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400 | n<=n+1; |
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401 | |
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402 | src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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403 | end if; |
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404 | dma_wr<='1'; |
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405 | dma_rd<='1'; |
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406 | elsif n=3 then |
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407 | if dma_rd_grant='1' and dma_wr_grant='1' then |
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408 | n<=n+1; |
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409 | tempval:=Ram_data_in; |
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410 | rd_ok<='0'; |
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411 | wr_ok<='1'; |
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412 | dma_wr<='1'; |
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413 | dma_rd<='1'; |
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414 | else |
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415 | dma_wr<='0'; |
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416 | dma_rd<='0'; |
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417 | n<=n-1; |
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418 | end if; |
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419 | src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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420 | elsif n=4 then |
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421 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
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422 | n<=n+1; |
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423 | |
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424 | --tempval(4):='0'; --RESET du bit DReceived |
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425 | tempval(1):='1'; -- SET du bit DReceiving |
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426 | data_to_send<=tempval; |
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427 | else |
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428 | rd_ok<='0'; |
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429 | wr_ok<='1'; |
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430 | end if; |
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431 | dma_wr<='1'; |
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432 | dma_rd<='1'; |
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433 | elsif n=5 then |
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434 | n<="0000"; |
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435 | ex1_state_mach <= fifo_select; |
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436 | dma_wr<='0'; |
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437 | dma_rd<='0'; |
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438 | end if; |
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439 | |
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440 | -- execution du barrier |
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441 | when execute_barrier1 => if switch_port_in_full = '0' then |
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442 | ex1_state_mach <= execute_barrier2; |
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443 | else |
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444 | ex1_state_mach <= execute_barrier1; |
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445 | end if; |
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446 | when execute_barrier2 => if switch_port_in_full = '0' then |
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447 | ex1_state_mach <= execute_barrier3; |
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448 | else |
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449 | ex1_state_mach <= execute_barrier2; |
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450 | end if; |
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451 | when execute_barrier3 => if switch_port_in_full = '0' then |
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452 | ex1_state_mach <= execute_barrier4; |
---|
453 | else |
---|
454 | ex1_state_mach <= execute_barrier3; |
---|
455 | end if; |
---|
456 | when execute_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then |
---|
457 | pid_counter <= pid_counter + 1; |
---|
458 | ex1_state_mach <= execute_barrier1; |
---|
459 | else |
---|
460 | ex1_state_mach <= fifo_select; |
---|
461 | end if; |
---|
462 | when execute_init1 => if Initialized='1' then |
---|
463 | ex1_state_mach<=execute_init2; |
---|
464 | end if; |
---|
465 | |
---|
466 | when execute_init2 => if dma_wr_grant = '1' then -- fin du mpi_init |
---|
467 | ex1_state_mach <= execute_init3; |
---|
468 | else |
---|
469 | ex1_state_mach <= execute_init2; |
---|
470 | end if; |
---|
471 | -- écriture dans le registre status reg. |
---|
472 | src_address<=std_logic_vector(to_unsigned(core_base_adr,16)); |
---|
473 | when execute_init3 =>if AppInitAck='1' then |
---|
474 | ex1_state_mach <= fifo_select; |
---|
475 | end if; |
---|
476 | when others => ex1_state_mach <= fifo_select; |
---|
477 | end case; |
---|
478 | end if; |
---|
479 | end if; |
---|
480 | end process; |
---|
481 | |
---|
482 | -- sortie de la machine à etat |
---|
483 | ex1_fsm_action : process(ex1_state_mach, fifo_empty, switch_port_in_full, packet_length,pid, |
---|
484 | pid_counter, ram_data_in,AppInitAck, data_to_send, packet_type, wr_ok) |
---|
485 | variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); |
---|
486 | begin |
---|
487 | -- code fonctionnel |
---|
488 | case ex1_state_mach is |
---|
489 | when fifo_select => priority_rotation <='1'; -- on peut changer la priorité |
---|
490 | fifo_rd_en <= '0'; |
---|
491 | switch_port_in_data <= (others =>'Z'); |
---|
492 | switch_port_in_wr_en <= '0'; |
---|
493 | dma_rd_request <= '0'; |
---|
494 | dma_wr_request <= '0'; |
---|
495 | Ram_rd<='0'; |
---|
496 | Ram_wr<='0'; |
---|
497 | Ram_data_out<=(others=>'0'); |
---|
498 | AppInitReq<='0'; |
---|
499 | Result <=(others=>'0'); |
---|
500 | when read_status1 => priority_rotation <='0'; |
---|
501 | fifo_rd_en <= '0'; |
---|
502 | switch_port_in_data <= (others =>'Z'); |
---|
503 | switch_port_in_wr_en <= '0'; |
---|
504 | dma_rd_request <= '1'; |
---|
505 | dma_wr_request <= '0'; |
---|
506 | Ram_rd<='0'; |
---|
507 | Ram_wr<='0'; |
---|
508 | Ram_data_out<=(others=>'0'); |
---|
509 | AppInitReq<='0'; |
---|
510 | Result <=(others=>'0'); |
---|
511 | when read_status2 => priority_rotation <='0'; |
---|
512 | fifo_rd_en <= '0'; |
---|
513 | switch_port_in_data <= (others =>'Z'); |
---|
514 | switch_port_in_wr_en <= '0'; |
---|
515 | dma_rd_request <= '1'; |
---|
516 | dma_wr_request <= '0'; |
---|
517 | Ram_rd<='1'; |
---|
518 | Ram_wr<='0'; |
---|
519 | Ram_data_out<=(others=>'0'); |
---|
520 | AppInitReq<='0'; |
---|
521 | status_reg:=Ram_data_in; |
---|
522 | Result <=(others=>'0'); |
---|
523 | when fetch_packet_type => priority_rotation <='0'; |
---|
524 | fifo_rd_en <= not(fifo_empty); |
---|
525 | switch_port_in_data <= (others =>'Z'); |
---|
526 | AppInitReq<='0'; |
---|
527 | switch_port_in_wr_en <= '0'; |
---|
528 | Ram_rd<='0'; |
---|
529 | Ram_wr<='0'; |
---|
530 | dma_rd_request <= '0'; |
---|
531 | dma_wr_request <= '0'; |
---|
532 | Ram_data_out<=(others=>'0'); |
---|
533 | Result <=(others=>'0'); |
---|
534 | |
---|
535 | when decode_packet_type => priority_rotation <='0'; |
---|
536 | fifo_rd_en <= not(fifo_empty); |
---|
537 | switch_port_in_data <= (others =>'Z'); |
---|
538 | switch_port_in_wr_en <= '0'; |
---|
539 | AppInitReq<='0'; |
---|
540 | Ram_rd<='0'; |
---|
541 | Ram_wr<='0'; |
---|
542 | dma_rd_request <= '0'; |
---|
543 | dma_wr_request <= '0'; |
---|
544 | Ram_data_out<=(others=>'0'); |
---|
545 | Result <=(others=>'0'); |
---|
546 | |
---|
547 | when fetch_addresses => priority_rotation <='0'; |
---|
548 | fifo_rd_en <= not(fifo_empty); |
---|
549 | switch_port_in_data <= (others =>'Z'); |
---|
550 | switch_port_in_wr_en <= '0'; |
---|
551 | AppInitReq<='0'; |
---|
552 | Ram_rd<='0'; |
---|
553 | Ram_wr<='0'; |
---|
554 | dma_rd_request <= '0'; |
---|
555 | dma_wr_request <= '0'; |
---|
556 | Ram_data_out<=(others=>'0'); |
---|
557 | Result <=(others=>'0'); |
---|
558 | |
---|
559 | when decode_packet_type2 =>priority_rotation <='0'; |
---|
560 | fifo_rd_en <= '0'; |
---|
561 | switch_port_in_data <= data_to_send; |
---|
562 | switch_port_in_wr_en <= '0'; |
---|
563 | AppInitReq<='0'; |
---|
564 | Ram_rd<='0'; |
---|
565 | Ram_wr<='0'; |
---|
566 | dma_rd_request <= '0'; |
---|
567 | dma_wr_request <= '0'; |
---|
568 | Ram_data_out<=(others=>'0'); |
---|
569 | Result <=(others=>'0'); |
---|
570 | |
---|
571 | when execute_barrier1 => priority_rotation <='0'; |
---|
572 | fifo_rd_en <= '0'; |
---|
573 | switch_port_in_data <= packet_type & pid_counter; |
---|
574 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
575 | AppInitReq<='0'; |
---|
576 | Ram_rd<='0'; |
---|
577 | Ram_wr<='0'; |
---|
578 | dma_rd_request <= '0'; |
---|
579 | dma_wr_request <= '0'; |
---|
580 | Ram_data_out<=(others=>'0'); |
---|
581 | Result <=(others=>'0'); |
---|
582 | |
---|
583 | when execute_barrier2 => priority_rotation <='0'; |
---|
584 | fifo_rd_en <= '0'; |
---|
585 | switch_port_in_data <= packet_length; |
---|
586 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
587 | AppInitReq<='0'; |
---|
588 | Ram_rd<='0'; |
---|
589 | Ram_wr<='0'; |
---|
590 | dma_rd_request <= '0'; |
---|
591 | dma_wr_request <= '0'; |
---|
592 | Ram_data_out<=(others=>'0'); |
---|
593 | Result <=(others=>'0'); |
---|
594 | |
---|
595 | when execute_barrier3 => priority_rotation <='0'; |
---|
596 | fifo_rd_en <= '0'; |
---|
597 | switch_port_in_data <= "0000" & pid; |
---|
598 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
599 | AppInitReq<='0'; |
---|
600 | Ram_rd<='0'; |
---|
601 | Ram_wr<='0'; |
---|
602 | dma_rd_request <= '0'; |
---|
603 | dma_wr_request <= '0'; |
---|
604 | Ram_data_out<=(others=>'0'); |
---|
605 | Result <=(others=>'0'); |
---|
606 | |
---|
607 | when execute_barrier4 => priority_rotation <='0'; |
---|
608 | fifo_rd_en <= '0'; |
---|
609 | switch_port_in_data <= "0000" & pid; |
---|
610 | switch_port_in_wr_en <= '0'; |
---|
611 | AppInitReq<='0'; |
---|
612 | dma_rd_request <= '0'; |
---|
613 | Ram_rd<='0'; |
---|
614 | Ram_wr<='0'; |
---|
615 | dma_wr_request <= '0'; |
---|
616 | Ram_data_out<=(others=>'0'); |
---|
617 | Result <=(others=>'0'); |
---|
618 | |
---|
619 | when execute_get1 => priority_rotation <='0'; |
---|
620 | fifo_rd_en <= '0'; |
---|
621 | switch_port_in_data <= data_to_send; |
---|
622 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
623 | AppInitReq<='0'; |
---|
624 | Ram_rd<='0'; |
---|
625 | Ram_wr<='0'; |
---|
626 | dma_rd_request <= '0'; |
---|
627 | dma_wr_request <= '0'; |
---|
628 | Ram_data_out<=(others=>'0'); |
---|
629 | Result <=(others=>'0'); |
---|
630 | |
---|
631 | when execute_get2 => priority_rotation <='0'; |
---|
632 | fifo_rd_en <= '0'; |
---|
633 | switch_port_in_data <= data_to_send; |
---|
634 | switch_port_in_wr_en <='0'; |
---|
635 | AppInitReq<='0'; |
---|
636 | Ram_rd<='0'; |
---|
637 | Ram_wr<='0'; |
---|
638 | dma_rd_request <= '0'; |
---|
639 | dma_wr_request <= Wr_ok; |
---|
640 | Ram_rd<='0'; |
---|
641 | Ram_wr<='0'; |
---|
642 | Ram_data_out<=(others=>'0'); |
---|
643 | Result <=(others=>'0'); |
---|
644 | |
---|
645 | |
---|
646 | when execute_get3 => priority_rotation <='0'; |
---|
647 | fifo_rd_en <= '0'; |
---|
648 | switch_port_in_data <= ram_data_in;---??? |
---|
649 | switch_port_in_wr_en <= '0'; |
---|
650 | AppInitReq<='0'; |
---|
651 | dma_rd_request <= '0'; |
---|
652 | dma_wr_request <= '1'; |
---|
653 | Ram_rd<='0'; |
---|
654 | Ram_wr<='1'; |
---|
655 | Ram_data_out<=data_to_send; -- le résultat de l'exécution |
---|
656 | --result(1)<='1'; |
---|
657 | Result <=(2=>'1',others=>'0');--Get completed |
---|
658 | when execute_get4 => priority_rotation <='0'; |
---|
659 | fifo_rd_en <= '0'; |
---|
660 | switch_port_in_data <= ram_Data_in; |
---|
661 | switch_port_in_wr_en <= '0'; |
---|
662 | AppInitReq<='0'; |
---|
663 | dma_rd_request <= dma_rd; |
---|
664 | dma_wr_request <= dma_wr; |
---|
665 | Ram_rd<=rd_ok; |
---|
666 | Ram_wr<=wr_ok; |
---|
667 | Ram_data_out<=data_to_send; --"00000001"; |
---|
668 | Result <=(2=>'1',others=>'0'); --get completed |
---|
669 | when execute_put1 => priority_rotation <='0'; |
---|
670 | fifo_rd_en <= '0'; |
---|
671 | switch_port_in_data <= data_to_send; |
---|
672 | switch_port_in_wr_en <= '0'; |
---|
673 | AppInitReq<='0'; |
---|
674 | dma_rd_request <= '1'; |
---|
675 | dma_wr_request <= '0'; |
---|
676 | Ram_rd<='0'; |
---|
677 | Ram_wr<='0'; |
---|
678 | Ram_data_out<=(others=>'0'); |
---|
679 | Result <=(others=>'0'); |
---|
680 | |
---|
681 | |
---|
682 | when execute_put2 => priority_rotation <='0'; |
---|
683 | fifo_rd_en <= '0'; |
---|
684 | switch_port_in_data <= data_to_send; |
---|
685 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
686 | AppInitReq<='0'; |
---|
687 | Ram_rd<='1'; |
---|
688 | Ram_wr<='0'; |
---|
689 | dma_rd_request <= '1'; |
---|
690 | dma_wr_request <= '0'; |
---|
691 | Ram_data_out<=(others=>'0'); |
---|
692 | Result <=(others=>'0'); |
---|
693 | |
---|
694 | when execute_put3 => priority_rotation <='0'; |
---|
695 | fifo_rd_en <= '0'; |
---|
696 | switch_port_in_data <= ram_data_in; |
---|
697 | switch_port_in_wr_en <= not(switch_port_in_full) and wr_ok; |
---|
698 | AppInitReq<='0'; |
---|
699 | dma_rd_request <= '1'; |
---|
700 | dma_wr_request <= '0'; |
---|
701 | Ram_rd<='1'; |
---|
702 | Ram_wr<='0'; |
---|
703 | Ram_data_out<=(others=>'0'); |
---|
704 | Result <=(others=>'0'); |
---|
705 | |
---|
706 | when execute_put4 => priority_rotation <='0'; |
---|
707 | fifo_rd_en <= '0'; |
---|
708 | switch_port_in_data <= ram_data_in;---??? |
---|
709 | switch_port_in_wr_en <= '0'; |
---|
710 | AppInitReq<='0'; |
---|
711 | dma_rd_request <= rd_ok; |
---|
712 | dma_wr_request <= wr_ok; |
---|
713 | Ram_rd<=rd_ok; |
---|
714 | Ram_wr<=wr_ok; |
---|
715 | Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution |
---|
716 | --result(1)<='1'; |
---|
717 | Result <=(1=>'1',others=>'0');--put completed |
---|
718 | when execute_put5 => priority_rotation <='0'; |
---|
719 | fifo_rd_en <= '0'; |
---|
720 | switch_port_in_data <= ram_Data_in; |
---|
721 | switch_port_in_wr_en <= '0'; |
---|
722 | AppInitReq<='0'; |
---|
723 | dma_rd_request <= dma_rd; |
---|
724 | dma_wr_request <= dma_wr; |
---|
725 | Ram_rd<=rd_ok; |
---|
726 | Ram_wr<=wr_ok; |
---|
727 | Ram_data_out<=data_to_send; --"00000001"; |
---|
728 | Result <=(1=>'1',others=>'0'); --put completed |
---|
729 | when execute_init1 => priority_rotation <='0'; |
---|
730 | fifo_rd_en <= '0'; |
---|
731 | switch_port_in_data <= (others =>'Z'); |
---|
732 | switch_port_in_wr_en <= '0'; |
---|
733 | dma_rd_request <= '0'; |
---|
734 | dma_wr_request <= '0'; |
---|
735 | Ram_rd<='0'; |
---|
736 | Ram_wr<='0'; |
---|
737 | Ram_data_out<=(others=>'0'); |
---|
738 | AppInitReq<='1'; |
---|
739 | Result <=(others=>'0'); |
---|
740 | |
---|
741 | when execute_init2=> priority_rotation <='0'; |
---|
742 | fifo_rd_en <= '0'; |
---|
743 | switch_port_in_data <= (others =>'Z'); |
---|
744 | switch_port_in_wr_en <= '0'; |
---|
745 | AppInitReq<='1'; |
---|
746 | dma_rd_request <= '0'; |
---|
747 | dma_wr_request <= '1'; |
---|
748 | Ram_rd<='0'; |
---|
749 | Ram_wr<='1'; |
---|
750 | Ram_data_out<="00010000"; -- le résultat de l'exécution |
---|
751 | -- dans le registre status |
---|
752 | Result <=(others=>'0');-- |
---|
753 | when execute_init3=> priority_rotation <='0'; |
---|
754 | fifo_rd_en <= '0'; |
---|
755 | switch_port_in_data <= ram_Data_in; |
---|
756 | switch_port_in_wr_en <= '0'; |
---|
757 | AppInitReq<='1'; |
---|
758 | dma_rd_request <= '0'; |
---|
759 | dma_wr_request <= '1'; |
---|
760 | Ram_rd<='0'; |
---|
761 | Ram_wr<='1'; |
---|
762 | Ram_data_out<="00010000"; |
---|
763 | Result<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit |
---|
764 | |
---|
765 | when others => priority_rotation <='0'; |
---|
766 | fifo_rd_en <= '0'; |
---|
767 | switch_port_in_data <= (others =>'Z'); |
---|
768 | switch_port_in_wr_en <= '0'; |
---|
769 | dma_rd_request <= '0'; |
---|
770 | dma_wr_request <= '0'; |
---|
771 | Ram_rd<='0'; |
---|
772 | Ram_wr<='0'; |
---|
773 | Ram_data_out<=(others=>'0'); |
---|
774 | AppInitReq<='0'; |
---|
775 | Result <=(others=>'0'); |
---|
776 | end case; |
---|
777 | |
---|
778 | end process; |
---|
779 | |
---|
780 | end Behavioral; |
---|
781 | |
---|