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Changeset 39 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd
- Timestamp:
- Dec 7, 2012, 11:31:34 AM (12 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd
r35 r39 56 56 fifo_empty : in STD_LOGIC; 57 57 fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); 58 fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service 58 59 59 60 -- Accès au réseau sur puce … … 90 91 signal packet_length : std_logic_vector(Word-1 downto 0); 91 92 signal src_address : std_logic_vector(ADRLEN-1 downto 0); 92 signal Wr_ok,rd_ok:std_logic:='0';93 signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; 93 94 --signal res_address : std_logic_vector(15 downto 0); 94 95 signal dest_address : std_logic_vector(ADRLEN-1 downto 0); … … 217 218 end if; 218 219 else 220 Wr_Ok<='0'; 219 221 ex1_state_mach <= execute_put4; 220 222 end if; 221 when execute_put4 => if dma_ wr_grant = '1' then -- fin du mpi_put223 when execute_put4 => if dma_rd_grant = '1' then -- fin du mpi_put 222 224 ex1_state_mach <= execute_put5; 223 225 n<="0000"; 224 226 data_to_send<="00000001"; 225 rd_ok<='1';226 wr_ok<='0';227 227 else 228 228 ex1_state_mach <= execute_put4; 229 229 end if; 230 rd_ok<='1'; 231 wr_ok<='0'; 230 232 src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 231 when execute_put5 => 232 if n=0 then 233 234 when execute_put5 => if n <6 then 235 236 dma_wr<='1'; --demander un accès exclusif au bus 237 dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données 238 else 239 dma_wr<='0'; 240 dma_rd<='0'; 241 end if; 242 243 if n=0 then 233 244 if dma_rd_grant='1' then 234 n<=n+1; 235 tempval:=Ram_data_in; 236 src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 237 tempval(5):='1'; -- SET du bit DSENT 238 data_to_send<=tempval; 239 245 n<=n+1; 246 240 247 end if; 241 248 rd_ok<='1'; 242 249 wr_ok<='0'; 250 dma_wr<='1'; 251 dma_rd<='1'; 243 252 elsif n=1 then 244 if dma_wr_grant = '1' then 253 if dma_rd_grant='1' then 254 n<=n+1; 255 dma_wr<='1'; 256 end if; 257 rd_ok<='1'; 258 wr_ok<='0'; 259 260 dma_rd<='1'; 261 elsif n=2 then 262 if dma_rd_grant='1' and dma_wr_grant='1' then 263 n<=n+1; 264 tempval:=Ram_data_in; 265 src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 266 if fifo_src='0' then -- c'est un put qui est exécuté 267 tempval(5):='1'; -- SET du bit DSENT 268 else -- c'est un Get qui est exécuté 269 tempval(2):='0'; --annuler le sending après un GET 270 end if; 271 data_to_send<=tempval; 272 rd_ok<='0'; 273 wr_ok<='1'; 274 dma_wr<='1'; 275 dma_rd<='1'; 276 else 277 rd_ok<='1'; 278 wr_ok<='0'; 279 dma_rd<='0'; --libérer le bus et revenir en arrière 280 dma_wr<='0'; 281 n<=n-1; 282 end if; 283 elsif n=3 then 284 if dma_wr_grant = '1' and dma_rd_grant='1' then 245 285 n<=n+1; 246 286 … … 249 289 rd_ok<='0'; 250 290 wr_ok<='1'; 251 elsif n=2 then 252 if dma_wr_grant = '1' then 291 dma_wr<='1'; 292 dma_rd<='1'; 293 elsif n=4 then 294 if dma_wr_grant = '1' and dma_rd_grant='1' then 253 295 n<=n+1; 254 296 … … 258 300 rd_ok<='0'; 259 301 wr_ok<='1'; 260 elsif n=3 then 302 dma_wr<='1'; 303 dma_rd<='0'; 304 elsif n=5 then 261 305 if dma_wr_grant = '1' then 262 306 n<=n+1; … … 267 311 rd_ok<='0'; 268 312 wr_ok<='1'; 269 elsif n=4 then 313 dma_wr<='1'; 314 dma_rd<='0'; 315 elsif n=6 then 270 316 n<="0000"; 271 317 ex1_state_mach <= fifo_select; 272 318 rd_ok<='0'; 273 319 wr_ok<='0'; 320 dma_wr<='0'; 321 dma_rd<='0'; 274 322 end if; 275 323 … … 302 350 data_to_send <= dest_address(7 downto 0); 303 351 n <= n + 1; 352 ex1_state_mach <= execute_get1; 353 elsif switch_port_in_full = '0' and n = 7 then 304 354 ex1_state_mach <= execute_get2; 355 n<="0000"; 305 356 else 306 357 ex1_state_mach <= execute_get1; 307 358 end if; 308 when execute_get2 => if switch_port_in_full = '0'then359 when execute_get2 => if dma_wr_grant = '1' then 309 360 ex1_state_mach <= execute_get3; 361 src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16)); 362 data_to_send<="00000001"; 310 363 else 311 364 ex1_state_mach <= execute_get2; 312 end if; 365 wr_ok<='1'; 366 end if; 367 313 368 when execute_get3 => if dma_wr_grant = '1' then -- fin du post de mpi_get 314 369 ex1_state_mach <= execute_get4; 315 370 n<="0000"; 316 371 data_to_send<="00000001"; 372 wr_ok<='0'; 373 rd_ok<='1'; 317 374 else 318 375 ex1_state_mach <= execute_get3; 319 376 end if; 320 377 src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16)); 321 when execute_get4 => 322 if n=0 then 323 if dma_rd_grant='1' then 324 n<=n+1; 325 tempval:=Ram_data_in; 378 when execute_get4 => if n=0 then 379 380 if dma_rd_grant='1' then 381 n<=n+1; 382 383 end if; 384 rd_ok<='1'; 385 wr_ok<='0'; 386 dma_wr<='1'; 387 dma_rd<='1'; 388 elsif n=1 then 389 src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 390 if dma_rd_grant='1' then 391 n<=n+1; 392 393 end if; 394 rd_ok<='1'; 395 wr_ok<='0'; 396 dma_wr<='1'; 397 dma_rd<='1'; 398 elsif n=2 then 399 if dma_rd_grant='1' then 400 n<=n+1; 401 326 402 src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 327 403 end if; 328 elsif n=1 then 329 n<=n+1; 404 dma_wr<='1'; 405 dma_rd<='1'; 406 elsif n=3 then 407 if dma_rd_grant='1' and dma_wr_grant='1' then 408 n<=n+1; 409 tempval:=Ram_data_in; 410 rd_ok<='0'; 411 wr_ok<='1'; 412 dma_wr<='1'; 413 dma_rd<='1'; 414 else 415 dma_wr<='0'; 416 dma_rd<='0'; 417 n<=n-1; 418 end if; 330 419 src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 331 elsif n= 2then332 if dma_wr_grant = '1' then420 elsif n=4 then 421 if dma_wr_grant = '1' and dma_rd_grant='1' then 333 422 n<=n+1; 334 423 335 tempval(4):='0'; --RESET du bit DReceived424 --tempval(4):='0'; --RESET du bit DReceived 336 425 tempval(1):='1'; -- SET du bit DReceiving 337 426 data_to_send<=tempval; 427 else 428 rd_ok<='0'; 429 wr_ok<='1'; 338 430 end if; 339 elsif n=3 then 431 dma_wr<='1'; 432 dma_rd<='1'; 433 elsif n=5 then 340 434 n<="0000"; 341 435 ex1_state_mach <= fifo_select; 436 dma_wr<='0'; 437 dma_rd<='0'; 342 438 end if; 343 439 … … 536 632 fifo_rd_en <= '0'; 537 633 switch_port_in_data <= data_to_send; 538 switch_port_in_wr_en <= not(switch_port_in_full);634 switch_port_in_wr_en <='0'; 539 635 AppInitReq<='0'; 540 636 Ram_rd<='0'; 541 637 Ram_wr<='0'; 542 638 dma_rd_request <= '0'; 543 dma_wr_request <= '0';639 dma_wr_request <= Wr_ok; 544 640 Ram_rd<='0'; 545 641 Ram_wr<='0'; … … 565 661 switch_port_in_wr_en <= '0'; 566 662 AppInitReq<='0'; 567 dma_rd_request <= '1';568 dma_wr_request <= '1';569 Ram_rd<= '1';570 Ram_wr<= '1';663 dma_rd_request <= dma_rd; 664 dma_wr_request <= dma_wr; 665 Ram_rd<=rd_ok; 666 Ram_wr<=wr_ok; 571 667 Ram_data_out<=data_to_send; --"00000001"; 572 668 Result <=(2=>'1',others=>'0'); --get completed … … 613 709 switch_port_in_wr_en <= '0'; 614 710 AppInitReq<='0'; 615 dma_rd_request <= '0';616 dma_wr_request <= '1';617 Ram_rd<= '0';618 Ram_wr<= '1';711 dma_rd_request <= rd_ok; 712 dma_wr_request <= wr_ok; 713 Ram_rd<=rd_ok; 714 Ram_wr<=wr_ok; 619 715 Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution 620 716 --result(1)<='1'; … … 625 721 switch_port_in_wr_en <= '0'; 626 722 AppInitReq<='0'; 627 dma_rd_request <= rd_ok;628 dma_wr_request <= wr_ok;723 dma_rd_request <= dma_rd; 724 dma_wr_request <= dma_wr; 629 725 Ram_rd<=rd_ok; 630 726 Ram_wr<=wr_ok;
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