[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: GRIIA - ETIS |
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| 3 | -- Engineer: GAMOM, KIEGAING |
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| 4 | -- |
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| 5 | -- Create Date: 01:02:10 06/17/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: EX2_FSM - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- machine a etat qui execute la reception des packet dans le core mpi |
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| 13 | -- Dependencies: |
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| 14 | --ss |
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| 15 | -- Revision: 26/01/2012 |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | library NocLib ; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.Numeric_std.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | use Work.Packet_type.ALL; |
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| 26 | use NocLib.CoreTypes.all; |
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| 27 | ---- Uncomment the following library declaration if instantiating |
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| 28 | ---- any Xilinx primitives in this code. |
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| 29 | --library UNISIM; |
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| 30 | --use UNISIM.VComponents.all; |
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| 31 | |
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| 32 | entity EX2_FSM is |
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| 33 | |
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| 34 | generic ( |
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| 35 | pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur |
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| 36 | nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 |
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| 37 | ); |
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| 38 | Port ( clk : in STD_LOGIC; |
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| 39 | reset : in STD_LOGIC; |
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| 40 | |
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| 41 | Instruction_en : in std_logic; |
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| 42 | |
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| 43 | dma_wr_grant : in STD_LOGIC; |
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| 44 | dma_wr_request : out STD_LOGIC; |
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| 45 | dma_rd_grant : in STD_LOGIC; |
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| 46 | dma_rd_request : out STD_LOGIC; |
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| 47 | ram_rd : out std_logic; |
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| 48 | ram_wr : out std_logic; |
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| 49 | ram_address : out std_logic_vector(ADRLEN-1 downto 0); |
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| 50 | Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 51 | Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 52 | |
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| 53 | fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 54 | fifo_wr_en : out STD_LOGIC; |
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| 55 | fifo_full : in STD_LOGIC; |
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| 56 | |
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| 57 | AppRank : in STD_LOGIC_VECTOR(3 downto 0); |
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| 58 | AppSize : in STD_LOGIC_VECTOR(3 downto 0); |
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| 59 | packet_received : out STD_LOGIC; |
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| 60 | packet_ack : in STD_LOGIC; |
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| 61 | barrier_completed : out STD_LOGIC; |
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| 62 | Ready : Out std_logic; |
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| 63 | AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application |
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| 64 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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| 65 | Initialized:in std_logic ; -- état de la Lib |
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| 66 | |
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| 67 | switch_data_available : in STD_LOGIC; |
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| 68 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 69 | switch_port_out_rd_en : out STD_LOGIC |
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| 70 | |
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| 71 | |
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| 72 | |
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| 73 | ); |
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| 74 | end EX2_FSM; |
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| 75 | |
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| 76 | architecture Behavioral of EX2_FSM is |
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| 77 | -- définition du type etat de la machine à etat |
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| 78 | type fsm_states is (fetch_packet_type, decode_packet_type, decode_packet_type2, |
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| 79 | fetch_addresses,execute_spawn,execute_put1,execute_put2,execute_put3 ,execute_put4, |
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| 80 | execute_put5,execute_get1, execute_get2,execute_get3,execute_get4, |
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| 81 | execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4, |
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| 82 | execute_barrier5, execute_barrier6, execute_barrier7,execute_init1,execute_init2); |
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| 83 | signal ex2_state_mach :fsm_states; |
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| 84 | -- machine a etat du module |
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| 85 | signal packet_type : std_logic_vector(3 downto 0); |
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| 86 | signal packet_length : std_logic_vector(Word-1 downto 0); |
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| 87 | signal barrier_counter : std_logic_vector(3 downto 0); |
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| 88 | signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 89 | signal n : std_logic_vector(3 downto 0); |
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| 90 | signal dest_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'Z'); |
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| 91 | signal data_to_write_fifo : std_logic_vector(Word-1 downto 0); |
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| 92 | signal Ex2_on : std_logic:='0'; |
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[39] | 93 | signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; |
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[15] | 94 | |
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| 95 | begin |
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| 96 | ram_address <= dest_address; |
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| 97 | fifo_data <= data_to_write_fifo; |
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| 98 | |
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| 99 | -- processus de transistion entre les etats |
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| 100 | fsm_nst_logic : process(clk) |
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| 101 | variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée |
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| 102 | variable tempval : std_logic_vector(Word-1 downto 0); |
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| 103 | begin |
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| 104 | if rising_edge(clk) then |
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| 105 | if reset = '1' then |
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| 106 | ex2_state_mach <= fetch_packet_type; |
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| 107 | Ex2_on<='0'; |
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| 108 | barrier_counter <= "0000"; |
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| 109 | else |
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| 110 | Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non |
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| 111 | case ex2_state_mach is |
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| 112 | when fetch_packet_type => if switch_data_available ='1' and Ex2_on='1' then --and initialized ='1' |
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| 113 | ex2_state_mach <= decode_packet_type; |
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| 114 | packet_type<=switch_port_out_data(7 downto 4); |
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| 115 | else |
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| 116 | ex2_state_mach <= fetch_packet_type; |
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| 117 | end if; |
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| 118 | when decode_packet_type => if switch_data_available ='0' then |
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| 119 | ex2_state_mach <= decode_packet_type; |
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| 120 | else |
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| 121 | if packet_type = MPI_PUT then |
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| 122 | packet_length <= switch_port_out_data - 2; |
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| 123 | n <="0000"; |
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| 124 | ex2_state_mach <= decode_packet_type2; |
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| 125 | elsif packet_type = MPI_GET then |
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| 126 | packet_length <=switch_port_out_data-2; |
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| 127 | ex2_state_mach <= decode_packet_type2; |
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| 128 | elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then |
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| 129 | packet_length <= switch_port_out_data; |
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| 130 | n <= "0000"; |
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| 131 | ex2_state_mach <= execute_barrier1; |
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| 132 | elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then |
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| 133 | ex2_state_mach <= execute_init1; |
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| 134 | else |
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| 135 | ex2_state_mach <= decode_packet_type; |
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| 136 | end if; |
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| 137 | end if; |
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| 138 | when decode_packet_type2 => if packet_type = MPI_PUT then |
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| 139 | ex2_state_mach <= fetch_addresses; |
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| 140 | else |
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| 141 | ex2_state_mach <= execute_get1; |
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| 142 | end if; |
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| 143 | when fetch_addresses => if switch_data_available = '1' and n = 0 then |
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| 144 | dest_address(15 downto 8) <= switch_port_out_data; |
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| 145 | n <= n + 1; |
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| 146 | ex2_state_mach <= fetch_addresses; |
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| 147 | elsif switch_data_available = '1' and n = 1 then |
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| 148 | dest_address(Word-1 downto 0) <= switch_port_out_data; |
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| 149 | packet_length <= packet_length - 2; |
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| 150 | ex2_state_mach <= execute_put1; |
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| 151 | else |
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| 152 | ex2_state_mach <= fetch_addresses; |
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| 153 | end if; |
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| 154 | -- execution du mpi Init |
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| 155 | when execute_init1 =>if Initialized='1' then |
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| 156 | ex2_state_mach<=execute_init2; |
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| 157 | end if; |
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| 158 | when execute_init2=> if AppInitAck='1' then |
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| 159 | ex2_state_mach<=fetch_packet_type; |
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| 160 | end if; |
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| 161 | when execute_put1 => if dma_wr_grant = '1' then |
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| 162 | ex2_state_mach <= execute_put2; |
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| 163 | data_to_ram<=switch_port_out_data; |
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| 164 | rd_ok<='1'; |
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| 165 | n<="0000"; |
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| 166 | delai:=0; |
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| 167 | else |
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| 168 | ex2_state_mach <= execute_put1; |
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| 169 | end if; |
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| 170 | when execute_put2 => if unsigned( packet_length) > 1 then |
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[39] | 171 | |
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[15] | 172 | if switch_data_available = '1' and dma_wr_grant='1' then |
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[39] | 173 | |
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[15] | 174 | packet_length <= packet_length - 1; |
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| 175 | dest_address <= dest_address + 1; |
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| 176 | ex2_state_mach <= execute_put2; |
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| 177 | rd_ok<='1'; |
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[39] | 178 | wr_ok<='1'; |
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[15] | 179 | data_to_ram<=switch_port_out_data; |
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[39] | 180 | else |
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| 181 | if switch_data_available = '1' and dma_wr_grant='0' then |
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[15] | 182 | if delai=0 then |
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[39] | 183 | data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch |
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[15] | 184 | end if; |
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| 185 | delai:=1;--indique qu'un temps supplémentaire est |
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| 186 | --nécessaire pour écrire la donnée en RAM |
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| 187 | end if; |
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| 188 | ex2_state_mach <= execute_put2; |
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[39] | 189 | rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données |
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| 190 | end if; |
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[15] | 191 | else |
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| 192 | if switch_data_available = '1' then |
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| 193 | --la dernière donnée à écrire en RAM |
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| 194 | data_to_ram<=switch_port_out_data; |
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[39] | 195 | rd_ok<='0'; |
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| 196 | wr_ok<='1'; |
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| 197 | else |
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| 198 | rd_ok<='1'; |
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| 199 | wr_ok<='0'; |
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[15] | 200 | end if; |
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| 201 | if dma_wr_grant='1' then |
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| 202 | |
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| 203 | ex2_state_mach <= execute_put3; |
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[39] | 204 | Wr_ok<='0'; |
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[15] | 205 | |
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| 206 | end if; |
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| 207 | end if; |
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| 208 | |
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| 209 | when execute_put3 => if dma_rd_grant='1' then |
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| 210 | dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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| 211 | ex2_state_mach <= execute_put4; |
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| 212 | n<="0000"; |
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| 213 | rd_ok<='1'; |
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| 214 | wr_ok<='0'; |
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| 215 | end if; |
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| 216 | |
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[39] | 217 | when execute_put4 => if n <=4 then |
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| 218 | |
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| 219 | dma_wr<='1'; --demander un accès exclusif au bus |
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| 220 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
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| 221 | else |
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| 222 | dma_wr<='0'; |
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| 223 | dma_rd<='0'; |
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| 224 | end if; |
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| 225 | if n=0 then |
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[15] | 226 | if dma_rd_grant='1' then |
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| 227 | n<=n+1; |
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[39] | 228 | else |
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| 229 | rd_ok<='1'; |
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| 230 | wr_ok<='0'; |
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[15] | 231 | end if; |
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[39] | 232 | elsif n=1 then |
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| 233 | if dma_rd_grant='1' then |
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| 234 | n<=n+1; |
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| 235 | else |
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[15] | 236 | rd_ok<='1'; |
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| 237 | wr_ok<='0'; |
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[39] | 238 | end if; |
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[15] | 239 | elsif n=2 then |
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[39] | 240 | if dma_rd_grant='1' then |
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| 241 | n<=n+1; |
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| 242 | tempval:=Ram_data_in; |
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| 243 | tempval(4):='1'; --SET du bit DReceived |
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[64] | 244 | tempval(1):='0'; --reset du bit DRING !! |
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[39] | 245 | data_to_ram<=tempval; |
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| 246 | rd_ok<='0'; |
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| 247 | wr_ok<='1'; |
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| 248 | else |
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| 249 | rd_ok<='1'; |
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| 250 | wr_ok<='0'; |
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| 251 | n<=n-1; |
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| 252 | end if; |
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| 253 | elsif n=3 then |
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[15] | 254 | if dma_wr_grant='1' then |
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| 255 | rd_ok<='0'; |
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| 256 | wr_ok<='1'; |
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[39] | 257 | n<=n+1; |
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| 258 | end if; |
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| 259 | elsif n=4 then |
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| 260 | if dma_wr_grant='1' then |
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| 261 | rd_ok<='0'; |
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| 262 | wr_ok<='1'; |
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[15] | 263 | ex2_state_mach <= execute_put5; |
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| 264 | n<="0000"; |
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| 265 | end if; |
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| 266 | end if; |
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| 267 | |
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| 268 | |
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| 269 | |
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| 270 | dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction |
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| 271 | when execute_put5 => |
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| 272 | ex2_state_mach <= fetch_packet_type; -- fin du mpi_put |
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| 273 | |
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| 274 | |
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| 275 | when execute_get1 => if switch_data_available = '1' then -- conversion du get en put en empilement dans le fifo |
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| 276 | data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0); |
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| 277 | packet_length <= packet_length - 1; |
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| 278 | ex2_state_mach <= execute_get2; |
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| 279 | wr_ok<='1'; |
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| 280 | end if; |
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[39] | 281 | when execute_get2 => if fifo_full = '0' and switch_data_available ='1' and packet_length > 0 then |
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[15] | 282 | data_to_write_fifo <= switch_port_out_data; |
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| 283 | packet_length <= packet_length - 1; |
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| 284 | ex2_state_mach <= execute_get2; |
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| 285 | wr_ok<='1'; |
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| 286 | elsif packet_length = 0 and switch_data_available ='1' then-- |
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| 287 | ex2_state_mach <= fetch_packet_type; |
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| 288 | wr_ok<='0'; |
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| 289 | else |
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| 290 | ex2_state_mach <= execute_get3; |
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| 291 | wr_ok<='0'; |
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| 292 | end if; |
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| 293 | when execute_get3 => if dma_rd_grant='1' then -- fin du mpi_put |
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| 294 | ex2_state_mach <= execute_get4; |
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| 295 | n<="0000"; |
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| 296 | --activer le bit sending du registre de transfert |
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| 297 | else |
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| 298 | ex2_state_mach <= execute_get3; |
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| 299 | end if; |
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| 300 | |
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| 301 | dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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[39] | 302 | when execute_get4 => if n <4 then |
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| 303 | |
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| 304 | dma_wr<='1'; --demander un accès exclusif au bus |
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| 305 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
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| 306 | else |
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| 307 | dma_wr<='0'; |
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| 308 | dma_rd<='0'; |
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| 309 | end if; |
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[15] | 310 | if n=0 then |
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[39] | 311 | if dma_rd_grant='1' then |
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| 312 | n<=n+1; |
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| 313 | |
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| 314 | end if; |
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| 315 | rd_ok<='1'; |
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| 316 | wr_ok<='0'; |
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| 317 | elsif n=1 then |
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| 318 | if dma_rd_grant='1' then |
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| 319 | n<=n+1; |
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| 320 | |
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| 321 | end if; |
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| 322 | rd_ok<='1'; |
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| 323 | wr_ok<='0'; |
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| 324 | |
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| 325 | elsif n=2 then |
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| 326 | if dma_rd_grant='1' and dma_wr_grant='1' then |
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[15] | 327 | n<=n+1; |
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| 328 | tempval:=Ram_data_in; |
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| 329 | tempval(2):='1'; --mise à 1 du Bit Dreceiving |
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[39] | 330 | --tempval(5):='0'; --Mise à 0 du Bit Sent |
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[15] | 331 | data_to_ram<=tempval; |
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[39] | 332 | rd_ok<='0'; |
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| 333 | wr_ok<='1'; |
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| 334 | else |
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[15] | 335 | rd_ok<='1'; |
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| 336 | wr_ok<='0'; |
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[39] | 337 | end if; |
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| 338 | |
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| 339 | elsif n=3 then |
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| 340 | if dma_wr_grant = '1' then |
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[15] | 341 | n<=n+1; |
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| 342 | rd_ok<='0'; |
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| 343 | wr_ok<='1'; |
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[39] | 344 | end if; |
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| 345 | elsif n=4 then |
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[15] | 346 | if dma_wr_grant = '1' then |
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| 347 | n<="0000"; |
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| 348 | ex2_state_mach <= fetch_packet_type; -- fin du mpi_get |
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[39] | 349 | else |
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| 350 | rd_ok<='0'; |
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| 351 | wr_ok<='1'; |
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| 352 | --n<=n-1; |
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| 353 | end if; |
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[15] | 354 | end if; |
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| 355 | |
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| 356 | |
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| 357 | dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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| 358 | -- execution du barrier |
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| 359 | when execute_barrier1 => if switch_data_available = '1' then |
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| 360 | pading_data <= switch_port_out_data; |
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| 361 | ex2_state_mach <= execute_barrier2; |
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| 362 | else |
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| 363 | ex2_state_mach <= execute_barrier1; |
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| 364 | end if; |
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| 365 | when execute_barrier2 => if packet_type = MPI_BARRIER_REACHED then |
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| 366 | barrier_counter <= barrier_counter + 1; |
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| 367 | ex2_state_mach <= execute_barrier4; |
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| 368 | else |
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| 369 | ex2_state_mach <= execute_barrier3; |
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| 370 | end if; |
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| 371 | when execute_barrier3 => if n < 10 then |
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| 372 | n <= n + 1; |
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| 373 | ex2_state_mach <= execute_barrier3; |
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| 374 | else |
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| 375 | ex2_state_mach <= fetch_packet_type; |
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| 376 | end if; |
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| 377 | when execute_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED |
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| 378 | data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000"; |
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| 379 | ex2_state_mach <= execute_barrier5; |
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| 380 | else |
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| 381 | ex2_state_mach <= fetch_packet_type; |
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| 382 | end if; |
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| 383 | when execute_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED |
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| 384 | data_to_write_fifo <= "00000011"; |
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| 385 | ex2_state_mach <= execute_barrier6; |
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| 386 | else |
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| 387 | ex2_state_mach <= execute_barrier5; |
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| 388 | end if; |
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| 389 | when execute_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED |
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| 390 | data_to_write_fifo <= "00000000"; |
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| 391 | ex2_state_mach <= execute_barrier7; |
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| 392 | else |
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| 393 | ex2_state_mach <= execute_barrier6; |
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| 394 | end if; |
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| 395 | when execute_barrier7 => if fifo_full = '0' then |
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| 396 | barrier_counter <= "0000"; |
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| 397 | ex2_state_mach <= fetch_packet_type; |
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| 398 | else |
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| 399 | ex2_state_mach <= execute_barrier7; |
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| 400 | end if; |
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| 401 | |
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| 402 | when others => ex2_state_mach <= fetch_packet_type; |
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| 403 | end case; |
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| 404 | end if; |
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| 405 | end if; |
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| 406 | end process; |
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| 407 | |
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| 408 | -- sortie de la machine à etat |
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| 409 | -- |
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| 410 | ex2_fsm_action : process(ex2_state_mach, fifo_full, packet_length, data_to_write_fifo, packet_type, |
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| 411 | switch_data_available,switch_port_out_data,Ram_data_in,rd_ok) |
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| 412 | variable transact : std_logic_vector(Word-1 downto 0); |
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| 413 | begin |
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| 414 | -- code fonctionnel |
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| 415 | case ex2_state_mach is |
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| 416 | |
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| 417 | when fetch_packet_type => fifo_wr_en <= '0'; |
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| 418 | switch_port_out_rd_en <= switch_data_available; |
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| 419 | packet_received <= '0'; |
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| 420 | dma_wr_request <= '0'; |
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| 421 | dma_rd_request <= '0'; |
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| 422 | barrier_completed <= '0'; |
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| 423 | Ram_data_out<=(others=>'Z'); |
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| 424 | Ram_rd<='0'; |
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| 425 | Ram_wr<='0'; |
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| 426 | Ready<='1'; |
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| 427 | AppInitReq<='0'; |
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| 428 | |
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| 429 | |
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| 430 | when decode_packet_type => fifo_wr_en <= '0'; |
---|
| 431 | switch_port_out_rd_en <= switch_data_available; |
---|
| 432 | packet_received <= '0'; |
---|
| 433 | dma_wr_request <= '0'; |
---|
| 434 | dma_rd_request <= '0'; |
---|
| 435 | Ram_rd<='0'; |
---|
| 436 | Ram_wr<='0'; |
---|
| 437 | Ram_data_out<=(others=>'Z'); |
---|
| 438 | barrier_completed <= '0'; |
---|
| 439 | AppInitReq<='0'; |
---|
| 440 | Ready<='0'; |
---|
| 441 | |
---|
| 442 | when decode_packet_type2 => fifo_wr_en <= '0'; |
---|
| 443 | switch_port_out_rd_en <= '0'; |
---|
| 444 | packet_received <= '0'; |
---|
| 445 | dma_wr_request <= '0'; |
---|
| 446 | dma_rd_request <= '0'; |
---|
| 447 | Ram_rd<='0'; |
---|
| 448 | Ram_wr<='0'; |
---|
| 449 | Ram_data_out<=(others=>'Z'); |
---|
| 450 | barrier_completed <= '0'; |
---|
| 451 | AppInitReq<='0'; |
---|
| 452 | Ready<='0'; |
---|
| 453 | when fetch_addresses => fifo_wr_en <= '0'; |
---|
| 454 | switch_port_out_rd_en <= switch_data_available; |
---|
| 455 | packet_received <= '0'; |
---|
| 456 | dma_wr_request <= '0'; |
---|
| 457 | dma_rd_request <= '0'; |
---|
| 458 | Ram_rd<='0'; |
---|
| 459 | Ram_wr<='0'; |
---|
| 460 | Ram_data_out<=(others=>'Z'); |
---|
| 461 | barrier_completed <= '0'; |
---|
| 462 | AppInitReq<='0'; |
---|
| 463 | Ready<='0'; |
---|
| 464 | |
---|
| 465 | when execute_put1 => fifo_wr_en <= '0'; |
---|
| 466 | switch_port_out_rd_en <= '0'; |
---|
| 467 | packet_received <= '0'; |
---|
| 468 | dma_wr_request <= '1'; |
---|
| 469 | dma_rd_request <= '0'; |
---|
| 470 | Ram_rd<='0'; |
---|
| 471 | Ram_wr<='0'; |
---|
| 472 | Ram_data_out<=(others=>'Z'); |
---|
| 473 | barrier_completed <= '0'; |
---|
| 474 | AppInitReq<='0'; |
---|
| 475 | Ready<='0'; |
---|
| 476 | |
---|
| 477 | when execute_put2 => Ready<='0'; |
---|
| 478 | fifo_wr_en <= '0'; |
---|
| 479 | switch_port_out_rd_en <=rd_ok; |
---|
| 480 | |
---|
| 481 | if rd_ok = '1' then |
---|
| 482 | |
---|
| 483 | Ram_data_out<=switch_port_out_data; |
---|
| 484 | else |
---|
| 485 | Ram_data_out<=data_to_ram; |
---|
| 486 | end if; |
---|
| 487 | Ram_wr<='1'; |
---|
| 488 | Ram_rd<='0'; |
---|
| 489 | packet_received <= '0'; |
---|
| 490 | dma_rd_request <= '0'; |
---|
| 491 | dma_wr_request <= '1'; |
---|
| 492 | AppInitReq<='0'; |
---|
| 493 | barrier_completed <= '0'; |
---|
| 494 | when execute_put3 => Ready<='0'; |
---|
| 495 | fifo_wr_en <= '0'; |
---|
| 496 | switch_port_out_rd_en <=rd_ok; |
---|
| 497 | --ne pas corrompre le contenu de la RAM |
---|
[39] | 498 | --Ram_data_out<=data_to_ram; |
---|
[15] | 499 | Ram_wr<='0'; |
---|
| 500 | Ram_rd<='1'; |
---|
| 501 | packet_received <= '0'; |
---|
| 502 | dma_rd_request <= '1'; |
---|
| 503 | dma_wr_request <= '0'; |
---|
| 504 | AppInitReq<='0'; |
---|
| 505 | barrier_completed <= '0'; |
---|
| 506 | |
---|
| 507 | |
---|
| 508 | when execute_put4 => fifo_wr_en <= '0'; |
---|
| 509 | Ready<='0'; |
---|
| 510 | switch_port_out_rd_en <= '0'; |
---|
| 511 | packet_received <= '1'; |
---|
[39] | 512 | dma_rd_request <= dma_rd; |
---|
| 513 | dma_wr_request <=dma_wr; |
---|
[15] | 514 | Ram_wr<=wr_ok; |
---|
| 515 | Ram_rd<=rd_ok; |
---|
| 516 | AppInitReq<='0'; |
---|
| 517 | barrier_completed <= '0'; |
---|
[39] | 518 | Ram_data_out<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution |
---|
[15] | 519 | |
---|
| 520 | when execute_put5 => |
---|
| 521 | Ready<='0'; |
---|
| 522 | switch_port_out_rd_en<='0'; |
---|
| 523 | fifo_wr_en <= '0'; |
---|
| 524 | packet_received <= '1'; |
---|
| 525 | AppInitReq<='0'; |
---|
| 526 | barrier_completed <= '0'; |
---|
[39] | 527 | dma_rd_request <= dma_rd; |
---|
| 528 | dma_wr_request <= dma_wr; |
---|
[15] | 529 | Ram_rd<=rd_ok; |
---|
| 530 | Ram_wr<=wr_ok; |
---|
[39] | 531 | Ram_data_out<=data_to_ram; |
---|
[15] | 532 | --Result <=(1=>'1',others=>'0'); --put completed |
---|
| 533 | |
---|
| 534 | when execute_get1=> fifo_wr_en <= '0'; |
---|
| 535 | switch_port_out_rd_en <= switch_data_available; |
---|
| 536 | packet_received <= '0'; |
---|
| 537 | dma_wr_request <= '0'; |
---|
| 538 | dma_rd_request <= '0'; |
---|
| 539 | Ram_rd<='0'; |
---|
| 540 | Ram_wr<='0'; |
---|
| 541 | Ram_data_out<=(others=>'Z'); |
---|
| 542 | barrier_completed <= '0'; |
---|
| 543 | AppInitReq<='0'; |
---|
| 544 | Ready<='0'; |
---|
| 545 | |
---|
| 546 | when execute_get2 => if fifo_full = '0' and switch_data_available = '1' and packet_length > 0 then |
---|
| 547 | |
---|
| 548 | switch_port_out_rd_en <='1'; |
---|
| 549 | else |
---|
| 550 | |
---|
| 551 | switch_port_out_rd_en <='0'; |
---|
| 552 | end if; |
---|
| 553 | |
---|
| 554 | fifo_wr_en <= Wr_ok; |
---|
| 555 | Ready<='0'; |
---|
| 556 | packet_received <= '0'; |
---|
| 557 | dma_rd_request <= '0'; |
---|
| 558 | dma_wr_request <= '0'; |
---|
| 559 | Ram_rd<='0'; |
---|
| 560 | Ram_wr<='0'; |
---|
| 561 | Ram_data_out<=(others=>'Z'); |
---|
| 562 | barrier_completed <= '0'; |
---|
| 563 | AppInitReq<='0'; |
---|
| 564 | |
---|
| 565 | when execute_get3 => fifo_wr_en <= '0'; |
---|
| 566 | Ready<='0'; |
---|
| 567 | switch_port_out_rd_en <= '0'; |
---|
| 568 | packet_received <= '1'; |
---|
| 569 | dma_rd_request <= '1'; |
---|
| 570 | dma_wr_request <='0'; |
---|
| 571 | Ram_wr<='0'; |
---|
| 572 | Ram_rd<='1'; |
---|
| 573 | AppInitReq<='0'; |
---|
| 574 | barrier_completed <= '0'; |
---|
[39] | 575 | --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending |
---|
[15] | 576 | |
---|
| 577 | when execute_get4 => |
---|
| 578 | Ready<='0'; |
---|
| 579 | barrier_completed <= '0'; |
---|
| 580 | switch_port_out_rd_en<='0'; |
---|
| 581 | fifo_wr_en <= '0'; |
---|
| 582 | packet_received <= '1'; |
---|
| 583 | AppInitReq<='0'; |
---|
[39] | 584 | dma_rd_request <= dma_rd; |
---|
| 585 | dma_wr_request <= dma_wr; |
---|
[15] | 586 | Ram_rd<=rd_ok; |
---|
| 587 | Ram_wr<=wr_ok; |
---|
[39] | 588 | Ram_data_out<=data_to_ram; --activer le bit DSending |
---|
[15] | 589 | |
---|
| 590 | |
---|
| 591 | when execute_barrier1 => fifo_wr_en <= '0'; |
---|
| 592 | switch_port_out_rd_en <= switch_data_available; |
---|
| 593 | packet_received <= '0'; |
---|
| 594 | dma_wr_request <= '0'; |
---|
| 595 | dma_rd_request <= '0'; |
---|
| 596 | Ram_rd<='0'; |
---|
| 597 | Ram_wr<='0'; |
---|
| 598 | Ram_data_out<=(others=>'Z'); |
---|
| 599 | barrier_completed <= '0'; |
---|
| 600 | Ready<='0'; |
---|
| 601 | AppInitReq<='0'; |
---|
| 602 | |
---|
| 603 | when execute_barrier2 => fifo_wr_en <= '0'; |
---|
| 604 | Ready<='0'; |
---|
| 605 | switch_port_out_rd_en <='0'; |
---|
| 606 | packet_received <= '0'; |
---|
| 607 | dma_wr_request <= '0'; |
---|
| 608 | dma_rd_request <= '0'; |
---|
| 609 | Ram_rd<='0'; |
---|
| 610 | Ram_wr<='0'; |
---|
| 611 | Ram_data_out<=(others=>'Z'); |
---|
| 612 | barrier_completed <= '0'; |
---|
| 613 | AppInitReq<='0'; |
---|
| 614 | |
---|
| 615 | when execute_barrier3 => fifo_wr_en <= '0'; |
---|
| 616 | switch_port_out_rd_en <='0'; |
---|
| 617 | Ready<='0'; |
---|
| 618 | packet_received <= '0'; |
---|
| 619 | dma_wr_request <= '0'; |
---|
| 620 | dma_rd_request <= '0'; |
---|
| 621 | Ram_rd<='0'; |
---|
| 622 | Ram_wr<='0'; |
---|
| 623 | Ram_data_out<=(others=>'Z'); |
---|
| 624 | barrier_completed <= '1'; |
---|
| 625 | AppInitReq<='0'; |
---|
| 626 | |
---|
| 627 | when execute_barrier4 => fifo_wr_en <= '0'; |
---|
| 628 | switch_port_out_rd_en <='0'; |
---|
| 629 | packet_received <= '0'; |
---|
| 630 | dma_wr_request <= '0'; |
---|
| 631 | dma_rd_request <= '0'; |
---|
| 632 | Ram_rd<='0'; |
---|
| 633 | Ram_wr<='0'; |
---|
| 634 | Ram_data_out<=(others=>'Z'); |
---|
| 635 | barrier_completed <= '0'; |
---|
| 636 | AppInitReq<='0'; |
---|
| 637 | Ready<='0'; |
---|
| 638 | |
---|
| 639 | |
---|
| 640 | when execute_barrier5 => fifo_wr_en <= not(fifo_full); |
---|
| 641 | switch_port_out_rd_en <='0'; |
---|
| 642 | packet_received <= '0'; |
---|
| 643 | dma_wr_request <= '0'; |
---|
| 644 | dma_rd_request <= '0'; |
---|
| 645 | Ram_rd<='0'; |
---|
| 646 | Ram_wr<='0'; |
---|
| 647 | Ram_data_out<=(others=>'Z'); |
---|
| 648 | barrier_completed <= '0'; |
---|
| 649 | AppInitReq<='0'; |
---|
| 650 | Ready<='0'; |
---|
| 651 | |
---|
| 652 | when execute_barrier6 => fifo_wr_en <= not(fifo_full); |
---|
| 653 | switch_port_out_rd_en <= '0'; |
---|
| 654 | packet_received <= '0'; |
---|
| 655 | dma_wr_request <= '0'; |
---|
| 656 | dma_rd_request <= '0'; |
---|
| 657 | Ram_rd<='0'; |
---|
| 658 | Ram_wr<='0'; |
---|
| 659 | Ram_data_out<=(others=>'Z'); |
---|
| 660 | barrier_completed <= '0'; |
---|
| 661 | AppInitReq<='0'; |
---|
| 662 | Ready<='0'; |
---|
| 663 | |
---|
| 664 | when execute_barrier7 => fifo_wr_en <= not(fifo_full); |
---|
| 665 | switch_port_out_rd_en <= '0'; |
---|
| 666 | packet_received <= '0'; |
---|
| 667 | dma_wr_request <= '0'; |
---|
| 668 | dma_rd_request <= '0'; |
---|
| 669 | Ram_rd<='0'; |
---|
| 670 | Ram_wr<='0'; |
---|
| 671 | Ram_data_out<=(others=>'Z'); |
---|
| 672 | barrier_completed <= '0'; |
---|
| 673 | AppInitReq<='0'; |
---|
| 674 | Ready<='0'; |
---|
| 675 | |
---|
| 676 | |
---|
| 677 | when execute_init1 => fifo_wr_en <= not(fifo_full); |
---|
| 678 | switch_port_out_rd_en <= '0'; |
---|
| 679 | packet_received <= '0'; |
---|
| 680 | dma_wr_request <= '0'; |
---|
| 681 | dma_rd_request <= '0'; |
---|
| 682 | Ram_rd<='0'; |
---|
| 683 | Ram_wr<='0'; |
---|
| 684 | barrier_completed <= '0'; |
---|
| 685 | Ready<='0'; |
---|
| 686 | Ram_data_out<=(others =>'Z'); |
---|
| 687 | AppInitReq<='1'; |
---|
| 688 | |
---|
| 689 | |
---|
| 690 | when execute_init2 => fifo_wr_en <= not(fifo_full); |
---|
| 691 | switch_port_out_rd_en <= '0'; |
---|
| 692 | packet_received <= '0'; |
---|
| 693 | dma_wr_request <= '0'; |
---|
| 694 | dma_rd_request <= '0'; |
---|
| 695 | Ram_rd<='0'; |
---|
| 696 | Ram_wr<='0'; |
---|
| 697 | barrier_completed <= '0'; |
---|
| 698 | Ram_data_out<=(others =>'Z'); |
---|
| 699 | AppInitReq<='1'; |
---|
| 700 | Ready<='0'; |
---|
| 701 | |
---|
| 702 | when others => Ready<='1'; -- le module est à nouveau libre |
---|
| 703 | fifo_wr_en <= '0'; |
---|
| 704 | switch_port_out_rd_en <= '0'; |
---|
| 705 | packet_received <= '0'; |
---|
| 706 | dma_wr_request <= '0'; |
---|
| 707 | dma_rd_request <= '0'; |
---|
| 708 | barrier_completed <= '0'; |
---|
| 709 | Ram_data_out<=(others=>'Z'); |
---|
| 710 | Ram_rd<='0'; |
---|
| 711 | Ram_wr<='0'; |
---|
| 712 | Ready<='1'; |
---|
| 713 | AppInitReq<='0'; |
---|
| 714 | end case; |
---|
| 715 | |
---|
| 716 | end process; |
---|
| 717 | |
---|
| 718 | end Behavioral; |
---|
| 719 | |
---|