1 | <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
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2 | <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
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3 | <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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4 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
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5 | <TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status (12/09/2012 - 19:46:00)</B></TD></TR> |
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6 | <TR ALIGN=LEFT> |
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7 | <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
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8 | <TD>MPI_CORE_COMPONENTS.xise</TD> |
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9 | <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
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10 | <TD> No Errors </TD> |
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11 | </TR> |
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12 | <TR ALIGN=LEFT> |
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13 | <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
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14 | <TD>MPI_CORE_SCHEDULER</TD> |
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15 | <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
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16 | <TD>Placed and Routed</TD> |
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17 | </TR> |
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18 | <TR ALIGN=LEFT> |
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19 | <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
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20 | <TD>xc6slx45-3csg324</TD> |
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21 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
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22 | <TD> </TD> |
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23 | </TR> |
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24 | <TR ALIGN=LEFT> |
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25 | <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD> |
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26 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
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27 | <TD> </TD> |
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28 | </TR> |
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29 | <TR ALIGN=LEFT> |
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30 | <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
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31 | <TD>Balanced</TD> |
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32 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
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33 | <TD> |
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34 | </TD> |
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35 | </TR> |
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36 | <TR ALIGN=LEFT> |
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37 | <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
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38 | <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
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39 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
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40 | <TD> </TD> |
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41 | </TR> |
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42 | <TR ALIGN=LEFT> |
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43 | <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
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44 | <TD> |
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45 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_envsettings.html'> |
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46 | System Settings</A> |
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47 | </TD> |
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48 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
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49 | <TD> </TD> |
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50 | </TR> |
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51 | </TABLE> |
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52 | |
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53 | |
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54 | |
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55 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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56 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
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57 | <TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
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58 | <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
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59 | </TR> |
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60 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
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61 | <TD ALIGN=RIGHT>2</TD> |
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62 | <TD ALIGN=RIGHT>4,800</TD> |
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63 | <TD ALIGN=RIGHT>1%</TD> |
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64 | <TD COLSPAN='2'> </TD> |
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65 | </TR> |
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66 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> |
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67 | <TD ALIGN=RIGHT>2</TD> |
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68 | <TD> </TD> |
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69 | <TD> </TD> |
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70 | <TD COLSPAN='2'> </TD> |
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71 | </TR> |
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72 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> |
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73 | <TD ALIGN=RIGHT>0</TD> |
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74 | <TD> </TD> |
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75 | <TD> </TD> |
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76 | <TD COLSPAN='2'> </TD> |
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77 | </TR> |
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78 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD> |
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79 | <TD ALIGN=RIGHT>0</TD> |
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80 | <TD> </TD> |
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81 | <TD> </TD> |
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82 | <TD COLSPAN='2'> </TD> |
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83 | </TR> |
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84 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD> |
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85 | <TD ALIGN=RIGHT>0</TD> |
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86 | <TD> </TD> |
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87 | <TD> </TD> |
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88 | <TD COLSPAN='2'> </TD> |
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89 | </TR> |
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90 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
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91 | <TD ALIGN=RIGHT>9</TD> |
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92 | <TD ALIGN=RIGHT>2,400</TD> |
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93 | <TD ALIGN=RIGHT>1%</TD> |
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94 | <TD COLSPAN='2'> </TD> |
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95 | </TR> |
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96 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
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97 | <TD ALIGN=RIGHT>9</TD> |
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98 | <TD ALIGN=RIGHT>2,400</TD> |
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99 | <TD ALIGN=RIGHT>1%</TD> |
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100 | <TD COLSPAN='2'> </TD> |
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101 | </TR> |
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102 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
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103 | <TD ALIGN=RIGHT>4</TD> |
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104 | <TD> </TD> |
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105 | <TD> </TD> |
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106 | <TD COLSPAN='2'> </TD> |
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107 | </TR> |
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108 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
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109 | <TD ALIGN=RIGHT>0</TD> |
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110 | <TD> </TD> |
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111 | <TD> </TD> |
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112 | <TD COLSPAN='2'> </TD> |
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113 | </TR> |
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114 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
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115 | <TD ALIGN=RIGHT>5</TD> |
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116 | <TD> </TD> |
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117 | <TD> </TD> |
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118 | <TD COLSPAN='2'> </TD> |
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119 | </TR> |
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120 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD> |
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121 | <TD ALIGN=RIGHT>0</TD> |
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122 | <TD> </TD> |
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123 | <TD> </TD> |
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124 | <TD COLSPAN='2'> </TD> |
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125 | </TR> |
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126 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD> |
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127 | <TD ALIGN=RIGHT>0</TD> |
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128 | <TD ALIGN=RIGHT>1,200</TD> |
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129 | <TD ALIGN=RIGHT>0%</TD> |
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130 | <TD COLSPAN='2'> </TD> |
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131 | </TR> |
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132 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
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133 | <TD ALIGN=RIGHT>5</TD> |
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134 | <TD ALIGN=RIGHT>600</TD> |
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135 | <TD ALIGN=RIGHT>1%</TD> |
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136 | <TD COLSPAN='2'> </TD> |
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137 | </TR> |
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138 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> |
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139 | <TD ALIGN=RIGHT>9</TD> |
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140 | <TD> </TD> |
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141 | <TD> </TD> |
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142 | <TD COLSPAN='2'> </TD> |
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143 | </TR> |
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144 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD> |
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145 | <TD ALIGN=RIGHT>7</TD> |
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146 | <TD ALIGN=RIGHT>9</TD> |
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147 | <TD ALIGN=RIGHT>77%</TD> |
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148 | <TD COLSPAN='2'> </TD> |
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149 | </TR> |
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150 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD> |
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151 | <TD ALIGN=RIGHT>0</TD> |
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152 | <TD ALIGN=RIGHT>9</TD> |
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153 | <TD ALIGN=RIGHT>0%</TD> |
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154 | <TD COLSPAN='2'> </TD> |
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155 | </TR> |
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156 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD> |
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157 | <TD ALIGN=RIGHT>2</TD> |
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158 | <TD ALIGN=RIGHT>9</TD> |
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159 | <TD ALIGN=RIGHT>22%</TD> |
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160 | <TD COLSPAN='2'> </TD> |
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161 | </TR> |
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162 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD> |
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163 | <TD ALIGN=RIGHT>2</TD> |
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164 | <TD> </TD> |
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165 | <TD> </TD> |
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166 | <TD COLSPAN='2'> </TD> |
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167 | </TR> |
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168 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD> |
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169 | <TD ALIGN=RIGHT>14</TD> |
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170 | <TD ALIGN=RIGHT>4,800</TD> |
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171 | <TD ALIGN=RIGHT>1%</TD> |
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172 | <TD COLSPAN='2'> </TD> |
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173 | </TR> |
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174 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
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175 | <TD ALIGN=RIGHT>35</TD> |
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176 | <TD ALIGN=RIGHT>102</TD> |
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177 | <TD ALIGN=RIGHT>34%</TD> |
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178 | <TD COLSPAN='2'> </TD> |
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179 | </TR> |
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180 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD> |
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181 | <TD ALIGN=RIGHT>0</TD> |
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182 | <TD ALIGN=RIGHT>12</TD> |
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183 | <TD ALIGN=RIGHT>0%</TD> |
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184 | <TD COLSPAN='2'> </TD> |
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185 | </TR> |
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186 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD> |
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187 | <TD ALIGN=RIGHT>0</TD> |
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188 | <TD ALIGN=RIGHT>24</TD> |
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189 | <TD ALIGN=RIGHT>0%</TD> |
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190 | <TD COLSPAN='2'> </TD> |
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191 | </TR> |
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192 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD> |
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193 | <TD ALIGN=RIGHT>0</TD> |
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194 | <TD ALIGN=RIGHT>32</TD> |
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195 | <TD ALIGN=RIGHT>0%</TD> |
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196 | <TD COLSPAN='2'> </TD> |
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197 | </TR> |
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198 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD> |
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199 | <TD ALIGN=RIGHT>0</TD> |
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200 | <TD ALIGN=RIGHT>32</TD> |
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201 | <TD ALIGN=RIGHT>0%</TD> |
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202 | <TD COLSPAN='2'> </TD> |
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203 | </TR> |
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204 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> |
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205 | <TD ALIGN=RIGHT>1</TD> |
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206 | <TD ALIGN=RIGHT>16</TD> |
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207 | <TD ALIGN=RIGHT>6%</TD> |
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208 | <TD COLSPAN='2'> </TD> |
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209 | </TR> |
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210 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD> |
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211 | <TD ALIGN=RIGHT>1</TD> |
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212 | <TD> </TD> |
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213 | <TD> </TD> |
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214 | <TD COLSPAN='2'> </TD> |
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215 | </TR> |
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216 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD> |
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217 | <TD ALIGN=RIGHT>0</TD> |
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218 | <TD> </TD> |
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219 | <TD> </TD> |
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220 | <TD COLSPAN='2'> </TD> |
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221 | </TR> |
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222 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD> |
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223 | <TD ALIGN=RIGHT>0</TD> |
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224 | <TD ALIGN=RIGHT>4</TD> |
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225 | <TD ALIGN=RIGHT>0%</TD> |
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226 | <TD COLSPAN='2'> </TD> |
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227 | </TR> |
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228 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD> |
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229 | <TD ALIGN=RIGHT>0</TD> |
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230 | <TD ALIGN=RIGHT>200</TD> |
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231 | <TD ALIGN=RIGHT>0%</TD> |
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232 | <TD COLSPAN='2'> </TD> |
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233 | </TR> |
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234 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD> |
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235 | <TD ALIGN=RIGHT>0</TD> |
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236 | <TD ALIGN=RIGHT>200</TD> |
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237 | <TD ALIGN=RIGHT>0%</TD> |
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238 | <TD COLSPAN='2'> </TD> |
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239 | </TR> |
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240 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD> |
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241 | <TD ALIGN=RIGHT>0</TD> |
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242 | <TD ALIGN=RIGHT>200</TD> |
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243 | <TD ALIGN=RIGHT>0%</TD> |
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244 | <TD COLSPAN='2'> </TD> |
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245 | </TR> |
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246 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD> |
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247 | <TD ALIGN=RIGHT>0</TD> |
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248 | <TD ALIGN=RIGHT>4</TD> |
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249 | <TD ALIGN=RIGHT>0%</TD> |
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250 | <TD COLSPAN='2'> </TD> |
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251 | </TR> |
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252 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD> |
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253 | <TD ALIGN=RIGHT>0</TD> |
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254 | <TD ALIGN=RIGHT>128</TD> |
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255 | <TD ALIGN=RIGHT>0%</TD> |
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256 | <TD COLSPAN='2'> </TD> |
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257 | </TR> |
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258 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD> |
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259 | <TD ALIGN=RIGHT>0</TD> |
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260 | <TD ALIGN=RIGHT>8</TD> |
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261 | <TD ALIGN=RIGHT>0%</TD> |
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262 | <TD COLSPAN='2'> </TD> |
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263 | </TR> |
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264 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD> |
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265 | <TD ALIGN=RIGHT>0</TD> |
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266 | <TD ALIGN=RIGHT>4</TD> |
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267 | <TD ALIGN=RIGHT>0%</TD> |
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268 | <TD COLSPAN='2'> </TD> |
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269 | </TR> |
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270 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD> |
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271 | <TD ALIGN=RIGHT>0</TD> |
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272 | <TD ALIGN=RIGHT>8</TD> |
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273 | <TD ALIGN=RIGHT>0%</TD> |
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274 | <TD COLSPAN='2'> </TD> |
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275 | </TR> |
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276 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD> |
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277 | <TD ALIGN=RIGHT>0</TD> |
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278 | <TD ALIGN=RIGHT>1</TD> |
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279 | <TD ALIGN=RIGHT>0%</TD> |
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280 | <TD COLSPAN='2'> </TD> |
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281 | </TR> |
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282 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD> |
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283 | <TD ALIGN=RIGHT>0</TD> |
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284 | <TD ALIGN=RIGHT>2</TD> |
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285 | <TD ALIGN=RIGHT>0%</TD> |
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286 | <TD COLSPAN='2'> </TD> |
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287 | </TR> |
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288 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD> |
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289 | <TD ALIGN=RIGHT>0</TD> |
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290 | <TD ALIGN=RIGHT>2</TD> |
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291 | <TD ALIGN=RIGHT>0%</TD> |
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292 | <TD COLSPAN='2'> </TD> |
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293 | </TR> |
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294 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD> |
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295 | <TD ALIGN=RIGHT>0</TD> |
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296 | <TD ALIGN=RIGHT>1</TD> |
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297 | <TD ALIGN=RIGHT>0%</TD> |
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298 | <TD COLSPAN='2'> </TD> |
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299 | </TR> |
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300 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD> |
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301 | <TD ALIGN=RIGHT>0</TD> |
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302 | <TD ALIGN=RIGHT>1</TD> |
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303 | <TD ALIGN=RIGHT>0%</TD> |
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304 | <TD COLSPAN='2'> </TD> |
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305 | </TR> |
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306 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD> |
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307 | <TD ALIGN=RIGHT>0</TD> |
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308 | <TD ALIGN=RIGHT>1</TD> |
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309 | <TD ALIGN=RIGHT>0%</TD> |
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310 | <TD COLSPAN='2'> </TD> |
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311 | </TR> |
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312 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
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313 | <TD ALIGN=RIGHT>1.39</TD> |
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314 | <TD> </TD> |
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315 | <TD> </TD> |
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316 | <TD COLSPAN='2'> </TD> |
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317 | </TR> |
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318 | </TABLE> |
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319 | |
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320 | |
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321 | |
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322 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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323 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> |
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324 | <TR ALIGN=LEFT> |
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325 | <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
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326 | <TD>0 (Setup: 0, Hold: 0)</TD> |
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327 | <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
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328 | <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
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329 | </TR> |
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330 | <TR ALIGN=LEFT> |
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331 | <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
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332 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.unroutes'>All Signals Completely Routed</A></TD> |
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333 | <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
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334 | <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
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335 | </TR> |
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336 | <TR ALIGN=LEFT> |
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337 | <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
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338 | <TD> |
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339 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
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340 | <TD BGCOLOR='#FFFF99'><B> </B></TD> |
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341 | <TD COLSPAN='2'> </TD> |
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342 | </TABLE> |
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343 | |
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344 | |
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345 | |
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346 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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347 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
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348 | <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
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349 | <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
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350 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:05 2012</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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351 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:09 2012</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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352 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:27 2012</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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353 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:38 2012</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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354 | <TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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355 | <TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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356 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:43 2012</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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357 | <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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358 | </TABLE> |
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359 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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360 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
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361 | <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
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362 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Dec 14:52:37 2012</TD></TR> |
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363 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:26 2012</TD></TR> |
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364 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:32 2012</TD></TR> |
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365 | </TABLE> |
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366 | |
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367 | |
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368 | <br><center><b>Date Generated:</b> 12/09/2012 - 19:46:00</center> |
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369 | </BODY></HTML> |
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