Ignore:
Timestamp:
Dec 20, 2012, 3:42:20 PM (12 years ago)
Author:
rolagamo
Message:

Ceci est la version stable avant optimisation

File:
1 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html

    r15 r41  
    33<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    44<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
    5 <TD ALIGN=CENTER COLSPAN='4'><B>MPI_CORE_COMPONENTS Project Status</B></TD></TR>
     5<TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status (12/09/2012 - 19:46:00)</B></TD></TR>
    66<TR ALIGN=LEFT>
    77<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
    8 <TD>MPI_CORE_COMPONENTS.ise</TD>
    9 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
    10 <TD>New</TD>
     8<TD>MPI_CORE_COMPONENTS.xise</TD>
     9<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
     10<TD> No Errors </TD>
    1111</TR>
    1212<TR ALIGN=LEFT>
    1313<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
    1414<TD>MPI_CORE_SCHEDULER</TD>
     15<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
     16<TD>Placed and Routed</TD>
     17</TR>
     18<TR ALIGN=LEFT>
     19<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
     20<TD>xc6slx45-3csg324</TD>
    1521<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
    1622<TD>&nbsp;</TD>
    1723</TR>
    1824<TR ALIGN=LEFT>
    19 <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
    20 <TD>xc3s1200e-4fg320</TD>
     25<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
    2126<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
    2227<TD>&nbsp;</TD>
    2328</TR>
    2429<TR ALIGN=LEFT>
    25 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
     30<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
     31<TD>Balanced</TD>
    2632<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
    2733<TD>
    … …  
    2935</TR>
    3036<TR ALIGN=LEFT>
    31 <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
    32 <TD>Balanced</TD>
     37<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
     38<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
    3339<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
    3440<TD>&nbsp;</TD>
    3541</TR>
    3642<TR ALIGN=LEFT>
    37 <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
    38 <TD>Xilinx Default (unlocked)</TD>
     43<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
     44<TD>
     45<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_envsettings.html'>
     46System Settings</A>
     47</TD>
    3948<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
    4049<TD>&nbsp;&nbsp;</TD>
    … …  
    4453
    4554
    46 
    47 
    48 
    49 
    50 
     55&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
     56<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
     57<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
     58<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
     59</TR>
     60<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
     61<TD ALIGN=RIGHT>2</TD>
     62<TD ALIGN=RIGHT>4,800</TD>
     63<TD ALIGN=RIGHT>1%</TD>
     64<TD COLSPAN='2'>&nbsp;</TD>
     65</TR>
     66<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
     67<TD ALIGN=RIGHT>2</TD>
     68<TD>&nbsp;</TD>
     69<TD>&nbsp;</TD>
     70<TD COLSPAN='2'>&nbsp;</TD>
     71</TR>
     72<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
     73<TD ALIGN=RIGHT>0</TD>
     74<TD>&nbsp;</TD>
     75<TD>&nbsp;</TD>
     76<TD COLSPAN='2'>&nbsp;</TD>
     77</TR>
     78<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
     79<TD ALIGN=RIGHT>0</TD>
     80<TD>&nbsp;</TD>
     81<TD>&nbsp;</TD>
     82<TD COLSPAN='2'>&nbsp;</TD>
     83</TR>
     84<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
     85<TD ALIGN=RIGHT>0</TD>
     86<TD>&nbsp;</TD>
     87<TD>&nbsp;</TD>
     88<TD COLSPAN='2'>&nbsp;</TD>
     89</TR>
     90<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
     91<TD ALIGN=RIGHT>9</TD>
     92<TD ALIGN=RIGHT>2,400</TD>
     93<TD ALIGN=RIGHT>1%</TD>
     94<TD COLSPAN='2'>&nbsp;</TD>
     95</TR>
     96<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
     97<TD ALIGN=RIGHT>9</TD>
     98<TD ALIGN=RIGHT>2,400</TD>
     99<TD ALIGN=RIGHT>1%</TD>
     100<TD COLSPAN='2'>&nbsp;</TD>
     101</TR>
     102<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
     103<TD ALIGN=RIGHT>4</TD>
     104<TD>&nbsp;</TD>
     105<TD>&nbsp;</TD>
     106<TD COLSPAN='2'>&nbsp;</TD>
     107</TR>
     108<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
     109<TD ALIGN=RIGHT>0</TD>
     110<TD>&nbsp;</TD>
     111<TD>&nbsp;</TD>
     112<TD COLSPAN='2'>&nbsp;</TD>
     113</TR>
     114<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
     115<TD ALIGN=RIGHT>5</TD>
     116<TD>&nbsp;</TD>
     117<TD>&nbsp;</TD>
     118<TD COLSPAN='2'>&nbsp;</TD>
     119</TR>
     120<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
     121<TD ALIGN=RIGHT>0</TD>
     122<TD>&nbsp;</TD>
     123<TD>&nbsp;</TD>
     124<TD COLSPAN='2'>&nbsp;</TD>
     125</TR>
     126<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
     127<TD ALIGN=RIGHT>0</TD>
     128<TD ALIGN=RIGHT>1,200</TD>
     129<TD ALIGN=RIGHT>0%</TD>
     130<TD COLSPAN='2'>&nbsp;</TD>
     131</TR>
     132<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
     133<TD ALIGN=RIGHT>5</TD>
     134<TD ALIGN=RIGHT>600</TD>
     135<TD ALIGN=RIGHT>1%</TD>
     136<TD COLSPAN='2'>&nbsp;</TD>
     137</TR>
     138<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
     139<TD ALIGN=RIGHT>9</TD>
     140<TD>&nbsp;</TD>
     141<TD>&nbsp;</TD>
     142<TD COLSPAN='2'>&nbsp;</TD>
     143</TR>
     144<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
     145<TD ALIGN=RIGHT>7</TD>
     146<TD ALIGN=RIGHT>9</TD>
     147<TD ALIGN=RIGHT>77%</TD>
     148<TD COLSPAN='2'>&nbsp;</TD>
     149</TR>
     150<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
     151<TD ALIGN=RIGHT>0</TD>
     152<TD ALIGN=RIGHT>9</TD>
     153<TD ALIGN=RIGHT>0%</TD>
     154<TD COLSPAN='2'>&nbsp;</TD>
     155</TR>
     156<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
     157<TD ALIGN=RIGHT>2</TD>
     158<TD ALIGN=RIGHT>9</TD>
     159<TD ALIGN=RIGHT>22%</TD>
     160<TD COLSPAN='2'>&nbsp;</TD>
     161</TR>
     162<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
     163<TD ALIGN=RIGHT>2</TD>
     164<TD>&nbsp;</TD>
     165<TD>&nbsp;</TD>
     166<TD COLSPAN='2'>&nbsp;</TD>
     167</TR>
     168<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
     169<TD ALIGN=RIGHT>14</TD>
     170<TD ALIGN=RIGHT>4,800</TD>
     171<TD ALIGN=RIGHT>1%</TD>
     172<TD COLSPAN='2'>&nbsp;</TD>
     173</TR>
     174<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
     175<TD ALIGN=RIGHT>35</TD>
     176<TD ALIGN=RIGHT>102</TD>
     177<TD ALIGN=RIGHT>34%</TD>
     178<TD COLSPAN='2'>&nbsp;</TD>
     179</TR>
     180<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
     181<TD ALIGN=RIGHT>0</TD>
     182<TD ALIGN=RIGHT>12</TD>
     183<TD ALIGN=RIGHT>0%</TD>
     184<TD COLSPAN='2'>&nbsp;</TD>
     185</TR>
     186<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
     187<TD ALIGN=RIGHT>0</TD>
     188<TD ALIGN=RIGHT>24</TD>
     189<TD ALIGN=RIGHT>0%</TD>
     190<TD COLSPAN='2'>&nbsp;</TD>
     191</TR>
     192<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
     193<TD ALIGN=RIGHT>0</TD>
     194<TD ALIGN=RIGHT>32</TD>
     195<TD ALIGN=RIGHT>0%</TD>
     196<TD COLSPAN='2'>&nbsp;</TD>
     197</TR>
     198<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
     199<TD ALIGN=RIGHT>0</TD>
     200<TD ALIGN=RIGHT>32</TD>
     201<TD ALIGN=RIGHT>0%</TD>
     202<TD COLSPAN='2'>&nbsp;</TD>
     203</TR>
     204<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
     205<TD ALIGN=RIGHT>1</TD>
     206<TD ALIGN=RIGHT>16</TD>
     207<TD ALIGN=RIGHT>6%</TD>
     208<TD COLSPAN='2'>&nbsp;</TD>
     209</TR>
     210<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
     211<TD ALIGN=RIGHT>1</TD>
     212<TD>&nbsp;</TD>
     213<TD>&nbsp;</TD>
     214<TD COLSPAN='2'>&nbsp;</TD>
     215</TR>
     216<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
     217<TD ALIGN=RIGHT>0</TD>
     218<TD>&nbsp;</TD>
     219<TD>&nbsp;</TD>
     220<TD COLSPAN='2'>&nbsp;</TD>
     221</TR>
     222<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
     223<TD ALIGN=RIGHT>0</TD>
     224<TD ALIGN=RIGHT>4</TD>
     225<TD ALIGN=RIGHT>0%</TD>
     226<TD COLSPAN='2'>&nbsp;</TD>
     227</TR>
     228<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
     229<TD ALIGN=RIGHT>0</TD>
     230<TD ALIGN=RIGHT>200</TD>
     231<TD ALIGN=RIGHT>0%</TD>
     232<TD COLSPAN='2'>&nbsp;</TD>
     233</TR>
     234<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
     235<TD ALIGN=RIGHT>0</TD>
     236<TD ALIGN=RIGHT>200</TD>
     237<TD ALIGN=RIGHT>0%</TD>
     238<TD COLSPAN='2'>&nbsp;</TD>
     239</TR>
     240<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
     241<TD ALIGN=RIGHT>0</TD>
     242<TD ALIGN=RIGHT>200</TD>
     243<TD ALIGN=RIGHT>0%</TD>
     244<TD COLSPAN='2'>&nbsp;</TD>
     245</TR>
     246<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
     247<TD ALIGN=RIGHT>0</TD>
     248<TD ALIGN=RIGHT>4</TD>
     249<TD ALIGN=RIGHT>0%</TD>
     250<TD COLSPAN='2'>&nbsp;</TD>
     251</TR>
     252<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
     253<TD ALIGN=RIGHT>0</TD>
     254<TD ALIGN=RIGHT>128</TD>
     255<TD ALIGN=RIGHT>0%</TD>
     256<TD COLSPAN='2'>&nbsp;</TD>
     257</TR>
     258<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
     259<TD ALIGN=RIGHT>0</TD>
     260<TD ALIGN=RIGHT>8</TD>
     261<TD ALIGN=RIGHT>0%</TD>
     262<TD COLSPAN='2'>&nbsp;</TD>
     263</TR>
     264<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
     265<TD ALIGN=RIGHT>0</TD>
     266<TD ALIGN=RIGHT>4</TD>
     267<TD ALIGN=RIGHT>0%</TD>
     268<TD COLSPAN='2'>&nbsp;</TD>
     269</TR>
     270<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
     271<TD ALIGN=RIGHT>0</TD>
     272<TD ALIGN=RIGHT>8</TD>
     273<TD ALIGN=RIGHT>0%</TD>
     274<TD COLSPAN='2'>&nbsp;</TD>
     275</TR>
     276<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
     277<TD ALIGN=RIGHT>0</TD>
     278<TD ALIGN=RIGHT>1</TD>
     279<TD ALIGN=RIGHT>0%</TD>
     280<TD COLSPAN='2'>&nbsp;</TD>
     281</TR>
     282<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
     283<TD ALIGN=RIGHT>0</TD>
     284<TD ALIGN=RIGHT>2</TD>
     285<TD ALIGN=RIGHT>0%</TD>
     286<TD COLSPAN='2'>&nbsp;</TD>
     287</TR>
     288<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
     289<TD ALIGN=RIGHT>0</TD>
     290<TD ALIGN=RIGHT>2</TD>
     291<TD ALIGN=RIGHT>0%</TD>
     292<TD COLSPAN='2'>&nbsp;</TD>
     293</TR>
     294<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
     295<TD ALIGN=RIGHT>0</TD>
     296<TD ALIGN=RIGHT>1</TD>
     297<TD ALIGN=RIGHT>0%</TD>
     298<TD COLSPAN='2'>&nbsp;</TD>
     299</TR>
     300<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
     301<TD ALIGN=RIGHT>0</TD>
     302<TD ALIGN=RIGHT>1</TD>
     303<TD ALIGN=RIGHT>0%</TD>
     304<TD COLSPAN='2'>&nbsp;</TD>
     305</TR>
     306<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
     307<TD ALIGN=RIGHT>0</TD>
     308<TD ALIGN=RIGHT>1</TD>
     309<TD ALIGN=RIGHT>0%</TD>
     310<TD COLSPAN='2'>&nbsp;</TD>
     311</TR>
     312<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
     313<TD ALIGN=RIGHT>1.39</TD>
     314<TD>&nbsp;</TD>
     315<TD>&nbsp;</TD>
     316<TD COLSPAN='2'>&nbsp;</TD>
     317</TR>
     318</TABLE>
     319
     320
     321
     322&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
     323<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
     324<TR ALIGN=LEFT>
     325<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
     326<TD>0 (Setup: 0, Hold: 0)</TD>
     327<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
     328<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
     329</TR>
     330<TR ALIGN=LEFT>
     331<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
     332<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.unroutes'>All Signals Completely Routed</A></TD>
     333<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
     334<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
     335</TR>
     336<TR ALIGN=LEFT>
     337<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
     338<TD>
     339<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
     340<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
     341<TD COLSPAN='2'>&nbsp;</TD>
     342</TABLE>
    51343
    52344
    … …  
    56348<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
    57349<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
    58 <TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    59 <TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    60 <TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    61 <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     350<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:05 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     351<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:09 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     352<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:27 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     353<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:38 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     354<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    62355<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    63 <TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     356<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:43 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    64357<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    65358</TABLE>
    … …  
    67360<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
    68361<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
    69 </TABLE>
    70 
    71 
    72 <br><center><b>Date Generated:</b> 06/16/2011 - 20:05:57</center>
     362<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Dec 14:52:37 2012</TD></TR>
     363<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:26 2012</TD></TR>
     364<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:32 2012</TD></TR>
     365</TABLE>
     366
     367
     368<br><center><b>Date Generated:</b> 12/09/2012 - 19:46:00</center>
    73369</BODY></HTML>
Note: See TracChangeset for help on using the changeset viewer.