[15] | 1 | <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
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| 2 | <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
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| 3 | <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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| 4 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
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[64] | 5 | <TD ALIGN=CENTER COLSPAN='4'><B>DMA_ARBITER Project Status (04/03/2013 - 19:35:29)</B></TD></TR> |
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[15] | 6 | <TR ALIGN=LEFT> |
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| 7 | <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
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| 8 | <TD>MPI_CORE_COMPONENTS.xise</TD> |
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| 9 | <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
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[39] | 10 | <TD> No Errors </TD> |
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[15] | 11 | </TR> |
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| 12 | <TR ALIGN=LEFT> |
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| 13 | <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
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| 14 | <TD>MultiMPITest</TD> |
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| 15 | <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
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[41] | 16 | <TD>Placed and Routed</TD> |
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[15] | 17 | </TR> |
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| 18 | <TR ALIGN=LEFT> |
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| 19 | <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
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[41] | 20 | <TD>xc6slx45-3csg324</TD> |
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[15] | 21 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
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[39] | 22 | <TD> |
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[41] | 23 | No Errors</TD> |
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[15] | 24 | </TR> |
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| 25 | <TR ALIGN=LEFT> |
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| 26 | <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD> |
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| 27 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
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[64] | 28 | <TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/*.xmsgs?&DataKey=Warning'>3132 Warnings (78 new)</A></TD> |
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[15] | 29 | </TR> |
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| 30 | <TR ALIGN=LEFT> |
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| 31 | <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
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| 32 | <TD>Balanced</TD> |
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| 33 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
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| 34 | <TD> |
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[41] | 35 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD> |
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[15] | 36 | </TR> |
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| 37 | <TR ALIGN=LEFT> |
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| 38 | <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
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| 39 | <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
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| 40 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
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[41] | 41 | <TD> |
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| 42 | <font color="red"; face="Arial"><b>X </b></font> |
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[64] | 43 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>1 Failing Constraint</A></TD> |
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[15] | 44 | </TR> |
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| 45 | <TR ALIGN=LEFT> |
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| 46 | <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
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[39] | 47 | <TD> |
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| 48 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_envsettings.html'> |
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| 49 | System Settings</A> |
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| 50 | </TD> |
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[15] | 51 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
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[64] | 52 | <TD>3412527 <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD> |
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[15] | 53 | </TR> |
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| 54 | </TABLE> |
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| 55 | |
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| 56 | |
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| 57 | |
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| 58 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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[41] | 59 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
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| 60 | <TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
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| 61 | <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
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| 62 | </TR> |
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| 63 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
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[64] | 64 | <TD ALIGN=RIGHT>2,815</TD> |
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[41] | 65 | <TD ALIGN=RIGHT>54,576</TD> |
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| 66 | <TD ALIGN=RIGHT>5%</TD> |
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| 67 | <TD COLSPAN='2'> </TD> |
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| 68 | </TR> |
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| 69 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> |
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[64] | 70 | <TD ALIGN=RIGHT>2,208</TD> |
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[41] | 71 | <TD> </TD> |
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| 72 | <TD> </TD> |
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| 73 | <TD COLSPAN='2'> </TD> |
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| 74 | </TR> |
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| 75 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> |
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[64] | 76 | <TD ALIGN=RIGHT>607</TD> |
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[41] | 77 | <TD> </TD> |
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| 78 | <TD> </TD> |
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| 79 | <TD COLSPAN='2'> </TD> |
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| 80 | </TR> |
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| 81 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD> |
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| 82 | <TD ALIGN=RIGHT>0</TD> |
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| 83 | <TD> </TD> |
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| 84 | <TD> </TD> |
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| 85 | <TD COLSPAN='2'> </TD> |
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| 86 | </TR> |
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| 87 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD> |
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| 88 | <TD ALIGN=RIGHT>0</TD> |
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| 89 | <TD> </TD> |
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| 90 | <TD> </TD> |
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| 91 | <TD COLSPAN='2'> </TD> |
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| 92 | </TR> |
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| 93 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
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[64] | 94 | <TD ALIGN=RIGHT>12,079</TD> |
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[41] | 95 | <TD ALIGN=RIGHT>27,288</TD> |
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| 96 | <TD ALIGN=RIGHT>44%</TD> |
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| 97 | <TD COLSPAN='2'> </TD> |
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| 98 | </TR> |
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| 99 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
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[64] | 100 | <TD ALIGN=RIGHT>6,942</TD> |
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[41] | 101 | <TD ALIGN=RIGHT>27,288</TD> |
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| 102 | <TD ALIGN=RIGHT>25%</TD> |
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| 103 | <TD COLSPAN='2'> </TD> |
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| 104 | </TR> |
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| 105 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
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[64] | 106 | <TD ALIGN=RIGHT>5,481</TD> |
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[41] | 107 | <TD> </TD> |
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| 108 | <TD> </TD> |
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| 109 | <TD COLSPAN='2'> </TD> |
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| 110 | </TR> |
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| 111 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
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| 112 | <TD ALIGN=RIGHT>409</TD> |
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| 113 | <TD> </TD> |
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| 114 | <TD> </TD> |
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| 115 | <TD COLSPAN='2'> </TD> |
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| 116 | </TR> |
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| 117 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
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[64] | 118 | <TD ALIGN=RIGHT>1,052</TD> |
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[41] | 119 | <TD> </TD> |
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| 120 | <TD> </TD> |
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| 121 | <TD COLSPAN='2'> </TD> |
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| 122 | </TR> |
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| 123 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD> |
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| 124 | <TD ALIGN=RIGHT>0</TD> |
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| 125 | <TD> </TD> |
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| 126 | <TD> </TD> |
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| 127 | <TD COLSPAN='2'> </TD> |
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| 128 | </TR> |
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| 129 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD> |
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| 130 | <TD ALIGN=RIGHT>5,088</TD> |
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| 131 | <TD ALIGN=RIGHT>6,408</TD> |
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| 132 | <TD ALIGN=RIGHT>79%</TD> |
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| 133 | <TD COLSPAN='2'> </TD> |
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| 134 | </TR> |
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| 135 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD> |
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| 136 | <TD ALIGN=RIGHT>5,080</TD> |
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| 137 | <TD> </TD> |
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| 138 | <TD> </TD> |
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| 139 | <TD COLSPAN='2'> </TD> |
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| 140 | </TR> |
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| 141 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
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| 142 | <TD ALIGN=RIGHT>5,080</TD> |
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| 143 | <TD> </TD> |
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| 144 | <TD> </TD> |
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| 145 | <TD COLSPAN='2'> </TD> |
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| 146 | </TR> |
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| 147 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
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| 148 | <TD ALIGN=RIGHT>0</TD> |
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| 149 | <TD> </TD> |
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| 150 | <TD> </TD> |
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| 151 | <TD COLSPAN='2'> </TD> |
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| 152 | </TR> |
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| 153 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
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| 154 | <TD ALIGN=RIGHT>0</TD> |
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| 155 | <TD> </TD> |
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| 156 | <TD> </TD> |
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| 157 | <TD COLSPAN='2'> </TD> |
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| 158 | </TR> |
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| 159 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD> |
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| 160 | <TD ALIGN=RIGHT>8</TD> |
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| 161 | <TD> </TD> |
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| 162 | <TD> </TD> |
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| 163 | <TD COLSPAN='2'> </TD> |
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| 164 | </TR> |
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| 165 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
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| 166 | <TD ALIGN=RIGHT>8</TD> |
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| 167 | <TD> </TD> |
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| 168 | <TD> </TD> |
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| 169 | <TD COLSPAN='2'> </TD> |
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| 170 | </TR> |
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| 171 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
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| 172 | <TD ALIGN=RIGHT>0</TD> |
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| 173 | <TD> </TD> |
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| 174 | <TD> </TD> |
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| 175 | <TD COLSPAN='2'> </TD> |
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| 176 | </TR> |
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| 177 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
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| 178 | <TD ALIGN=RIGHT>0</TD> |
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| 179 | <TD> </TD> |
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| 180 | <TD> </TD> |
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| 181 | <TD COLSPAN='2'> </TD> |
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| 182 | </TR> |
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| 183 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD> |
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| 184 | <TD ALIGN=RIGHT>0</TD> |
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| 185 | <TD> </TD> |
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| 186 | <TD> </TD> |
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| 187 | <TD COLSPAN='2'> </TD> |
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| 188 | </TR> |
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| 189 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD> |
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[64] | 190 | <TD ALIGN=RIGHT>49</TD> |
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[41] | 191 | <TD> </TD> |
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| 192 | <TD> </TD> |
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| 193 | <TD COLSPAN='2'> </TD> |
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| 194 | </TR> |
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| 195 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD> |
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[64] | 196 | <TD ALIGN=RIGHT>1</TD> |
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[41] | 197 | <TD> </TD> |
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| 198 | <TD> </TD> |
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| 199 | <TD COLSPAN='2'> </TD> |
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| 200 | </TR> |
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| 201 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD> |
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| 202 | <TD ALIGN=RIGHT>48</TD> |
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| 203 | <TD> </TD> |
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| 204 | <TD> </TD> |
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| 205 | <TD COLSPAN='2'> </TD> |
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| 206 | </TR> |
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| 207 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD> |
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| 208 | <TD ALIGN=RIGHT>0</TD> |
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| 209 | <TD> </TD> |
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| 210 | <TD> </TD> |
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| 211 | <TD COLSPAN='2'> </TD> |
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| 212 | </TR> |
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| 213 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
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[64] | 214 | <TD ALIGN=RIGHT>3,785</TD> |
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[41] | 215 | <TD ALIGN=RIGHT>6,822</TD> |
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[64] | 216 | <TD ALIGN=RIGHT>55%</TD> |
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[41] | 217 | <TD COLSPAN='2'> </TD> |
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| 218 | </TR> |
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| 219 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> |
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[64] | 220 | <TD ALIGN=RIGHT>12,380</TD> |
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[41] | 221 | <TD> </TD> |
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| 222 | <TD> </TD> |
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| 223 | <TD COLSPAN='2'> </TD> |
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| 224 | </TR> |
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| 225 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD> |
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[64] | 226 | <TD ALIGN=RIGHT>9,722</TD> |
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| 227 | <TD ALIGN=RIGHT>12,380</TD> |
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[41] | 228 | <TD ALIGN=RIGHT>78%</TD> |
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| 229 | <TD COLSPAN='2'> </TD> |
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| 230 | </TR> |
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| 231 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD> |
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[64] | 232 | <TD ALIGN=RIGHT>301</TD> |
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| 233 | <TD ALIGN=RIGHT>12,380</TD> |
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[41] | 234 | <TD ALIGN=RIGHT>2%</TD> |
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| 235 | <TD COLSPAN='2'> </TD> |
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| 236 | </TR> |
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| 237 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD> |
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[64] | 238 | <TD ALIGN=RIGHT>2,357</TD> |
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| 239 | <TD ALIGN=RIGHT>12,380</TD> |
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| 240 | <TD ALIGN=RIGHT>19%</TD> |
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[41] | 241 | <TD COLSPAN='2'> </TD> |
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| 242 | </TR> |
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| 243 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD> |
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[64] | 244 | <TD ALIGN=RIGHT>855</TD> |
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[41] | 245 | <TD> </TD> |
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| 246 | <TD> </TD> |
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| 247 | <TD COLSPAN='2'> </TD> |
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| 248 | </TR> |
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| 249 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD> |
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[64] | 250 | <TD ALIGN=RIGHT>3,313</TD> |
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[41] | 251 | <TD ALIGN=RIGHT>54,576</TD> |
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| 252 | <TD ALIGN=RIGHT>6%</TD> |
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| 253 | <TD COLSPAN='2'> </TD> |
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| 254 | </TR> |
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| 255 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
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| 256 | <TD ALIGN=RIGHT>10</TD> |
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| 257 | <TD ALIGN=RIGHT>218</TD> |
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| 258 | <TD ALIGN=RIGHT>4%</TD> |
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| 259 | <TD COLSPAN='2'> </TD> |
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| 260 | </TR> |
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| 261 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD> |
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| 262 | <TD ALIGN=RIGHT>0</TD> |
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| 263 | <TD ALIGN=RIGHT>116</TD> |
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| 264 | <TD ALIGN=RIGHT>0%</TD> |
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| 265 | <TD COLSPAN='2'> </TD> |
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| 266 | </TR> |
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| 267 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD> |
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[64] | 268 | <TD ALIGN=RIGHT>3</TD> |
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[41] | 269 | <TD ALIGN=RIGHT>232</TD> |
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[64] | 270 | <TD ALIGN=RIGHT>1%</TD> |
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[41] | 271 | <TD COLSPAN='2'> </TD> |
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| 272 | </TR> |
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| 273 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD> |
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| 274 | <TD ALIGN=RIGHT>0</TD> |
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| 275 | <TD ALIGN=RIGHT>32</TD> |
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| 276 | <TD ALIGN=RIGHT>0%</TD> |
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| 277 | <TD COLSPAN='2'> </TD> |
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| 278 | </TR> |
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| 279 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD> |
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| 280 | <TD ALIGN=RIGHT>0</TD> |
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| 281 | <TD ALIGN=RIGHT>32</TD> |
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| 282 | <TD ALIGN=RIGHT>0%</TD> |
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| 283 | <TD COLSPAN='2'> </TD> |
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| 284 | </TR> |
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| 285 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> |
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| 286 | <TD ALIGN=RIGHT>4</TD> |
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| 287 | <TD ALIGN=RIGHT>16</TD> |
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| 288 | <TD ALIGN=RIGHT>25%</TD> |
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| 289 | <TD COLSPAN='2'> </TD> |
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| 290 | </TR> |
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| 291 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD> |
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| 292 | <TD ALIGN=RIGHT>4</TD> |
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| 293 | <TD> </TD> |
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| 294 | <TD> </TD> |
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| 295 | <TD COLSPAN='2'> </TD> |
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| 296 | </TR> |
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| 297 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD> |
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| 298 | <TD ALIGN=RIGHT>0</TD> |
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| 299 | <TD> </TD> |
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| 300 | <TD> </TD> |
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| 301 | <TD COLSPAN='2'> </TD> |
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| 302 | </TR> |
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| 303 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD> |
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| 304 | <TD ALIGN=RIGHT>0</TD> |
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| 305 | <TD ALIGN=RIGHT>8</TD> |
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| 306 | <TD ALIGN=RIGHT>0%</TD> |
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| 307 | <TD COLSPAN='2'> </TD> |
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| 308 | </TR> |
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| 309 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD> |
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| 310 | <TD ALIGN=RIGHT>0</TD> |
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| 311 | <TD ALIGN=RIGHT>376</TD> |
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| 312 | <TD ALIGN=RIGHT>0%</TD> |
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| 313 | <TD COLSPAN='2'> </TD> |
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| 314 | </TR> |
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| 315 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD> |
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| 316 | <TD ALIGN=RIGHT>0</TD> |
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| 317 | <TD ALIGN=RIGHT>376</TD> |
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| 318 | <TD ALIGN=RIGHT>0%</TD> |
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| 319 | <TD COLSPAN='2'> </TD> |
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| 320 | </TR> |
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| 321 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD> |
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| 322 | <TD ALIGN=RIGHT>0</TD> |
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| 323 | <TD ALIGN=RIGHT>376</TD> |
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| 324 | <TD ALIGN=RIGHT>0%</TD> |
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| 325 | <TD COLSPAN='2'> </TD> |
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| 326 | </TR> |
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| 327 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD> |
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| 328 | <TD ALIGN=RIGHT>0</TD> |
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| 329 | <TD ALIGN=RIGHT>4</TD> |
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| 330 | <TD ALIGN=RIGHT>0%</TD> |
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| 331 | <TD COLSPAN='2'> </TD> |
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| 332 | </TR> |
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| 333 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD> |
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| 334 | <TD ALIGN=RIGHT>0</TD> |
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| 335 | <TD ALIGN=RIGHT>256</TD> |
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| 336 | <TD ALIGN=RIGHT>0%</TD> |
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| 337 | <TD COLSPAN='2'> </TD> |
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| 338 | </TR> |
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| 339 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD> |
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| 340 | <TD ALIGN=RIGHT>0</TD> |
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| 341 | <TD ALIGN=RIGHT>8</TD> |
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| 342 | <TD ALIGN=RIGHT>0%</TD> |
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| 343 | <TD COLSPAN='2'> </TD> |
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| 344 | </TR> |
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| 345 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD> |
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| 346 | <TD ALIGN=RIGHT>0</TD> |
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| 347 | <TD ALIGN=RIGHT>4</TD> |
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| 348 | <TD ALIGN=RIGHT>0%</TD> |
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| 349 | <TD COLSPAN='2'> </TD> |
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| 350 | </TR> |
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| 351 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD> |
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| 352 | <TD ALIGN=RIGHT>0</TD> |
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| 353 | <TD ALIGN=RIGHT>58</TD> |
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| 354 | <TD ALIGN=RIGHT>0%</TD> |
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| 355 | <TD COLSPAN='2'> </TD> |
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| 356 | </TR> |
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| 357 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD> |
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| 358 | <TD ALIGN=RIGHT>0</TD> |
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| 359 | <TD ALIGN=RIGHT>1</TD> |
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| 360 | <TD ALIGN=RIGHT>0%</TD> |
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| 361 | <TD COLSPAN='2'> </TD> |
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| 362 | </TR> |
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| 363 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD> |
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| 364 | <TD ALIGN=RIGHT>0</TD> |
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| 365 | <TD ALIGN=RIGHT>2</TD> |
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| 366 | <TD ALIGN=RIGHT>0%</TD> |
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| 367 | <TD COLSPAN='2'> </TD> |
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| 368 | </TR> |
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| 369 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD> |
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| 370 | <TD ALIGN=RIGHT>0</TD> |
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| 371 | <TD ALIGN=RIGHT>2</TD> |
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| 372 | <TD ALIGN=RIGHT>0%</TD> |
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| 373 | <TD COLSPAN='2'> </TD> |
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| 374 | </TR> |
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| 375 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD> |
---|
| 376 | <TD ALIGN=RIGHT>0</TD> |
---|
| 377 | <TD ALIGN=RIGHT>4</TD> |
---|
| 378 | <TD ALIGN=RIGHT>0%</TD> |
---|
| 379 | <TD COLSPAN='2'> </TD> |
---|
| 380 | </TR> |
---|
| 381 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD> |
---|
| 382 | <TD ALIGN=RIGHT>0</TD> |
---|
| 383 | <TD ALIGN=RIGHT>1</TD> |
---|
| 384 | <TD ALIGN=RIGHT>0%</TD> |
---|
| 385 | <TD COLSPAN='2'> </TD> |
---|
| 386 | </TR> |
---|
| 387 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD> |
---|
| 388 | <TD ALIGN=RIGHT>0</TD> |
---|
| 389 | <TD ALIGN=RIGHT>1</TD> |
---|
| 390 | <TD ALIGN=RIGHT>0%</TD> |
---|
| 391 | <TD COLSPAN='2'> </TD> |
---|
| 392 | </TR> |
---|
| 393 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD> |
---|
| 394 | <TD ALIGN=RIGHT>0</TD> |
---|
| 395 | <TD ALIGN=RIGHT>1</TD> |
---|
| 396 | <TD ALIGN=RIGHT>0%</TD> |
---|
| 397 | <TD COLSPAN='2'> </TD> |
---|
| 398 | </TR> |
---|
| 399 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
---|
[64] | 400 | <TD ALIGN=RIGHT>5.66</TD> |
---|
[41] | 401 | <TD> </TD> |
---|
| 402 | <TD> </TD> |
---|
| 403 | <TD COLSPAN='2'> </TD> |
---|
| 404 | </TR> |
---|
[15] | 405 | </TABLE> |
---|
| 406 | |
---|
| 407 | |
---|
| 408 | |
---|
[41] | 409 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
---|
| 410 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> |
---|
| 411 | <TR ALIGN=LEFT> |
---|
| 412 | <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
---|
[64] | 413 | <TD>3412527 (Setup: 3412527, Hold: 0, Component Switching Limit: 0)</TD> |
---|
[41] | 414 | <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
---|
| 415 | <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
---|
| 416 | </TR> |
---|
| 417 | <TR ALIGN=LEFT> |
---|
| 418 | <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
---|
| 419 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD> |
---|
| 420 | <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
---|
| 421 | <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
---|
| 422 | </TR> |
---|
| 423 | <TR ALIGN=LEFT> |
---|
| 424 | <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
---|
| 425 | <TD> |
---|
| 426 | <font color="red"; face="Arial"><b>X </b></font> |
---|
[64] | 427 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>1 Failing Constraint</A></TD> |
---|
[41] | 428 | <TD BGCOLOR='#FFFF99'><B> </B></TD> |
---|
| 429 | <TD COLSPAN='2'> </TD> |
---|
| 430 | </TABLE> |
---|
[15] | 431 | |
---|
| 432 | |
---|
| 433 | |
---|
| 434 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
---|
| 435 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
---|
| 436 | <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
---|
| 437 | <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
---|
[64] | 438 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed 3. Apr 19:05:13 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/xst.xmsgs?&DataKey=Warning'>1211 Warnings (3 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/xst.xmsgs?&DataKey=Info'>433 Infos (10 new)</A></TD></TR> |
---|
| 439 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed 3. Apr 19:05:27 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>102 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
---|
| 440 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed 3. Apr 19:13:28 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Warning'>967 Warnings (74 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR> |
---|
| 441 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed 3. Apr 19:34:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Warning'>852 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
---|
[15] | 442 | <TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
---|
[64] | 443 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed 3. Apr 19:35:24 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR> |
---|
| 444 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>Wed 19. Dec 13:42:44 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>1106 Warnings (565 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
---|
[15] | 445 | </TABLE> |
---|
| 446 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
---|
| 447 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
---|
| 448 | <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
---|
[64] | 449 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 3. Apr 19:01:58 2013</TD></TR> |
---|
| 450 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 19. Dec 17:30:44 2012</TD></TR> |
---|
| 451 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon 18. Mar 11:20:20 2013</TD></TR> |
---|
| 452 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon 18. Mar 11:20:25 2013</TD></TR> |
---|
[15] | 453 | </TABLE> |
---|
| 454 | |
---|
| 455 | |
---|
[64] | 456 | <br><center><b>Date Generated:</b> 04/03/2013 - 19:35:29</center> |
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[15] | 457 | </BODY></HTML> |
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