[70] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 05:52:25 06/21/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: CORE_MPI - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | Library NocLib; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | use NocLib.CoreTypes.all; |
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| 26 | ---- Uncomment the following library declaration if instantiating |
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| 27 | ---- any Xilinx primitives in this code. |
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| 28 | --library UNISIM; |
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| 29 | --use UNISIM.VComponents.all; |
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| 30 | |
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| 31 | entity CORE_MPI is |
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| 32 | Port ( |
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| 33 | clk : in STD_LOGIC; |
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| 34 | reset : in STD_LOGIC; |
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| 35 | clkout : out std_logic; |
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| 36 | instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 37 | instruction_en : in STD_LOGIC; --valide l'instruction |
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| 38 | instruction_fifo_full : out STD_LOGIC; |
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| 39 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 40 | barrier_completed : out STD_LOGIC; |
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| 41 | packet_received : out STD_LOGIC; |
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| 42 | packet_ack : in std_logic; |
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| 43 | PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution |
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| 44 | ram_we : out STD_LOGIC; |
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| 45 | ram_en : out STD_LOGIC; |
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| 46 | ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0); |
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| 47 | ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0); |
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| 48 | ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 49 | hold_req : out STD_Logic; --requete vers application |
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| 50 | hold_ack : in STD_Logic; --autorisation par l'application |
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| 51 | switch_port_in_cmd_en : out std_logic; |
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| 52 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 53 | switch_port_in_wr_en : out STD_LOGIC; |
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| 54 | switch_port_in_full : in STD_LOGIC; |
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| 55 | switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 56 | switch_port_out_rd_en : out STD_LOGIC; |
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| 57 | switch_port_in_empty : in STD_LOGIC; |
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| 58 | switch_port_out_data_vailaible : in STD_LOGIC |
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| 59 | ); |
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| 60 | |
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| 61 | end CORE_MPI; |
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| 62 | |
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| 63 | architecture Structural of CORE_MPI is |
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| 64 | --déclaration des types |
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| 65 | type Type_Noc is |
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| 66 | record |
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| 67 | port_in_cmd_en : std_logic; |
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| 68 | port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 69 | port_in_wr_en : STD_LOGIC; |
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| 70 | port_in_empty : STD_LOGIC; |
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| 71 | port_in_full : STD_LOGIC; |
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| 72 | port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 73 | port_out_rd_en : STD_LOGIC; |
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| 74 | port_out_data_available : STD_LOGIC; |
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| 75 | end record; |
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| 76 | -- déclaration des composants MPI |
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| 77 | |
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| 78 | COMPONENT FIFO_64_FWFT |
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| 79 | PORT( |
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| 80 | clk : IN std_logic; |
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| 81 | din : IN std_logic_vector(Word-1 downto 0); |
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| 82 | rd_en : IN std_logic; |
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| 83 | srst : IN std_logic; |
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| 84 | wr_en : IN std_logic; |
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| 85 | dout : OUT std_logic_vector(Word-1 downto 0); |
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| 86 | empty : OUT std_logic; |
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| 87 | full : OUT std_logic |
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| 88 | ); |
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| 89 | END COMPONENT; |
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| 90 | COMPONENT load_instr |
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| 91 | Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 92 | Instruction_en : in STD_LOGIC; |
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| 93 | clk : in STD_LOGIC; |
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| 94 | reset : in STD_LOGIC; |
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| 95 | dma_rd_grant : in STD_LOGIC; |
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| 96 | dma_rd_request : out STD_LOGIC; |
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| 97 | instruction_ack : out STD_LOGIC; |
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| 98 | fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 99 | fifo_wr :out std_logic; |
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| 100 | fifo_full : in STD_LOGIC; |
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| 101 | copying : out std_logic; |
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| 102 | Ram_rd_en : out STD_LOGIC; |
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[74] | 103 | ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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[70] | 104 | ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); |
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| 105 | end component; |
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| 106 | COMPONENT DMA_ARBITER |
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| 107 | PORT( |
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| 108 | |
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| 109 | clk : IN std_logic; |
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| 110 | reset : IN std_logic; |
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| 111 | dma_rd_request : IN std_logic_vector(3 downto 0); |
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| 112 | data_wr_in : IN std_logic_vector(Word-1 downto 0); |
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| 113 | data_rd_out : out std_logic_vector(Word-1 downto 0); |
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| 114 | address_rd : IN std_logic_vector(15 downto 0); |
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| 115 | address_wr : IN std_logic_vector(15 downto 0); |
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| 116 | |
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| 117 | dma_wr_request : IN std_logic_vector(3 downto 0); |
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| 118 | address_out_rd : OUT std_logic_vector(15 downto 0); |
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| 119 | address_out_wr : OUT std_logic_vector(15 downto 0); |
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| 120 | ram_en : OUT std_logic; |
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| 121 | ram_we : OUT std_logic; |
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| 122 | hold_req : out STD_Logic; --requete vers application |
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| 123 | hold_ack : in STD_Logic; --autorisation par l'application |
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| 124 | data_wr_mem : OUT std_logic_vector(Word-1 downto 0); |
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| 125 | data_rd_mem : IN std_logic_vector(Word-1 downto 0); |
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| 126 | dma_wr_grant : OUT std_logic_vector(3 downto 0); |
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| 127 | dma_rd_grant : OUT std_logic_vector(3 downto 0) |
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| 128 | ); |
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| 129 | END COMPONENT; |
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| 130 | |
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| 131 | COMPONENT EX1_FSM |
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| 132 | PORT( |
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| 133 | clk : IN std_logic; |
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| 134 | reset : IN std_logic; |
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| 135 | |
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| 136 | pid : in std_logic_vector (3 downto 0); --port id |
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| 137 | nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc |
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| 138 | instruction : in std_logic_vector(Word-1 downto 0); |
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| 139 | instruction_en : in std_logic; |
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| 140 | fifo_empty : IN std_logic; |
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| 141 | fifo_data_out : IN std_logic_vector(Word-1 downto 0); |
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| 142 | fifo_rd_en : OUT std_logic; |
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| 143 | fifo_src : IN STD_LOGIC; |
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| 144 | ram_data_in : IN std_logic_vector(Word-1 downto 0); |
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| 145 | ram_data_out : out std_logic_vector(Word-1 downto 0); |
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| 146 | dma_rd_grant : IN std_logic; |
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| 147 | dma_wr_grant : IN std_logic; |
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| 148 | dma_wr_request : OUT std_logic; |
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| 149 | dma_rd_request : OUT std_logic; |
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| 150 | ram_address : OUT std_logic_vector(15 downto 0); |
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| 151 | ram_rd,ram_wr : out std_logic; |
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| 152 | Snd_Data : IN Typ_PortIO(0 to 3); |
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| 153 | Snd_Start : IN std_logic; |
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| 154 | Snd_Ack : OUT std_logic; |
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| 155 | priority_rotation : OUT std_logic; |
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| 156 | |
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| 157 | switch_port_in_data : OUT std_logic_vector(Word-1 downto 0); |
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| 158 | switch_port_in_wr_en : OUT std_logic; |
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| 159 | switch_port_in_full : IN std_logic; |
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| 160 | Result :out std_logic_vector(Word-1 downto 0); |
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| 161 | Ready : out std_logic; |
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| 162 | AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application |
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| 163 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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| 164 | Initialized:in std_logic -- état de la Lib |
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| 165 | ); |
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| 166 | END COMPONENT; |
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| 167 | |
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| 168 | COMPONENT EX2_FSM |
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| 169 | PORT( |
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| 170 | clk : IN std_logic; |
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| 171 | reset : IN std_logic; |
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| 172 | |
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| 173 | instruction_en: in std_logic; |
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| 174 | Initialized : in std_logic; |
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| 175 | |
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| 176 | switch_port_out_rd_en : OUT std_logic ; |
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| 177 | switch_data_available : IN std_logic; |
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| 178 | switch_port_out_data : IN std_logic_vector(Word-1 downto 0); |
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| 179 | AppRank : in STD_LOGIC_VECTOR; |
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| 180 | AppSize : in STD_LOGIC_VECTOR; |
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| 181 | dma_wr_grant : IN std_logic; |
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| 182 | dma_wr_request : OUT std_logic; |
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| 183 | dma_rd_grant : IN std_logic; |
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| 184 | dma_rd_request : OUT std_logic; |
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| 185 | ram_address : OUT std_logic_vector(15 downto 0); |
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| 186 | ram_rd,ram_wr : out std_logic; |
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| 187 | Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 188 | Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 189 | fifo_full : IN std_logic; |
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| 190 | Rec_Rdy : OUT std_logic; |
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[74] | 191 | Rec_Data : buffer Typ_PortIO(0 to 3); |
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[70] | 192 | Rec_Ack : IN std_logic; |
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| 193 | fifo_data : OUT std_logic_vector(Word-1 downto 0); |
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| 194 | fifo_wr_en : OUT std_logic; |
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| 195 | --fifo_out : out std_logic_vector; |
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| 196 | Result : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 197 | packet_received : OUT std_logic; |
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| 198 | packet_ack : IN std_logic; |
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| 199 | barrier_completed : OUT std_logic; |
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| 200 | Ready : Out std_logic; |
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| 201 | AppInitAck : in std_logic; |
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| 202 | AppInitReq : out std_logic |
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| 203 | ); |
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| 204 | END COMPONENT; |
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| 205 | |
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| 206 | |
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| 207 | COMPONENT EX3_FSM |
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| 208 | PORT( |
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| 209 | instruction : IN std_logic_vector(Word-1 downto 0); |
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| 210 | clk : IN std_logic; |
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| 211 | reset : IN std_logic; |
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| 212 | Ismain :in std_logic; |
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| 213 | ResOut : OUT std_logic_vector(Word-1 downto 0) |
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| 214 | |
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| 215 | ); |
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| 216 | END COMPONENT; |
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| 217 | |
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| 218 | COMPONENT EX4_FSM |
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| 219 | PORT( |
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| 220 | Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO |
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| 221 | Instruction_En : in STD_LOGIC; |
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| 222 | clk : in STD_LOGIC; |
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| 223 | reset : in STD_LOGIC; |
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| 224 | ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 225 | Result_En : out STD_LOGIC; |
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| 226 | Ready : out STD_LOGIC; |
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| 227 | NocSize : out STD_LOGIC_VECTOR; |
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| 228 | AppRank : out STD_LOGIC_VECTOR; |
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| 229 | AppSize : out STD_LOGIC_VECTOR; |
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| 230 | IsMain : out STD_LOGIC; |
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| 231 | I_fifo_full :in STD_LOGIC; |
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| 232 | Snd_Ack : IN std_logic; |
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| 233 | Rec_Rdy : IN std_logic; |
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| 234 | Rec_Data : IN Typ_PortIO(0 to 3); |
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| 235 | Snd_data : OUT Typ_PortIO(0 to 3); |
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[74] | 236 | Snd_Start : buffer std_logic; |
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[70] | 237 | Rec_Ack : OUT std_logic; |
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| 238 | I_fifo_wr_en: out STD_LOGIC; |
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| 239 | I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); |
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| 240 | Initialized : out STD_LOGIC; |
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| 241 | dma_wr_request : out std_logic; |
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| 242 | dma_rd_request : out std_logic; |
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| 243 | dma_wr_grant : in std_logic; |
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| 244 | dma_rd_grant : in std_logic; |
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| 245 | Ram_address : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage |
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| 246 | Ram_wr : out STD_LOGIC; --activation de l'écriture en RAM |
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| 247 | Ram_Data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports |
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| 248 | Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 249 | AppAck : in STD_LOGIC; |
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| 250 | AppReq : in STD_LOGIC; |
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| 251 | PortId : out STD_LOGIC_VECTOR(3 downto 0); |
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| 252 | port_in_cmd_en : out STD_LOGIC; |
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| 253 | port_in_wr_en : out STD_LOGIC; |
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| 254 | port_in_empty : in STD_LOGIC; |
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| 255 | port_in_full : in STD_LOGIC; |
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| 256 | port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 257 | port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 258 | port_out_rd_en : out STD_LOGIC; |
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| 259 | port_out_data_available : in STD_LOGIC); |
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| 260 | END COMPONENT; |
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| 261 | |
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| 262 | COMPONENT EX0_FSM |
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| 263 | PORT( |
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| 264 | clk : in STD_LOGIC; |
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| 265 | reset : in STD_LOGIC; |
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| 266 | |
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| 267 | Initialized : in STD_LOGIC; |
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| 268 | Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 269 | instruction_en: in STD_LOGIC; |
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| 270 | |
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| 271 | ClkRate : in STD_LOGIC_VECTOR ; |
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| 272 | uTimeResult : out STD_LOGIC_VECTOR; |
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| 273 | TickResult : out STD_LOGIC_VECTOR |
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| 274 | ); |
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| 275 | END COMPONENT; |
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| 276 | |
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| 277 | |
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| 278 | COMPONENT MPI_CORE_SCHEDULER |
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| 279 | PORT( |
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| 280 | clk : IN std_logic; |
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| 281 | reset : IN std_logic; |
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| 282 | priority_rotation : IN std_logic; |
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| 283 | instruction_fifo_empty : IN std_logic; |
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| 284 | instruction_fifo_rd_en : OUT std_logic; |
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| 285 | instruction_fifo_data : IN std_logic_vector(Word-1 downto 0); |
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| 286 | instruction_available : OUT std_logic; |
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| 287 | |
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| 288 | get_request_fifo_empty : IN std_logic; |
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| 289 | get_request_fifo_rd_en : OUT std_logic; |
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| 290 | get_request_fifo_data : IN std_logic_vector(Word-1 downto 0); |
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| 291 | |
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| 292 | fifo_rd_en : IN std_logic; |
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| 293 | fifo_empty : OUT std_logic; |
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| 294 | fifo_selected : OUT std_logic; |
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| 295 | |
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| 296 | data_out : OUT std_logic_vector(Word-1 downto 0) |
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| 297 | |
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| 298 | |
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| 299 | ); |
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| 300 | END COMPONENT; |
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| 301 | |
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| 302 | -- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts |
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| 303 | signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction |
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| 304 | |
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| 305 | |
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| 306 | signal scheduler_fifo_empty : std_logic; |
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| 307 | signal scheduler_data_out : std_logic_vector(Word-1 downto 0); |
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| 308 | signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0); |
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| 309 | |
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| 310 | signal scheduler_priority_rotation : std_logic; |
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| 311 | signal scheduler_rd_en : std_logic; |
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| 312 | |
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| 313 | signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états |
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| 314 | signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états! |
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| 315 | signal dma_rd_address3 : std_logic_vector(15 downto 0); |
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| 316 | signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0); |
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| 317 | signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0); |
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| 318 | signal dma_wr_address : std_logic_vector(15 downto 0); |
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| 319 | signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0); |
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| 320 | signal ram_data_out_signal : std_logic_vector(Word-1 downto 0); |
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| 321 | signal weram,rdram,ram_wev,ram_env :std_logic:='0'; |
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| 322 | |
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| 323 | signal i_fifo2_signal : std_logic_vector(Word-1 downto 0); |
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| 324 | signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI |
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| 325 | signal Res4_en:std_logic;--acquittement du réusltat du module n°4 |
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| 326 | signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE |
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| 327 | signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM |
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| 328 | signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM |
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| 329 | signal Exi_busy : std_logic:='0'; |
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| 330 | signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0); |
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| 331 | signal Instr_in : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 332 | --================interface DMA avec les modules ====================================== |
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| 333 | signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0); |
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| 334 | signal dma_data_out : std_logic_vector(Word-1 downto 0); |
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| 335 | signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0'); |
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| 336 | signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0'); |
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| 337 | signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1); |
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| 338 | -- |
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| 339 | --====================================================================================== |
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| 340 | --connexion au switch |
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| 341 | |
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| 342 | signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc |
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| 343 | |
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| 344 | --================================================================ |
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| 345 | --déclaration des signaux d'état du Core |
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| 346 | signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic; |
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| 347 | signal InitReq,InitReq1,InitReq2 :std_logic:='0'; -- demande d'initialisation |
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| 348 | signal InitAck,IAck,Ilatch : std_logic:='0'; |
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| 349 | signal MPISize,MyRank : std_logic_vector(3 downto 0); |
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| 350 | signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,... |
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| 351 | signal NocSize :std_logic_vector(3 downto 0):=(others=>'0'); |
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| 352 | Signal PortId : std_logic_vector(3 downto 0); |
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| 353 | Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz |
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| 354 | signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0'); |
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| 355 | signal TickCount : std_logic_vector(31 downto 0):=(others=>'0'); |
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| 356 | signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 357 | --======================================================== |
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| 358 | --déclaration des signaux permettant d'activer le module |
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| 359 | signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0); |
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| 360 | --======================================================== |
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| 361 | --signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi |
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| 362 | --======================================================== |
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| 363 | --connexion avec les FIFO instructions |
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| 364 | signal fifo1_wr : std_logic; |
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| 365 | signal fifo1_din : std_logic_vector (Word-1 downto 0); |
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| 366 | signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos |
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| 367 | signal i_fifo1_rd_en : std_logic; |
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| 368 | signal fifo1_full : std_logic; |
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| 369 | signal i_fifo1_empty : std_logic; |
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| 370 | signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0); |
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| 371 | signal i_fifo2_rd_en : std_logic; |
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| 372 | signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0); |
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| 373 | signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0); |
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| 374 | signal i_fifo2_wr_en : std_logic; |
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| 375 | signal i_fifo2_empty : std_logic; |
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| 376 | signal i_fifo2_full : std_logic; |
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| 377 | signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 378 | signal Ex2_i_fifo2_wr_en : std_logic:='0'; |
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| 379 | --signaux pour les données entre modules |
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| 380 | signal Snd_Ack :std_logic; |
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| 381 | signal Rec_Rdy : std_logic; |
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| 382 | signal Rec_Data : Typ_PortIO(0 to 3); |
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| 383 | signal Snd_data : Typ_PortIO(0 to 3); |
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| 384 | signal Snd_Start : std_logic; |
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| 385 | signal Rec_Ack : std_logic; |
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| 386 | --signal i_fifo2_empty : std_logic; |
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| 387 | --signal i_fifo2_full : std_logic; |
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| 388 | signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 389 | signal Ex4_i_fifo2_wr_en : std_logic:='0'; |
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| 390 | --signal i_fifo2_empty : std_logic; |
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| 391 | --signal i_fifo2_full : std_logic; |
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| 392 | -- signaux pour la gestion des MAE |
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| 393 | signal n,n_i :natural range 0 to 7:=0; |
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| 394 | signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0; |
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| 395 | signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0; |
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| 396 | --=========================================================== |
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| 397 | |
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| 398 | begin |
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| 399 | --switch_port_in_data_signal <= ; |
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| 400 | --switch_port_out_data_signal <= ; |
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| 401 | -- istanciation des composants du core MPI |
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| 402 | Instruction_Fifo1: FIFO_64_FWFT PORT MAP( |
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| 403 | clk =>clk, |
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| 404 | din =>fifo1_din, |
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| 405 | rd_en => i_fifo1_rd_en, |
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| 406 | srst => reset, |
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| 407 | wr_en => fifo1_wr, |
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| 408 | dout =>i_fifo1_data_out, |
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| 409 | empty => i_fifo1_empty, |
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| 410 | full => fifo1_full |
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| 411 | ); |
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| 412 | |
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| 413 | Instruction_Fifo2: FIFO_64_FWFT PORT MAP( |
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| 414 | clk =>clk, |
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| 415 | din => i_fifo2_data_in , |
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| 416 | rd_en =>i_fifo2_rd_en, |
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| 417 | srst =>reset, |
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| 418 | wr_en =>i_fifo2_wr_en, |
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| 419 | dout =>i_fifo2_data_out, |
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| 420 | empty =>i_fifo2_empty, |
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| 421 | full => i_fifo2_full |
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| 422 | ); |
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| 423 | LD_instr:load_instr PORT MAP ( |
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| 424 | |
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| 425 | Instruction =>Instruction, |
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| 426 | Instruction_en =>Instruction_en, |
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| 427 | clk =>clk, |
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| 428 | reset =>reset, |
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| 429 | dma_rd_grant =>dma_rd_grant(3), |
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| 430 | dma_rd_request =>dma_rd_request(3), |
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| 431 | copying=> Exi_busy, |
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| 432 | instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO |
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| 433 | fifo_din => fifo1_din, |
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| 434 | fifo_wr => fifo1_wr, |
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| 435 | fifo_full =>fifo1_full, |
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| 436 | Ram_rd_en=> Exi_ram_rd, |
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| 437 | ram_address_rd => dma_rd_address3, |
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| 438 | ram_data =>dma_data_out --sortie DMA |
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| 439 | ); |
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| 440 | |
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| 441 | pushout(0)<=ILatch; |
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| 442 | pushout(1)<=IsMain; |
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| 443 | pushout(2)<=SizeSet; |
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[74] | 444 | pushout(3)<=Ex4_result(6); --Spawn in progress on main |
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[70] | 445 | pushout(4)<=Initialized; |
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| 446 | pushout(5)<=Ex1_result(1); -- |
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[74] | 447 | pushout(6)<=LibState(3); --Spawned child |
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| 448 | pushout(7)<=Ex4_result(7); --Spawn complete |
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[70] | 449 | MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( |
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| 450 | instruction => i_fifo1_data_out, |
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| 451 | instruction_en=> '1', |
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| 452 | uTimeResult => uTimeCount, |
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| 453 | TickResult => TickCount, |
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| 454 | Initialized => Initialized, -- indique si la l'appel à init a été concluant |
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| 455 | ClkRate => uClkRate, |
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| 456 | clk =>clk , |
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| 457 | reset => reset |
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| 458 | ); |
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| 459 | MPI_CORE_EX1_FSM: EX1_FSM PORT MAP( |
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| 460 | clk =>clk , |
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| 461 | reset =>reset, |
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| 462 | pid => MyRank, --port Id |
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| 463 | nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés |
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| 464 | fifo_empty => scheduler_fifo_empty , |
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| 465 | fifo_data_out =>scheduler_data_out, |
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| 466 | fifo_rd_en =>scheduler_rd_en, |
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| 467 | fifo_src =>fifo_sel, |
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| 468 | priority_rotation => scheduler_priority_rotation, |
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| 469 | |
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| 470 | instruction_en=>Ex_en(1), --active le module |
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| 471 | Instruction => Instruction, |
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| 472 | switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic |
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| 473 | switch_port_in_data =>Noc1.port_in_data, |
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| 474 | switch_port_in_wr_en =>Noc1.Port_in_wr_en , |
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| 475 | |
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| 476 | Snd_Data =>Snd_Data, |
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| 477 | Snd_Start =>Snd_start, |
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| 478 | Snd_Ack =>Snd_ack, |
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| 479 | Ram_rd => ex1_ram_rd, |
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| 480 | Ram_wr =>ex1_ram_wr, |
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| 481 | ram_data_in =>dma_data_out, |
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| 482 | Ram_data_out =>dma_data_in1, |
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| 483 | ram_address=>dma_wr_address1, |
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| 484 | --ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture |
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| 485 | dma_rd_request =>dma_rd_request(1), |
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| 486 | dma_wr_request =>dma_wr_request(1), |
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| 487 | dma_rd_grant =>dma_rd_grant(1) , |
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| 488 | dma_wr_grant =>dma_wr_grant(1) , |
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| 489 | |
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| 490 | AppInitReq => InitReq1, -- requête d'initialisation de l'application |
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| 491 | AppInitAck =>Res4_En , -- Acquitement d'initialisation |
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| 492 | Initialized=>Initialized, -- état de la Lib |
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| 493 | Result => Ex1_Result, -- le résultat de l'exécution |
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| 494 | Ready=> Ex1_Rdy |
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| 495 | ); |
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| 496 | instruction_fifo_full<=fifo1_full; |
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| 497 | dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM |
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| 498 | Exi_sync :process(reset,clk) |
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| 499 | |
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| 500 | begin |
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| 501 | if rising_edge(clk) then |
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| 502 | if reset='1' then |
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| 503 | St_Ex2<=0; |
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| 504 | St_Ex1<=0; |
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| 505 | St_Ex4<=0; |
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| 506 | Ilatch<='0'; |
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| 507 | n<=0; |
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| 508 | else |
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| 509 | St_Ex2<=Next_St_Ex2; |
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| 510 | St_Ex1<=Next_St_Ex1; |
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| 511 | St_Ex4<=Next_St_Ex4; |
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| 512 | ILatch<=Iack; |
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| 513 | n<=n_i; |
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| 514 | end if; |
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| 515 | end if; |
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| 516 | End process Exi_sync; |
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| 517 | -- détermination de l'activation des module |
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| 518 | --scheduler_priority_rotation<=not(Ex1_rdy); |
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| 519 | Ex1_Act:process(ST_Ex1,Initialized,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ???? |
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| 520 | variable c_cyl:natural range 0 to 15:=0; |
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| 521 | begin |
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| 522 | if reset='1' then |
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| 523 | Next_St_ex1<=0; |
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| 524 | c_cyl:=0; |
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| 525 | else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1 |
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| 526 | case St_ex1 is |
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| 527 | when 0 => if InitReq='1' and Initialized='0' then |
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| 528 | Next_St_ex1<=1; |
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[74] | 529 | elsif Initialized='1' then |
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[70] | 530 | Next_St_ex1 <=2; |
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| 531 | elsif fifo_instr='1' then --cas d'une instruction directe qui est présente |
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| 532 | --if fifo_sel='0' then |
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| 533 | Next_St_ex1 <=2; |
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| 534 | --end if; |
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| 535 | end if; |
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| 536 | |
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| 537 | when 1 => if Ex4_Rdy='1' then |
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| 538 | Next_St_ex1<=4; |
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| 539 | end if; |
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[74] | 540 | when 2 => if Ex1_rdy='0' then --ex1 est libre et actif |
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[70] | 541 | Next_St_ex1<=3; |
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| 542 | end if; |
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| 543 | |
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[74] | 544 | when 3 => if Ex1_rdy='1' and Initialized='0'then --ex1 est occupé et actif |
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| 545 | Next_St_ex1<=0; |
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| 546 | elsif Ex1_rdy='1' and Initialized='1' then |
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| 547 | Next_St_ex1<=2; |
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[70] | 548 | end if; |
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[74] | 549 | |
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[70] | 550 | when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau |
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| 551 | --compter quelques cycles d'horloges pour attendre initreq2 |
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| 552 | if n=4 then |
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| 553 | Next_St_ex1<=0; |
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| 554 | n_i<=0; |
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| 555 | else |
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| 556 | n_i<=n+1; |
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| 557 | end if; |
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| 558 | else |
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| 559 | Next_St_ex1<=0; |
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| 560 | end if; |
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| 561 | |
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| 562 | when others => |
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| 563 | Next_St_ex1<=0; |
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| 564 | end case; |
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| 565 | end if; |
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| 566 | end process ex1_Act; |
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| 567 | |
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| 568 | ex1_v:process(St_Ex1) |
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| 569 | begin |
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| 570 | case St_Ex1 is |
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| 571 | when 0 => |
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| 572 | Ex_en(1)<='0'; |
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| 573 | when 1 => |
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| 574 | Ex_en(1)<='0'; |
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| 575 | when 2|3 => |
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| 576 | Ex_en(1)<='1'; |
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| 577 | when others => |
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| 578 | Ex_en(1)<='0'; |
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| 579 | end case; |
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| 580 | |
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| 581 | end process ex1_v; |
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| 582 | |
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| 583 | Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué |
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| 584 | begin |
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| 585 | Next_St_Ex2<=st_Ex2; |
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| 586 | Case st_Ex2 is |
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| 587 | |
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| 588 | when 0 => |
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| 589 | if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then |
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| 590 | Next_St_Ex2<=1; --active la réception des mesages sur le noeud. |
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| 591 | |
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| 592 | else |
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| 593 | Next_St_Ex2<=0; |
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| 594 | end if; |
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| 595 | When 1 => |
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| 596 | if Ex2_rdy='0' then |
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| 597 | Next_St_Ex2<=2; |
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| 598 | end if; |
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| 599 | When 2 => |
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| 600 | if Ex2_rdy='1' then |
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| 601 | Next_St_Ex2<=0; |
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| 602 | end if; |
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| 603 | when others => |
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| 604 | Next_St_Ex2<=0; |
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| 605 | end case; |
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| 606 | end process; |
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| 607 | Ex2_val:Process(st_Ex2,Ex4_result) -- |
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| 608 | |
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| 609 | begin |
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| 610 | Case st_Ex2 is |
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| 611 | |
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| 612 | when 0 => |
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| 613 | Ex_en(2)<='0'; |
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[74] | 614 | --LibState(3)<='0'; |
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[70] | 615 | when 1|2 => |
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| 616 | Ex_en(2) <='1'; |
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| 617 | when 3|4|5|6|7 => |
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| 618 | Ex_en(2)<='0'; |
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| 619 | when others=> |
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| 620 | Ex_en(2)<='0'; |
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| 621 | end case; |
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| 622 | if rising_edge(Ex4_result(1)) then |
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| 623 | LibState(3)<='1'; --spawn a été détecté. |
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| 624 | end if; |
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| 625 | end process; |
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| 626 | |
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| 627 | Ex_en_proc:process (clk,reset) |
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| 628 | begin |
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| 629 | if rising_edge(clk) then |
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| 630 | if reset='1' then |
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| 631 | Ex4_en<='0'; |
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| 632 | else |
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| 633 | |
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| 634 | if Ex_en(4)='1' then |
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| 635 | Ex4_en<='1'; --synchro |
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| 636 | else |
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| 637 | Ex4_en<='0'; --synchro |
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| 638 | end if; |
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| 639 | end if; |
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| 640 | end if; |
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| 641 | end process; |
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| 642 | Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en) |
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| 643 | begin |
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| 644 | |
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| 645 | case St_Ex4 is |
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| 646 | when 0 => |
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| 647 | if (InitReq1='1') then |
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| 648 | Next_St_Ex4<=1; |
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| 649 | elsif InitReq2='1' then --le module 1 n'est pas actif |
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| 650 | Next_St_Ex4<=2; |
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| 651 | else |
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| 652 | Next_St_Ex4<=0; |
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| 653 | end if; |
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| 654 | when 1 => |
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| 655 | If Res4_en='1' then --fin de l'exécution du module |
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| 656 | Next_St_Ex4<=3; |
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| 657 | end if; |
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| 658 | when 2 => |
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| 659 | if Res4_en='1' then --Ex2_result(0)='1' |
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| 660 | Next_St_Ex4<=4; |
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| 661 | end if; |
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| 662 | when 3 => |
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| 663 | if initreq1='0' then |
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| 664 | Next_St_Ex4<=5; |
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| 665 | end if; |
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| 666 | when 4 => |
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| 667 | if initreq2='0' then |
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| 668 | Next_St_Ex4<=5; |
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| 669 | end if; |
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| 670 | when 5 => |
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| 671 | Next_St_Ex4<=0; |
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| 672 | when others => |
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| 673 | Next_St_Ex4<=0; |
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| 674 | end case; |
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| 675 | |
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| 676 | end process Ex4_active; |
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| 677 | |
---|
| 678 | Ex4_active_val:process (st_Ex4) |
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| 679 | begin |
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| 680 | case St_Ex4 is |
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| 681 | when 0 => |
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| 682 | AppReq<='0'; |
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| 683 | InitReq<='0';Ex_en(4)<='0'; |
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| 684 | AppAck<='0'; |
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| 685 | when 1 => |
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| 686 | AppReq<='1'; |
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| 687 | InitReq<='1'; |
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| 688 | Ex_en(4)<='1'; |
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| 689 | AppAck<='0'; |
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| 690 | when 2 => |
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| 691 | AppReq<='1'; |
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| 692 | InitReq<='1'; |
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| 693 | Ex_en(4)<='1'; |
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| 694 | AppAck<='0'; |
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| 695 | when 3 => |
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| 696 | AppReq<='0'; |
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| 697 | InitReq<='0'; |
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| 698 | Ex_en(4)<='0'; |
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| 699 | AppAck<='1'; |
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| 700 | when 4 => |
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| 701 | AppReq<='0'; |
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| 702 | InitReq<='0'; |
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| 703 | Ex_en(4)<='0'; |
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| 704 | AppAck<='1'; |
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| 705 | when 5 => |
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| 706 | AppReq<='0'; |
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| 707 | InitReq<='0';Ex_en(4)<='0'; |
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| 708 | AppAck<='1'; |
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| 709 | when others => |
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| 710 | AppReq<='0'; |
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| 711 | InitReq<='0'; |
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| 712 | AppAck<='0'; |
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| 713 | Ex_en(4)<='0'; |
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| 714 | end case ; |
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| 715 | -- Appreq<=Ex_en(4); --signal d'activation de la MAE Init |
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| 716 | --InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation |
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| 717 | --AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed |
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| 718 | end process Ex4_active_val; |
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| 719 | --Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ??? |
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| 720 | Ex_en(3)<='0'; |
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| 721 | --Ex_en(4)<= '1' when InitReq='1' else '0'; |
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| 722 | |
---|
| 723 | -- soit une requête du PE soit une requête du Core |
---|
| 724 | |
---|
| 725 | |
---|
| 726 | MPI_CORE_EX2_FSM: EX2_FSM PORT MAP( |
---|
| 727 | |
---|
| 728 | clk =>clk, |
---|
| 729 | reset =>reset, |
---|
| 730 | instruction_en=>Ex_en(2), |
---|
| 731 | Ready =>Ex2_rdy, --signale que le module est disponible |
---|
| 732 | fifo_full =>i_fifo2_full, |
---|
| 733 | |
---|
| 734 | fifo_wr_en => Ex2_i_fifo2_wr_en, |
---|
| 735 | fifo_data => Ex2_i_fifo2_data_in, |
---|
| 736 | |
---|
| 737 | switch_port_out_rd_en => Noc2.port_out_rd_en, |
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| 738 | switch_data_available =>Noc2.port_out_data_available, |
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| 739 | switch_port_out_data =>Noc2.port_out_data , |
---|
| 740 | |
---|
| 741 | Rec_Rdy => Rec_Rdy, |
---|
| 742 | Rec_Data =>Rec_Data, |
---|
| 743 | Rec_Ack =>Rec_Ack, |
---|
| 744 | -- il manque un signal pour valider l'accès à la RAM |
---|
| 745 | dma_wr_request =>dma_wr_request(2), |
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| 746 | dma_wr_grant =>dma_wr_grant(2), |
---|
| 747 | dma_rd_request =>dma_rd_request(2), |
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| 748 | dma_rd_grant =>dma_rd_grant(2), |
---|
| 749 | ram_address =>dma_wr_address2, |
---|
| 750 | Ram_rd => ex2_ram_rd, |
---|
| 751 | Ram_wr =>ex2_ram_wr, |
---|
| 752 | Ram_data_out=> Dma_data_out, |
---|
| 753 | Ram_data_in => Dma_data_in2, |
---|
| 754 | packet_received =>packet_received, |
---|
| 755 | packet_ack => packet_ack, |
---|
| 756 | barrier_completed =>barrier_completed, |
---|
| 757 | AppRank =>MyRank, |
---|
| 758 | AppSize =>MPISize, |
---|
| 759 | AppInitReq => InitReq2, -- requête d'initialisation de l'application |
---|
| 760 | AppInitAck =>Res4_En , -- Acquitement d'initialisation |
---|
| 761 | Initialized=>Initialized, |
---|
| 762 | Result => Ex2_Result -- le résultat de l'exécution |
---|
| 763 | ); |
---|
| 764 | Dma_rd_address2<=Dma_wr_address2; |
---|
| 765 | ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( |
---|
[74] | 766 | instruction => x"00", --pas utiliser |
---|
[70] | 767 | ResOut => RankSize, |
---|
| 768 | clk =>clk , |
---|
| 769 | IsMain=>IsMain, |
---|
| 770 | reset => reset |
---|
| 771 | ); |
---|
| 772 | MPI_CORE_EX4_FSM :EX4_FSM PORT MAP ( |
---|
| 773 | Instruction => Instr_in, --STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 774 | Instruction_En =>Ex4_en, -- ='1' lorsque ce module est sollicité |
---|
| 775 | clk =>clk, |
---|
| 776 | reset =>reset, |
---|
| 777 | ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 778 | Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module |
---|
| 779 | Ready => Ex4_Rdy, |
---|
| 780 | NocSize =>NocSize, |
---|
| 781 | AppRank =>MyRank, |
---|
| 782 | AppSize =>MPISize, |
---|
| 783 | IsMain =>IsMain, |
---|
| 784 | Rec_Rdy => Rec_Rdy, |
---|
| 785 | Rec_Data =>Rec_Data, |
---|
| 786 | Rec_Ack =>Rec_Ack, |
---|
| 787 | Snd_Ack =>Snd_ack, |
---|
| 788 | Snd_data =>Snd_data, |
---|
| 789 | Snd_Start =>Snd_Start, |
---|
| 790 | |
---|
| 791 | I_fifo_full =>i_fifo2_full, |
---|
| 792 | |
---|
| 793 | I_fifo_wr_en => Ex4_i_fifo2_wr_en, |
---|
| 794 | I_fifo_data_in => Ex4_i_fifo2_data_in, |
---|
| 795 | Initialized =>Initialized, |
---|
| 796 | Ram_data_out => Dma_data_out, |
---|
| 797 | Ram_address =>dma_wr_Address4, --accès au stockage |
---|
| 798 | Ram_wr =>Ex4_Ram_wr, --activation de l'écriture en RAM |
---|
| 799 | Ram_data_in =>Dma_data_in4, --données à écrire en RAM |
---|
| 800 | DMA_rd_Request => dma_rd_request(4), |
---|
| 801 | DMA_rd_grant => dma_rd_grant(4), |
---|
| 802 | DMA_wr_Request => dma_wr_request(4), |
---|
| 803 | DMA_wr_grant => dma_wr_grant(4), |
---|
| 804 | AppAck =>AppAck, |
---|
| 805 | AppReq =>InitReq, |
---|
| 806 | PortId=>PortId, |
---|
| 807 | port_in_cmd_en => Noc3.port_in_cmd_en, |
---|
| 808 | port_in_wr_en =>Noc3.port_in_wr_en, |
---|
| 809 | port_in_empty =>Noc3.port_in_empty, |
---|
| 810 | port_in_full =>Noc3.port_in_full, |
---|
| 811 | port_in_data =>Noc3.port_in_data, |
---|
| 812 | port_out_data =>Noc3.port_out_data, |
---|
| 813 | port_out_rd_en =>Noc3.port_out_rd_en, |
---|
| 814 | port_out_data_available =>Noc3.port_out_data_available |
---|
| 815 | |
---|
| 816 | |
---|
| 817 | ); |
---|
| 818 | --=============Mux des signaux d'accès à la RAM========= |
---|
| 819 | ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement |
---|
| 820 | Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM |
---|
| 821 | |
---|
| 822 | --dma_data_in <=dma_data_in1 or dma_data_in2; |
---|
| 823 | --dma_data_out <=dma_data_out1 or dma_data_out2; |
---|
| 824 | mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3, |
---|
[15] | 825 | ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd ) |
---|
| 826 | begin |
---|
| 827 | case dma_rd_grant is |
---|
[70] | 828 | when "0001" => dma_rd_address <= dma_rd_address1; |
---|
[15] | 829 | rdram<= ex1_ram_rd; |
---|
[70] | 830 | when "0010" => dma_rd_address <= dma_rd_address2; |
---|
[15] | 831 | rdram<= ex2_ram_rd; |
---|
[70] | 832 | when "0100" => dma_rd_address <= dma_rd_address3; |
---|
[15] | 833 | rdram<= exi_ram_rd; |
---|
| 834 | -- when "1000" => dma_rd_address <= <input4>; |
---|
[72] | 835 | when others => dma_rd_address <= (others =>'0'); |
---|
[15] | 836 | rdram<='0'; |
---|
| 837 | end case; |
---|
[70] | 838 | end process; |
---|
[74] | 839 | mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4, |
---|
| 840 | ex1_ram_wr,ex2_ram_wr,ex4_ram_wr) |
---|
[15] | 841 | begin |
---|
| 842 | case dma_wr_grant is |
---|
[70] | 843 | |
---|
| 844 | when "0001" => dma_wr_address <= dma_wr_address1; |
---|
| 845 | weram<=ex1_ram_wr ; |
---|
| 846 | Dma_data_in<=Dma_data_in1; |
---|
| 847 | when "0010" => dma_wr_address <= dma_wr_address2; |
---|
| 848 | weram<=ex2_ram_wr ; |
---|
[15] | 849 | Dma_data_in<=Dma_data_in2; |
---|
[70] | 850 | when "1000" => dma_wr_address <= dma_wr_address4; |
---|
| 851 | weram<=ex4_ram_wr; |
---|
[15] | 852 | Dma_data_in<=Dma_data_in4; |
---|
[72] | 853 | when others => dma_wr_address <= (others =>'0'); |
---|
[15] | 854 | weram<='0'; |
---|
| 855 | end case; |
---|
[70] | 856 | end process; |
---|
| 857 | --====================================================== |
---|
| 858 | |
---|
| 859 | --=================Mux des signaux qui vont au switch============ |
---|
| 860 | clkout<=clk; -- permettra le lien avec le module du switch |
---|
| 861 | |
---|
| 862 | NOC1.port_out_data<=switch_port_out_data; |
---|
| 863 | NOC1.port_out_data_available<=switch_port_out_data_vailaible; |
---|
| 864 | NOC1.port_in_empty<=switch_port_in_empty; |
---|
| 865 | NOC1.port_in_full<=switch_port_in_full; |
---|
| 866 | |
---|
| 867 | NOC2.port_out_data<=switch_port_out_data; |
---|
| 868 | NOC2.port_out_data_available<=switch_port_out_data_vailaible; |
---|
| 869 | NOC2.port_in_empty<=switch_port_in_empty; |
---|
| 870 | NOC2.port_in_full<=switch_port_in_full; |
---|
| 871 | |
---|
| 872 | NOC3.port_out_data<=switch_port_out_data; |
---|
| 873 | NOC3.port_out_data_available<=switch_port_out_data_vailaible; |
---|
| 874 | NOC3.port_in_empty<=switch_port_in_empty; |
---|
| 875 | NOC3.port_in_full<=switch_port_in_full; |
---|
| 876 | mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2, |
---|
[74] | 877 | ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en, |
---|
| 878 | instruction,ex2_result) |
---|
[70] | 879 | |
---|
| 880 | begin |
---|
| 881 | case Ex_en is |
---|
| 882 | |
---|
| 883 | when"0001" => |
---|
| 884 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 885 | switch_port_out_rd_en<=NOC2.port_out_rd_en; |
---|
| 886 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 887 | switch_port_in_cmd_en <='0'; |
---|
| 888 | when "0010"|"0011" => |
---|
| 889 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 890 | switch_port_out_rd_en<=NOC2.port_out_rd_en; |
---|
| 891 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 892 | switch_port_in_cmd_en <='0'; |
---|
| 893 | i_fifo2_wr_en<=ex2_i_fifo2_wr_en; |
---|
| 894 | i_fifo2_data_in<=ex2_i_fifo2_data_in; |
---|
| 895 | when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!! |
---|
| 896 | if initreq2='1' then |
---|
| 897 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 898 | switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 899 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 900 | switch_port_in_cmd_en <='0'; |
---|
| 901 | else |
---|
| 902 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 903 | switch_port_out_rd_en<=NOC2.port_out_rd_en; |
---|
| 904 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 905 | switch_port_in_cmd_en <='0'; |
---|
| 906 | end if; |
---|
| 907 | i_fifo2_wr_en<=ex2_i_fifo2_wr_en; |
---|
| 908 | i_fifo2_data_in<=ex2_i_fifo2_data_in; |
---|
| 909 | when "1001" => --ca où un appel à init est effectué |
---|
| 910 | if initialized='0' then |
---|
| 911 | switch_port_in_data <=Noc3.port_in_data; |
---|
| 912 | switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 913 | switch_port_in_wr_en <=NOC3.port_in_wr_en; |
---|
| 914 | switch_port_in_cmd_en <=NOC3.port_in_cmd_en; |
---|
| 915 | else |
---|
| 916 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 917 | switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 918 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 919 | end if; |
---|
| 920 | i_fifo2_wr_en<=ex4_i_fifo2_wr_en; |
---|
| 921 | i_fifo2_data_in<=ex4_i_fifo2_data_in; |
---|
| 922 | when "1010" => --ca où un appel à init est effectué |
---|
| 923 | --switch_port_in_data <=Noc3.port_in_data; |
---|
| 924 | -- switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 925 | -- switch_port_in_wr_en <=NOC3.port_in_wr_en; |
---|
| 926 | -- switch_port_in_cmd_en <=NOC3.port_in_cmd_en; |
---|
| 927 | switch_port_in_data <=Noc1.port_in_data; |
---|
| 928 | switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 929 | switch_port_in_wr_en <=NOC1.port_in_wr_en; |
---|
| 930 | i_fifo2_wr_en<=ex4_i_fifo2_wr_en; |
---|
| 931 | i_fifo2_data_in<=ex4_i_fifo2_data_in; |
---|
| 932 | when others => --permet de gérer le cas où un spawn arrive par le réseau |
---|
| 933 | switch_port_in_data <=Noc3.port_in_data; |
---|
| 934 | switch_port_out_rd_en<=NOC3.port_out_rd_en; |
---|
| 935 | switch_port_in_wr_en <=NOC3.port_in_wr_en; |
---|
| 936 | switch_port_in_cmd_en <=NOC3.port_in_cmd_en; |
---|
| 937 | |
---|
| 938 | i_fifo2_wr_en<=ex4_i_fifo2_wr_en; |
---|
| 939 | i_fifo2_data_in<=ex4_i_fifo2_data_in; |
---|
| 940 | end case; |
---|
| 941 | Instr_in <=Instruction ; |
---|
| 942 | if initreq2='1' and Ex_en(4)='1' then |
---|
| 943 | Instr_in <=Ex2_Result ; |
---|
| 944 | else |
---|
| 945 | Instr_in <=Instruction ; |
---|
| 946 | end if; |
---|
| 947 | i_fifo2_wr_en<=ex2_i_fifo2_wr_en; |
---|
| 948 | i_fifo2_data_in<=ex2_i_fifo2_data_in; |
---|
| 949 | end process; |
---|
| 950 | |
---|
| 951 | |
---|
| 952 | --=============================================================== |
---|
| 953 | MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP( |
---|
| 954 | clk =>clk, |
---|
| 955 | reset =>reset, |
---|
| 956 | |
---|
| 957 | data_wr_mem => ram_data_in, --vers RAM |
---|
| 958 | |
---|
| 959 | data_rd_mem => Ram_data_out, --- Vers RAM |
---|
| 960 | address_rd =>dma_rd_address, |
---|
| 961 | address_wr =>dma_wr_address, |
---|
| 962 | address_out_rd =>ram_address_rd, |
---|
| 963 | address_out_wr =>ram_address_wr, |
---|
| 964 | ram_en => ram_env, --validation lecture |
---|
| 965 | ram_we =>ram_wev, --validation écriture |
---|
| 966 | hold_req=>hold_req,--demande de bus à l'application |
---|
| 967 | hold_ack=>hold_ack, -- libération du bus RAM par l'application |
---|
| 968 | |
---|
| 969 | data_rd_out => Dma_data_out, --vers périphérique |
---|
| 970 | data_wr_in =>Dma_data_in, --vers périphérique |
---|
| 971 | dma_wr_grant =>dma_wr_grant, |
---|
| 972 | dma_rd_request => dma_rd_request, |
---|
| 973 | dma_rd_grant => dma_rd_grant, |
---|
| 974 | dma_wr_request => dma_wr_request |
---|
| 975 | ); |
---|
| 976 | |
---|
| 977 | |
---|
| 978 | CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction |
---|
| 979 | -- qui sera exécutée par la MAE EX1 |
---|
| 980 | clk => clk, |
---|
| 981 | reset => reset, |
---|
| 982 | priority_rotation =>scheduler_priority_rotation, |
---|
| 983 | instruction_fifo_empty =>i_fifo1_empty, |
---|
| 984 | get_request_fifo_empty => i_fifo2_empty, |
---|
| 985 | instruction_fifo_rd_en =>i_fifo1_rd_en, |
---|
| 986 | get_request_fifo_rd_en =>i_fifo2_rd_en , |
---|
| 987 | instruction_fifo_data =>i_fifo1_data_out, |
---|
| 988 | get_request_fifo_data =>i_fifo2_data_out, |
---|
| 989 | fifo_selected =>fifo_sel, |
---|
| 990 | instruction_available => fifo_instr, |
---|
| 991 | fifo_empty => scheduler_fifo_empty, |
---|
| 992 | fifo_rd_en =>scheduler_rd_en, |
---|
| 993 | data_out => scheduler_data_out |
---|
| 994 | ); |
---|
| 995 | |
---|
| 996 | end structural; |
---|
| 997 | |
---|