[70] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer:GAMOM /KIEGAING |
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| 4 | -- |
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| 5 | -- Create Date: 08:12:29 06/16/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: EX1_FSM - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Ce module est chargé de recevoir les instructions du programme MPI et |
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| 12 | -- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC |
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| 13 | -- (GET) |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: 09/07/2012 |
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| 18 | -- Revision 0.03 - File updated |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | library NocLib ; |
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| 27 | use Work.Packet_type.ALL; |
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| 28 | USE ieee.numeric_std.ALL; |
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| 29 | |
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| 30 | |
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| 31 | use NocLib.CoreTypes.all; |
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| 32 | ---- Uncomment the following library declaration if instantiating |
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| 33 | ---- any Xilinx primitives in this code. |
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| 34 | --library UNISIM; |
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| 35 | --use UNISIM.VComponents.all; |
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| 36 | |
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| 37 | entity EX1_FSM is |
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| 38 | -- parametres generiques du module : |
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| 39 | |
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| 40 | |
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| 41 | Port ( |
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| 42 | --instruction_available : in STD_LOGIC; |
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| 43 | clk : in STD_LOGIC; |
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| 44 | reset : in STD_LOGIC; |
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| 45 | instruction : in std_logic_vector(Word-1 downto 0); |
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| 46 | instruction_en : in std_logic:='0'; -- active le module instruction |
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| 47 | pid : in std_logic_vector(3 downto 0) ; -- id du processeur |
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| 48 | nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 |
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| 49 | Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module |
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| 50 | Ready : out std_logic; --indique la fin de l'éxécution d'une instruction |
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| 51 | AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application |
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| 52 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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| 53 | Initialized:in std_logic ; -- état de la Lib |
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| 54 | -- Accès au Fifo d'instructions |
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| 55 | priority_rotation : out STD_LOGIC:='0'; |
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| 56 | fifo_rd_en : out STD_LOGIC:='0'; |
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| 57 | fifo_empty : in STD_LOGIC; |
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| 58 | fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); |
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| 59 | fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service |
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| 60 | |
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| 61 | |
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| 62 | Snd_Data : IN Typ_PortIO(0 to 3); |
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| 63 | Snd_Start : IN std_logic; |
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| 64 | Snd_Ack : OUT std_logic; |
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| 65 | |
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| 66 | -- Accès au réseau sur puce |
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| 67 | switch_port_in_full : in std_logic; |
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[72] | 68 | switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); |
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[70] | 69 | switch_port_in_wr_en : out STD_LOGIC:='0'; |
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| 70 | -- Accès à la mémoire RAM du PE |
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| 71 | ram_data_in : in std_logic_vector(7 downto 0); |
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| 72 | ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); |
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| 73 | ram_rd,ram_wr : out std_logic:='0'; |
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[72] | 74 | ram_address : out std_logic_vector(15 downto 0):=(others=>'0'); |
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[70] | 75 | |
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| 76 | dma_wr_request : OUT std_logic:='0'; |
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| 77 | dma_rd_request : OUT std_logic:='0'; |
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| 78 | dma_wr_grant : in STD_LOGIC; |
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| 79 | dma_rd_grant : in STD_LOGIC); |
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| 80 | end EX1_FSM; |
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| 81 | |
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| 82 | architecture Behavioral of EX1_FSM is |
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| 83 | |
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| 84 | component proto_send is |
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| 85 | generic (sizemem : natural := 64); |
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| 86 | port ( |
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| 87 | clk,reset : in std_logic; |
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| 88 | fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée |
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| 89 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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| 90 | fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie |
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| 91 | fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée |
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| 92 | fifo_in_data_out : in std_logic_vector(Word-1 downto 0); |
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| 93 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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| 94 | packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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| 95 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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| 96 | snd_start : in std_logic; --début de la réception |
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| 97 | snd_ack :in std_logic; -- acquittement de la réception |
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| 98 | snd_comp : out std_logic; -- fin de la réception |
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| 99 | mem :in memory(0 to sizemem-1)); --données à copier vers le fifo |
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| 100 | |
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| 101 | |
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| 102 | end component proto_send; |
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| 103 | -- definition du type etat pour le codage des etats des fsm |
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| 104 | type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, |
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| 105 | decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4, |
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| 106 | ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5, |
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[72] | 107 | ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync); |
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[70] | 108 | -- machine a etat du module |
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| 109 | signal ex1_state,Next_Ex1_state : fsm_states; |
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| 110 | |
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| 111 | -- les variables utilisées dans la fsm |
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| 112 | signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0'; |
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| 113 | signal mem : memory(0 to 3); |
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| 114 | signal data_to_send,noc_fifo_in : std_logic_vector(Word-1 downto 0); |
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| 115 | signal packet_type : std_logic_vector(3 downto 0); |
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| 116 | --signal dpid : std_logic_vector(3 downto 0); |
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| 117 | signal pid_counter : std_logic_vector(3 downto 0); |
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| 118 | signal p_len,p_len_i: std_logic_vector(Word-1 downto 0); |
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| 119 | signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0); |
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| 120 | signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; |
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| 121 | --signal res_address : std_logic_vector(15 downto 0); |
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| 122 | signal dest_address : std_logic_vector(ADRLEN-1 downto 0); |
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| 123 | signal n,n_i : natural range 0 to 15; |
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| 124 | signal len,len_i : natural range 0 to 255; |
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| 125 | signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0'; |
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| 126 | signal fifo_sel:std_logic:='0'; |
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| 127 | signal run_init:std_logic:='0'; |
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| 128 | begin |
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| 129 | -- connection des signaux avec les ports |
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| 130 | ram_address <= src_address; |
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| 131 | sw_send: proto_send generic map (sizemem=>4) |
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| 132 | port map ( |
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| 133 | clk=>clk, |
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| 134 | reset=>reset, |
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| 135 | fifo_in_empty=>fifo_empty, |
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| 136 | fifo_in_full=>'0',--pas utilisé |
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| 137 | fifo_out_empty=>'0', |
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| 138 | packet_len=>p_len, |
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| 139 | copy_mode=>fifo_copy, |
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| 140 | fifo_out_full => switch_port_in_full, |
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| 141 | fifo_in_rd_en=>fifo_rd, |
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| 142 | fifo_in_data_out=>fifo_data_out, |
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| 143 | fifo_out_wr_en =>fifo_wr, |
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| 144 | |
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| 145 | fifo_out_data_in =>noc_fifo_in, |
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| 146 | snd_start =>snd_start_sync, |
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| 147 | snd_ack =>snd_ack1, |
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| 148 | snd_comp=>snd_comp, |
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| 149 | mem =>mem |
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| 150 | ); |
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| 151 | ex1_fsm_sync:process(clk) |
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| 152 | |
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| 153 | begin |
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| 154 | if rising_edge(clk) then |
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| 155 | if reset = '1' then |
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| 156 | ex1_state <= fifo_select; |
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| 157 | n<=0; |
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| 158 | len<=0; |
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| 159 | p_len<=(others=>'0'); |
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| 160 | snd_ack<='0'; |
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| 161 | src_address<=(others=>'0'); |
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| 162 | else |
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| 163 | ex1_state<=next_ex1_state; |
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| 164 | n<=n_i; |
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| 165 | len<=len_i; |
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| 166 | p_len<=p_len_i; |
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| 167 | src_address <= src_address_i; |
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| 168 | snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4 |
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| 169 | snd_start_sync<=snd_start1; |
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| 170 | end if; |
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| 171 | end if; |
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| 172 | end process ex1_fsm_sync; |
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| 173 | -- processus de transistion entre les etats |
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| 174 | fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, |
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[74] | 175 | pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address, |
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| 176 | fifo_src,dest_address,packet_type) |
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[70] | 177 | variable tempval : std_logic_vector(Word-1 downto 0); |
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| 178 | variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé |
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| 179 | begin |
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| 180 | n_i<=n; --valeur par défaut |
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| 181 | Next_ex1_state <=Ex1_state; |
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| 182 | case ex1_state is |
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| 183 | when fifo_select => if instruction_en='1' and fifo_empty ='0' then |
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| 184 | Next_ex1_state <= fetch_packet_type; |
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| 185 | else |
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| 186 | Next_ex1_state <= fifo_select; |
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| 187 | end if; |
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| 188 | rd_ok<='0'; |
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| 189 | wr_ok<='0'; |
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| 190 | if instruction_en='1' and snd_start='1' then |
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| 191 | run_init<='1'; |
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| 192 | Next_ex1_state<=ex1_init_run; |
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[74] | 193 | else |
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| 194 | run_init<='0'; |
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[70] | 195 | end if; |
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| 196 | --lecture du registre status de la mib MPI |
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| 197 | when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put |
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| 198 | Next_ex1_state <= read_status2; |
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| 199 | else |
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| 200 | Next_ex1_state <= read_status1; |
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| 201 | end if; |
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| 202 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); |
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| 203 | when read_status2 => |
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| 204 | Next_ex1_state <= fifo_select; |
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| 205 | when fetch_packet_type => rd_ok<='0'; |
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| 206 | if fifo_empty ='1' then |
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| 207 | Next_ex1_state <= fifo_select; |
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| 208 | else |
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| 209 | packet_type <= fifo_data_out(7 downto 4); |
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| 210 | data_to_send <= fifo_data_out; |
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| 211 | Next_ex1_state <= decode_packet_type; |
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| 212 | rd_ok<='1'; |
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| 213 | end if; |
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| 214 | when decode_packet_type => rd_ok<='0'; |
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| 215 | if fifo_empty='0' then |
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| 216 | if packet_type = MPI_PUT then |
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| 217 | p_len_i <= fifo_data_out + 4; |
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| 218 | n_i <= 0;rd_ok<='1'; |
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| 219 | Next_ex1_state <= fetch_addresses; |
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| 220 | elsif packet_type = MPI_GET then |
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| 221 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 222 | p_len_i <= fifo_data_out; |
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| 223 | n_i <= 0; rd_ok<='1'; |
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| 224 | Next_ex1_state <= fetch_addresses; |
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| 225 | elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then |
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| 226 | p_len_i <= "00000011"; -- = 3 |
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| 227 | pid_counter <= "0000"; |
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| 228 | rd_ok<='1'; |
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| 229 | Next_ex1_state <= ex1_barrier1; |
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| 230 | elsif packet_type = MPI_INIT then |
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| 231 | Next_ex1_state<=ex1_init1; |
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| 232 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 233 | p_len_i<=fifo_data_out; |
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| 234 | n_i<=0;rd_ok<='1'; |
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| 235 | elsif packet_type = MPI_ACK then |
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| 236 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 237 | p_len_i<=fifo_data_out; |
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| 238 | n_i <= 0; rd_ok<='0'; |
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| 239 | Next_ex1_state <= ex1_send_Ack; |
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[72] | 240 | elsif packet_type = MPI_WIN_SYNC then |
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| 241 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 242 | p_len_i<=fifo_data_out; |
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| 243 | n_i <= 0; rd_ok<='0'; |
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| 244 | Next_ex1_state <= ex1_WSynC; |
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[70] | 245 | elsif packet_type = MPI_SPAWN then |
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| 246 | Next_ex1_state<=ex1_SPAWN; |
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| 247 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 248 | p_len_i<=fifo_data_out; |
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| 249 | onepop:='1';--il y a une donnée lue |
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| 250 | src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16)); |
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| 251 | rd_ok<='0'; |
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| 252 | else -- packet non reconnu |
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| 253 | --synthesis translate_off |
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| 254 | report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ; |
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| 255 | --synthesis translate_on |
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| 256 | if fifo_empty = '1' then |
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| 257 | Next_ex1_state <= fifo_select; |
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| 258 | |
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| 259 | else |
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| 260 | rd_ok<='1'; |
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| 261 | packet_type <= fifo_data_out(7 downto 4); --lire le prochain paquet |
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| 262 | data_to_send <= fifo_data_out; |
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| 263 | Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure |
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| 264 | end if; |
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| 265 | end if; |
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| 266 | end if; |
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| 267 | when fetch_addresses => n_i<=n;rd_ok<='1'; |
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| 268 | if fifo_empty = '0' and n = 0 then |
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| 269 | src_address_i(15 downto 8) <= fifo_data_out; |
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| 270 | n_i <= n + 1; |
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| 271 | Next_ex1_state <= fetch_addresses; |
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| 272 | elsif fifo_empty = '0' and n = 1 then |
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| 273 | src_address_i(7 downto 0) <= fifo_data_out; |
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| 274 | n_i <= n + 1; |
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| 275 | Next_ex1_state <= fetch_addresses; |
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| 276 | elsif fifo_empty = '0' and n = 2 then |
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| 277 | dest_address(15 downto 8) <= fifo_data_out; |
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| 278 | n_i <= n + 1; |
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| 279 | Next_ex1_state <= fetch_addresses; |
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| 280 | elsif fifo_empty = '0' and n = 3 then |
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| 281 | dest_address(7 downto 0) <= fifo_data_out; |
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| 282 | n_i <= n+1; |
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| 283 | elsif n=4 then |
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| 284 | rd_ok<='0'; |
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| 285 | n_i<=0; |
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| 286 | Next_ex1_state <= decode_packet_type2; |
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| 287 | elsif fifo_empty='1' then |
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| 288 | rd_ok<='0'; |
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| 289 | Next_ex1_state <= fetch_addresses; --attendre les données manquantes |
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| 290 | else |
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| 291 | Next_ex1_state <= fifo_select; |
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| 292 | end if; |
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| 293 | when decode_packet_type2 => if packet_type = MPI_PUT then |
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| 294 | Next_ex1_state <= ex1_put1; |
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| 295 | elsif packet_type = MPI_GET then |
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| 296 | Next_ex1_state <= ex1_get1; |
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| 297 | end if; |
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| 298 | -- execution du mpi put |
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| 299 | when ex1_put1 => if dma_rd_grant = '1' then |
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| 300 | Next_ex1_state <= ex1_put2; |
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| 301 | else |
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| 302 | Next_ex1_state <= ex1_put1; |
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| 303 | end if; |
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| 304 | Wr_ok<='0'; |
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| 305 | when ex1_put2 =>Wr_ok<='0'; |
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| 306 | if switch_port_in_full = '0' and n = 0 then |
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| 307 | --envoie du code MPI_PUT |
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| 308 | n_i<= n + 1; |
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| 309 | wr_ok<='1'; |
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| 310 | Next_ex1_state <= ex1_put2; |
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| 311 | elsif switch_port_in_full = '0' and n = 1 then |
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| 312 | data_to_send <= p_len; |
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| 313 | n_i<= n + 1; |
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| 314 | wr_ok<='1'; |
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| 315 | Next_ex1_state <= ex1_put2; |
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| 316 | elsif switch_port_in_full = '0' and n = 2 then |
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| 317 | data_to_send <= dest_address(15 downto 8); |
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| 318 | n_i<= n + 1; |
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| 319 | wr_ok<='1'; |
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| 320 | Next_ex1_state <= ex1_put2; |
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| 321 | elsif switch_port_in_full = '0' and n = 3 then |
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| 322 | data_to_send <= dest_address(7 downto 0); |
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| 323 | n_i<= n +1; |
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| 324 | wr_ok<='1'; |
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| 325 | Next_ex1_state <= ex1_put2; |
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| 326 | elsif switch_port_in_full = '0' and n = 4 then |
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| 327 | p_len_i <= p_len - 4; |
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| 328 | Next_ex1_state <= ex1_put3; |
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| 329 | Wr_ok<='0'; |
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| 330 | n_i<=0; |
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| 331 | else |
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| 332 | Next_ex1_state <= ex1_put2; |
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| 333 | end if; |
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| 334 | when ex1_put3 => wr_ok<='0'; |
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| 335 | if unsigned(p_len)>0 then |
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| 336 | --if n=0 then |
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| 337 | -- n_i<=1; --cycle d'attente pour la RAM |
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| 338 | -- Wr_ok<='0'; |
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| 339 | -- elsif n=1 then |
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| 340 | if switch_port_in_full = '0' then |
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| 341 | if n=1 then --creer un délai sur ces signaux par rapport à src_adress |
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| 342 | p_len_i <= p_len - 1; |
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| 343 | Wr_Ok<='1'; |
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| 344 | end if; |
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| 345 | n_i<=1; |
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| 346 | src_address_i <= src_address+1; |
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| 347 | Next_ex1_state <= ex1_put3; |
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| 348 | |
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| 349 | |
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| 350 | else |
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| 351 | Wr_Ok<='0'; |
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| 352 | src_address_i <= src_address; |
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| 353 | n_i<=0; |
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| 354 | end if; |
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| 355 | --elsif n=2 then |
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| 356 | -- n_i<=0; --cycle d'attente pour la RAM |
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| 357 | -- Wr_ok<='0'; |
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| 358 | -- src_address_i <= src_address ; --prochaine lecture |
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| 359 | -- |
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| 360 | -- end if; |
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| 361 | else |
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| 362 | Wr_Ok<='0'; |
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| 363 | Next_ex1_state <= ex1_put4; |
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| 364 | end if; |
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[72] | 365 | when ex1_put4 =>rd_ok<='1'; |
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| 366 | wr_ok<='0'; |
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| 367 | if dma_rd_grant = '1' then -- fin du mpi_put |
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[70] | 368 | Next_ex1_state <= ex1_put5; |
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[72] | 369 | rd_ok<='0'; |
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[70] | 370 | n_i<=0; |
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| 371 | data_to_send<="00000001"; |
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| 372 | else |
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| 373 | Next_ex1_state <= ex1_put4; |
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| 374 | end if; |
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[72] | 375 | |
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| 376 | if fifo_src='0' then --détection Put ou Get |
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| 377 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
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| 378 | else |
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| 379 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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| 380 | end if; |
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| 381 | when ex1_put5 => if n >0 then |
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[70] | 382 | |
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| 383 | dma_wr<='1'; --demander un accès exclusif au bus |
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| 384 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
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| 385 | else |
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| 386 | dma_wr<='0'; |
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| 387 | dma_rd<='0'; |
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| 388 | end if; |
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| 389 | |
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| 390 | if n=0 then |
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[72] | 391 | |
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| 392 | n_i<=n+1; |
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| 393 | elsif n=1 then |
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[70] | 394 | if dma_rd_grant='1' then |
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| 395 | n_i<=n+1; |
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| 396 | |
---|
| 397 | end if; |
---|
| 398 | rd_ok<='1'; |
---|
| 399 | wr_ok<='0'; |
---|
| 400 | dma_wr<='1'; |
---|
| 401 | dma_rd<='1'; |
---|
[72] | 402 | elsif n=2 then |
---|
[70] | 403 | if dma_rd_grant='1' then |
---|
| 404 | n_i<=n+1; |
---|
| 405 | dma_wr<='1'; |
---|
[72] | 406 | tempval:=Ram_data_in; |
---|
[70] | 407 | end if; |
---|
| 408 | rd_ok<='1'; |
---|
| 409 | wr_ok<='0'; |
---|
| 410 | |
---|
| 411 | dma_rd<='1'; |
---|
[72] | 412 | elsif n=3 then |
---|
[70] | 413 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
| 414 | n_i<=n+1; |
---|
| 415 | tempval:=Ram_data_in; |
---|
[72] | 416 | --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
[70] | 417 | if fifo_src='0' then -- c'est un put qui est exécuté |
---|
| 418 | tempval(5):='1'; -- SET du bit DSENT |
---|
| 419 | else -- c'est un Get qui est exécuté |
---|
[72] | 420 | tempval(2):='1'; -- ne pas annuler le sending après un GET |
---|
[70] | 421 | end if; |
---|
| 422 | data_to_send<=tempval; |
---|
| 423 | rd_ok<='0'; |
---|
| 424 | wr_ok<='1'; |
---|
| 425 | dma_wr<='1'; |
---|
| 426 | dma_rd<='1'; |
---|
| 427 | else |
---|
| 428 | rd_ok<='1'; |
---|
| 429 | wr_ok<='0'; |
---|
| 430 | dma_rd<='0'; --libérer le bus et revenir en arrière |
---|
| 431 | dma_wr<='0'; |
---|
[72] | 432 | n_i<=0; |
---|
[70] | 433 | end if; |
---|
| 434 | elsif n=3 then |
---|
| 435 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
---|
| 436 | n_i<=n+1; |
---|
| 437 | |
---|
[72] | 438 | --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
[70] | 439 | end if; |
---|
| 440 | rd_ok<='0'; |
---|
| 441 | wr_ok<='1'; |
---|
| 442 | dma_wr<='1'; |
---|
| 443 | dma_rd<='1'; |
---|
| 444 | elsif n=4 then |
---|
| 445 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
---|
| 446 | n_i<=n+1; |
---|
| 447 | |
---|
| 448 | src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16)); |
---|
| 449 | |
---|
| 450 | end if; |
---|
| 451 | rd_ok<='0'; |
---|
| 452 | wr_ok<='1'; |
---|
| 453 | dma_wr<='1'; |
---|
| 454 | dma_rd<='0'; |
---|
| 455 | elsif n=5 then |
---|
| 456 | if dma_wr_grant = '1' then |
---|
| 457 | n_i<=n+1; |
---|
| 458 | |
---|
| 459 | -- SET du bit DSENT |
---|
| 460 | data_to_send<="00000001"; |
---|
| 461 | end if; |
---|
| 462 | rd_ok<='0'; |
---|
| 463 | wr_ok<='1'; |
---|
| 464 | dma_wr<='1'; |
---|
| 465 | dma_rd<='0'; |
---|
| 466 | elsif n=6 then |
---|
| 467 | n_i<=0; |
---|
| 468 | Next_ex1_state <= fifo_select; |
---|
| 469 | rd_ok<='0'; |
---|
| 470 | wr_ok<='0'; |
---|
| 471 | dma_wr<='0'; |
---|
| 472 | dma_rd<='0'; |
---|
| 473 | end if; |
---|
| 474 | |
---|
| 475 | |
---|
| 476 | when ex1_get1 => wr_ok<='0'; |
---|
| 477 | if switch_port_in_full = '0' and n = 0 then -- execution du mpi get |
---|
| 478 | --écrire l'entête de la fonction |
---|
| 479 | n_i<= n + 1; |
---|
| 480 | Wr_ok<='1'; |
---|
| 481 | Next_ex1_state <= ex1_get1; |
---|
| 482 | elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get |
---|
| 483 | data_to_send <= "00001000"; -- longueur du paquet sur le réseau ? |
---|
| 484 | n_i<= n + 1; |
---|
| 485 | Wr_ok<='1'; |
---|
| 486 | Next_ex1_state <= ex1_get1; |
---|
| 487 | elsif switch_port_in_full = '0' and n = 2 then |
---|
| 488 | data_to_send <= "0000"&pid; -- Rang source |
---|
| 489 | n_i<= n + 1; |
---|
| 490 | Wr_ok<='1'; |
---|
| 491 | Next_ex1_state <= ex1_get1; |
---|
| 492 | elsif switch_port_in_full = '0' and n = 3 then |
---|
| 493 | data_to_send <= p_len; |
---|
| 494 | n_i<= n + 1; |
---|
| 495 | Wr_ok<='1'; |
---|
| 496 | Next_ex1_state <= ex1_get1; |
---|
| 497 | elsif switch_port_in_full = '0' and n = 4 then |
---|
| 498 | data_to_send <= src_address(15 downto 8); |
---|
| 499 | n_i<= n + 1; |
---|
| 500 | Wr_ok<='1'; |
---|
| 501 | Next_ex1_state <= ex1_get1; |
---|
| 502 | elsif switch_port_in_full = '0' and n = 5 then |
---|
| 503 | data_to_send <= src_address(7 downto 0); |
---|
| 504 | n_i<= n + 1; |
---|
| 505 | Wr_ok<='1'; |
---|
| 506 | Next_ex1_state <= ex1_get1; |
---|
| 507 | elsif switch_port_in_full = '0' and n = 6 then |
---|
| 508 | data_to_send <= dest_address(15 downto 8); |
---|
| 509 | n_i<= n + 1; |
---|
| 510 | Wr_ok<='1'; |
---|
| 511 | Next_ex1_state <= ex1_get1; |
---|
| 512 | elsif switch_port_in_full = '0' and n = 7 then |
---|
| 513 | data_to_send <= dest_address(7 downto 0); |
---|
| 514 | n_i<= n + 1; |
---|
| 515 | Wr_ok<='1'; |
---|
| 516 | Next_ex1_state <= ex1_get1; |
---|
| 517 | elsif switch_port_in_full = '0' and n = 8 then |
---|
| 518 | Next_ex1_state <= ex1_get2; |
---|
| 519 | n_i<=0; |
---|
| 520 | else |
---|
| 521 | Next_ex1_state <= ex1_get1; |
---|
| 522 | end if; |
---|
| 523 | when ex1_get2 => if dma_wr_grant = '1' then |
---|
[72] | 524 | Next_ex1_state <= ex1_get3; |
---|
| 525 | src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); |
---|
| 526 | data_to_send<="00000001"; |
---|
[70] | 527 | else |
---|
[72] | 528 | Next_ex1_state <= ex1_get2; |
---|
| 529 | end if; |
---|
| 530 | dma_wr<='1'; |
---|
| 531 | when ex1_send_ack |ex1_Wsync=> rd_ok<='0'; |
---|
| 532 | if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync |
---|
[70] | 533 | if switch_port_in_full = '0' then |
---|
| 534 | |
---|
| 535 | wr_Ok<='1'; --envoie de la première donnée(code ack) |
---|
| 536 | n_i<= n + 1; |
---|
| 537 | onepop:='0'; |
---|
| 538 | |
---|
| 539 | end if; |
---|
| 540 | elsif n = 1 then |
---|
| 541 | if fifo_empty='0' and onepop='0' then |
---|
| 542 | data_to_send <=p_len ; |
---|
| 543 | |
---|
| 544 | rd_Ok<='1'; --passe la longueur |
---|
| 545 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
---|
| 546 | |
---|
| 547 | else |
---|
| 548 | rd_Ok<='0'; |
---|
| 549 | end if; |
---|
| 550 | |
---|
| 551 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 552 | onepop:=not onepop; |
---|
| 553 | n_i<= n + 1; |
---|
| 554 | wr_ok<='1'; |
---|
| 555 | elsif (switch_port_in_full = '1') then |
---|
| 556 | wr_Ok<='0'; |
---|
| 557 | |
---|
| 558 | end if; |
---|
| 559 | |
---|
| 560 | elsif (n= 2) then |
---|
| 561 | if fifo_empty='0' and onepop='0' then |
---|
| 562 | |
---|
| 563 | data_to_send <=fifo_data_out; |
---|
| 564 | rd_Ok<='1'; |
---|
| 565 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
---|
| 566 | |
---|
| 567 | else |
---|
| 568 | rd_Ok<='0'; |
---|
| 569 | end if; |
---|
| 570 | |
---|
| 571 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 572 | onepop:=not onepop; |
---|
| 573 | n_i<= n + 1; |
---|
| 574 | wr_ok<='1'; |
---|
| 575 | else |
---|
| 576 | wr_Ok<='0'; |
---|
| 577 | |
---|
| 578 | end if; |
---|
| 579 | elsif (n= 3) then |
---|
| 580 | if fifo_empty='0' and onepop='0' then |
---|
| 581 | |
---|
| 582 | data_to_send <=fifo_data_out; |
---|
| 583 | rd_Ok<='1'; |
---|
| 584 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
---|
| 585 | |
---|
| 586 | else |
---|
| 587 | rd_Ok<='0'; |
---|
| 588 | end if; |
---|
| 589 | |
---|
| 590 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 591 | onepop:=not onepop; |
---|
| 592 | n_i<= n + 1; |
---|
| 593 | wr_ok<='1'; |
---|
| 594 | |
---|
| 595 | else |
---|
| 596 | wr_Ok<='0'; |
---|
| 597 | |
---|
| 598 | end if; |
---|
| 599 | elsif n = 4 then |
---|
| 600 | n_i<=0; |
---|
| 601 | Wr_Ok<='0'; |
---|
| 602 | rd_ok<='0';--vider le tampon |
---|
| 603 | Next_ex1_state <= fifo_select; |
---|
| 604 | |
---|
| 605 | end if; |
---|
| 606 | |
---|
[74] | 607 | when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie |
---|
[72] | 608 | if dma_wr_grant = '1' then -- fin du post de mpi_get |
---|
| 609 | |
---|
| 610 | n_i<=n+1; |
---|
[70] | 611 | data_to_send<="00000001"; |
---|
[72] | 612 | wr_ok<='1'; |
---|
| 613 | rd_ok<='0'; |
---|
| 614 | end if; |
---|
| 615 | |
---|
[74] | 616 | elsif n=2 then |
---|
[72] | 617 | n_i<=0; |
---|
| 618 | Next_ex1_state <= ex1_get4; |
---|
| 619 | end if; |
---|
[70] | 620 | src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); |
---|
[72] | 621 | when ex1_get4 => wr_ok<='0'; |
---|
| 622 | rd_ok<='0'; |
---|
| 623 | dma_wr<='1'; |
---|
| 624 | dma_rd<='1'; |
---|
| 625 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
| 626 | |
---|
| 627 | if n=0 then |
---|
| 628 | |
---|
[70] | 629 | if dma_rd_grant='1' then |
---|
| 630 | n_i<=n+1; |
---|
| 631 | |
---|
| 632 | end if; |
---|
| 633 | rd_ok<='1'; |
---|
| 634 | wr_ok<='0'; |
---|
[72] | 635 | |
---|
[70] | 636 | elsif n=1 then |
---|
[72] | 637 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
[70] | 638 | if dma_rd_grant='1' then |
---|
| 639 | n_i<=n+1; |
---|
| 640 | |
---|
| 641 | end if; |
---|
| 642 | rd_ok<='1'; |
---|
| 643 | wr_ok<='0'; |
---|
[72] | 644 | |
---|
[70] | 645 | elsif n=2 then |
---|
| 646 | if dma_rd_grant='1' then |
---|
| 647 | n_i<=n+1; |
---|
[72] | 648 | rd_ok<='1'; |
---|
| 649 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
[74] | 650 | else |
---|
| 651 | n_i<=1; |
---|
[70] | 652 | end if; |
---|
[72] | 653 | |
---|
[70] | 654 | elsif n=3 then |
---|
| 655 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
[74] | 656 | n_i<=n+1; |
---|
| 657 | tempval:=Ram_data_in; |
---|
| 658 | rd_ok<='1'; |
---|
| 659 | wr_ok<='0'; |
---|
| 660 | dma_wr<='1'; |
---|
| 661 | dma_rd<='1'; |
---|
[70] | 662 | else |
---|
[74] | 663 | dma_wr<='0'; |
---|
| 664 | dma_rd<='0'; |
---|
| 665 | n_i<=n-1; |
---|
[70] | 666 | end if; |
---|
[72] | 667 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
[70] | 668 | elsif n=4 then |
---|
| 669 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
---|
| 670 | n_i<=n+1; |
---|
[74] | 671 | rd_ok<='0'; |
---|
| 672 | wr_ok<='1'; |
---|
[72] | 673 | tempval(6):='1'; --SET du bit Windows Busy --car réception Get |
---|
[70] | 674 | tempval(1):='1'; -- SET du bit DReceiving |
---|
| 675 | data_to_send<=tempval; |
---|
| 676 | else |
---|
| 677 | rd_ok<='0'; |
---|
| 678 | wr_ok<='1'; |
---|
[74] | 679 | n_i<=1; |
---|
[70] | 680 | end if; |
---|
| 681 | dma_wr<='1'; |
---|
| 682 | dma_rd<='1'; |
---|
| 683 | elsif n=5 then |
---|
[74] | 684 | n_i<=0; |
---|
[70] | 685 | Next_ex1_state <= fifo_select; |
---|
| 686 | dma_wr<='0'; |
---|
| 687 | dma_rd<='0'; |
---|
| 688 | end if; |
---|
| 689 | |
---|
| 690 | when ex1_spawn => rd_ok<='0'; |
---|
| 691 | if n = 0 then -- execution du mpi spawn |
---|
| 692 | if switch_port_in_full = '0' then |
---|
| 693 | |
---|
| 694 | wr_Ok<='1'; |
---|
| 695 | n_i<= n + 1; |
---|
| 696 | onepop:='0'; |
---|
| 697 | --data_to_send<=len; |
---|
| 698 | end if; |
---|
| 699 | elsif n = 1 then |
---|
| 700 | if fifo_empty='0' and onepop='0' then |
---|
| 701 | data_to_send <=p_len ; |
---|
| 702 | |
---|
| 703 | rd_Ok<='1'; |
---|
| 704 | onepop:='1'; --une donnée lue il faut arrêter de dépiler |
---|
| 705 | |
---|
| 706 | end if; |
---|
| 707 | |
---|
| 708 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 709 | onepop:='0'; |
---|
| 710 | n_i<= n + 1; |
---|
| 711 | wr_ok<='1'; |
---|
| 712 | else |
---|
| 713 | wr_Ok<='0'; |
---|
| 714 | |
---|
| 715 | end if; |
---|
| 716 | |
---|
| 717 | elsif (n= 2) or (n=3) then |
---|
| 718 | if fifo_empty='0' and onepop='0' then |
---|
| 719 | |
---|
| 720 | data_to_send <=fifo_data_out; |
---|
| 721 | rd_Ok<='1'; |
---|
| 722 | onepop:='1'; --une donnée lue il faut arrêter de dépiler |
---|
| 723 | |
---|
| 724 | end if; |
---|
| 725 | |
---|
| 726 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 727 | onepop:='0'; |
---|
| 728 | n_i<= n + 1; |
---|
| 729 | wr_ok<='1'; |
---|
| 730 | else |
---|
| 731 | wr_Ok<='0'; |
---|
| 732 | |
---|
| 733 | end if; |
---|
| 734 | elsif n=4 then |
---|
| 735 | n_i<=0; |
---|
| 736 | Wr_Ok<='0'; |
---|
| 737 | rd_ok<='0'; |
---|
| 738 | Next_ex1_state <= fifo_select; |
---|
| 739 | end if; |
---|
| 740 | -- execution du barrier |
---|
| 741 | when ex1_barrier1 => if switch_port_in_full = '0' then |
---|
| 742 | Next_ex1_state <= ex1_barrier2; |
---|
| 743 | else |
---|
| 744 | Next_ex1_state <= ex1_barrier1; |
---|
| 745 | end if; |
---|
| 746 | when ex1_barrier2 => if switch_port_in_full = '0' then |
---|
| 747 | Next_ex1_state <= ex1_barrier3; |
---|
| 748 | else |
---|
| 749 | Next_ex1_state <= ex1_barrier2; |
---|
| 750 | end if; |
---|
| 751 | when ex1_barrier3 => if switch_port_in_full = '0' then |
---|
| 752 | Next_ex1_state <= ex1_barrier4; |
---|
| 753 | else |
---|
| 754 | Next_ex1_state <= ex1_barrier3; |
---|
| 755 | end if; |
---|
| 756 | when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then |
---|
| 757 | pid_counter <= pid_counter + 1; |
---|
| 758 | Next_ex1_state <= ex1_barrier1; |
---|
| 759 | else |
---|
| 760 | Next_ex1_state <= fifo_select; |
---|
| 761 | end if; |
---|
| 762 | when ex1_init1 => rd_ok<='0'; |
---|
| 763 | if n=0 then |
---|
| 764 | n_i<=n+1; |
---|
| 765 | Len_i<=len-2; --deux données a été dépilée |
---|
| 766 | elsif n=1 then --vider le fifo instruction |
---|
| 767 | if len>0 then |
---|
| 768 | if fifo_empty='0' then |
---|
| 769 | rd_ok<='1'; |
---|
| 770 | Len_i<=len-1; |
---|
| 771 | |
---|
| 772 | else |
---|
| 773 | rd_ok<='0'; |
---|
| 774 | Len_i<=Len; |
---|
| 775 | end if; |
---|
| 776 | else |
---|
| 777 | n_i<=n+1; |
---|
| 778 | end if; |
---|
| 779 | elsif n=2 then -- |
---|
| 780 | n_i<=0; |
---|
| 781 | rd_ok<='0'; |
---|
| 782 | Next_ex1_state<=ex1_init_run; |
---|
| 783 | |
---|
| 784 | end if; |
---|
| 785 | |
---|
| 786 | when ex1_init_run=> if n=0 then |
---|
| 787 | if snd_start='1' then --le module ex4 veut envoyer des données |
---|
[74] | 788 | |
---|
[70] | 789 | n_i<=n+1; |
---|
| 790 | |
---|
| 791 | for i in 0 to 3 loop |
---|
| 792 | mem(i)<=snd_data(i); |
---|
| 793 | end loop; |
---|
[74] | 794 | if snd_data(0)(7 downto 4)=MPI_INIT or |
---|
| 795 | snd_data(0)(7 downto 4)=MPI_SPAWN or |
---|
| 796 | snd_data(0)(7 downto 4)=MPI_ACK then |
---|
| 797 | |
---|
| 798 | else |
---|
| 799 | report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !"; |
---|
[70] | 800 | end if; |
---|
| 801 | P_len_i<=x"04"; |
---|
| 802 | fifo_copy<='0'; |
---|
| 803 | snd_ack1<='0'; |
---|
| 804 | |
---|
| 805 | end if; |
---|
| 806 | if AppInitAck='1' then |
---|
| 807 | Next_ex1_state<=ex1_init2; |
---|
| 808 | end if; |
---|
| 809 | elsif n=1 then |
---|
| 810 | fifo_sel<='0';--pas de rotation du fifo instruction |
---|
| 811 | snd_start1<='1'; |
---|
| 812 | P_len_i<=x"04"; |
---|
| 813 | fifo_copy<='0'; |
---|
| 814 | snd_ack1<='0'; |
---|
| 815 | |
---|
| 816 | n_i<=n+1; |
---|
| 817 | elsif n=2 then |
---|
| 818 | if snd_comp='1' then |
---|
| 819 | snd_ack1<='1'; |
---|
| 820 | |
---|
| 821 | snd_start1<='0'; |
---|
| 822 | n_i<=n+1; |
---|
| 823 | end if; |
---|
| 824 | elsif n=3 then |
---|
| 825 | snd_start1<='0'; |
---|
| 826 | snd_ack1<='1'; |
---|
| 827 | fifo_sel<='0'; |
---|
| 828 | if snd_start='0' then --attente l'annulation de l'envoie |
---|
| 829 | n_i<=0; |
---|
| 830 | snd_ack1<='0'; |
---|
| 831 | if run_init='1' then |
---|
| 832 | Next_EX1_state<=fifo_select; |
---|
[74] | 833 | --run_init<='0'; |
---|
[70] | 834 | end if; |
---|
| 835 | end if; |
---|
| 836 | end if; |
---|
| 837 | |
---|
| 838 | |
---|
[74] | 839 | when ex1_init2 => -- écriture dans le registre status reg. |
---|
| 840 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); |
---|
[70] | 841 | if n=0 then --envoie du message Spawn Ack sur le réseau |
---|
| 842 | if instruction(6)='1' then --Spawned=1 ? |
---|
[74] | 843 | n_i<=1; --envoie du message Spawn à main lib |
---|
| 844 | Data_to_send<="01010000"; --init+spawn |
---|
[70] | 845 | else |
---|
| 846 | n_i<=4; --écrire le résultat de la fn |
---|
[74] | 847 | Data_to_send<="00010000"; --init seul |
---|
[70] | 848 | end if; |
---|
| 849 | |
---|
| 850 | elsif n=1 then |
---|
| 851 | n_i<=n+1; |
---|
| 852 | mem(0)<=MPI_INIT & x"0"; --répondre au premier |
---|
| 853 | mem(1)<=x"04"; |
---|
| 854 | mem(2)<=x"00"; |
---|
| 855 | mem(3)<=INIT_SPAWN & pid;-- indiquer qui répond au |
---|
| 856 | elsif n=2 then |
---|
| 857 | snd_start1<='1'; |
---|
| 858 | n_i<=n+1; |
---|
[74] | 859 | fifo_copy<='0'; |
---|
[70] | 860 | elsif n=3 then |
---|
| 861 | if snd_comp='1' then |
---|
| 862 | snd_ack1<='1'; |
---|
| 863 | snd_start1<='0'; |
---|
| 864 | n_i<=n+1; |
---|
| 865 | end if; |
---|
[74] | 866 | elsif n=4 then --écriture du registre status |
---|
| 867 | dma_wr<='1'; |
---|
[70] | 868 | wr_ok<='1'; |
---|
| 869 | if dma_wr_grant = '1' then -- fin du mpi_init |
---|
| 870 | n_i<=n+1; |
---|
| 871 | end if; |
---|
[74] | 872 | elsif n=5 then |
---|
| 873 | wr_ok<='1'; |
---|
| 874 | if dma_wr_grant = '1' then -- fin du mpi_init |
---|
| 875 | n_i<=n+1; |
---|
| 876 | end if; |
---|
| 877 | elsif n=6 then |
---|
[70] | 878 | Next_ex1_state <= ex1_init3; |
---|
| 879 | n_i<=0; |
---|
| 880 | wr_ok<='0'; |
---|
| 881 | end if; |
---|
| 882 | |
---|
[74] | 883 | |
---|
[70] | 884 | when ex1_init3 =>--if AppInitAck='1' then |
---|
| 885 | Next_ex1_state <= fifo_select; |
---|
| 886 | --end if; |
---|
| 887 | when ex1_ready => Next_ex1_state <= fifo_select; |
---|
| 888 | when others => Next_ex1_state <= fifo_select; |
---|
| 889 | end case; |
---|
| 890 | |
---|
| 891 | end process; |
---|
| 892 | |
---|
| 893 | -- sortie de la machine à etat |
---|
| 894 | ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, |
---|
[74] | 895 | pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok, |
---|
| 896 | fifo_rd) |
---|
[70] | 897 | variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); |
---|
| 898 | begin |
---|
| 899 | -- code fonctionnel |
---|
[74] | 900 | case ex1_state is |
---|
[70] | 901 | when fifo_select => priority_rotation <='1'; -- on peut changer la priorité |
---|
| 902 | fifo_rd_en <= '0'; |
---|
[72] | 903 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 904 | switch_port_in_wr_en <= '0'; |
---|
| 905 | dma_rd_request <= '0'; |
---|
| 906 | dma_wr_request <= '0'; |
---|
| 907 | Ram_rd<='0'; |
---|
| 908 | Ram_wr<='0'; |
---|
| 909 | Ram_data_out<=(others=>'0'); |
---|
| 910 | AppInitReq<='0'; |
---|
| 911 | Result <=(others=>'0'); |
---|
| 912 | Ready<='1'; |
---|
| 913 | when read_status1 => priority_rotation <='0'; |
---|
| 914 | fifo_rd_en <= '0'; |
---|
[72] | 915 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 916 | switch_port_in_wr_en <= '0'; |
---|
| 917 | dma_rd_request <= '1'; |
---|
| 918 | dma_wr_request <= '0'; |
---|
| 919 | Ram_rd<='0'; |
---|
| 920 | Ram_wr<='0'; |
---|
| 921 | Ram_data_out<=(others=>'0'); |
---|
| 922 | AppInitReq<='0'; |
---|
| 923 | Result <=(others=>'0'); |
---|
| 924 | Ready<='0'; |
---|
| 925 | when read_status2 => priority_rotation <='0'; |
---|
| 926 | fifo_rd_en <= '0'; |
---|
[72] | 927 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 928 | switch_port_in_wr_en <= '0'; |
---|
| 929 | dma_rd_request <= '1'; |
---|
| 930 | dma_wr_request <= '0'; |
---|
| 931 | Ram_rd<='1'; |
---|
| 932 | Ram_wr<='0'; |
---|
| 933 | Ram_data_out<=(others=>'0'); |
---|
| 934 | AppInitReq<='0'; |
---|
| 935 | status_reg:=Ram_data_in; |
---|
| 936 | Result <=(others=>'0'); |
---|
| 937 | Ready<='0'; |
---|
| 938 | when fetch_packet_type => priority_rotation <='0'; |
---|
| 939 | fifo_rd_en <= rd_ok; |
---|
[72] | 940 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 941 | AppInitReq<='0'; |
---|
| 942 | switch_port_in_wr_en <= '0'; |
---|
| 943 | Ram_rd<='0'; |
---|
| 944 | Ram_wr<='0'; |
---|
| 945 | dma_rd_request <= '0'; |
---|
| 946 | dma_wr_request <= '0'; |
---|
| 947 | Ram_data_out<=(others=>'0'); |
---|
| 948 | Result <=(others=>'0'); |
---|
| 949 | Ready<='0'; |
---|
| 950 | |
---|
| 951 | when decode_packet_type => priority_rotation <='0'; |
---|
| 952 | fifo_rd_en <= rd_ok; |
---|
[74] | 953 | switch_port_in_data <= Data_To_Send; |
---|
[70] | 954 | switch_port_in_wr_en <= '0'; |
---|
| 955 | AppInitReq<='0'; |
---|
| 956 | Ram_rd<='0'; |
---|
| 957 | Ram_wr<='0'; |
---|
| 958 | dma_rd_request <= '0'; |
---|
| 959 | dma_wr_request <= '0'; |
---|
| 960 | Ram_data_out<=(others=>'0'); |
---|
| 961 | Result <=(others=>'0'); |
---|
| 962 | Ready<='0'; |
---|
| 963 | when fetch_addresses => priority_rotation <='0'; |
---|
| 964 | fifo_rd_en <= rd_ok; |
---|
[72] | 965 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 966 | switch_port_in_wr_en <= '0'; |
---|
| 967 | AppInitReq<='0'; |
---|
| 968 | Ram_rd<='0'; |
---|
| 969 | Ram_wr<='0'; |
---|
| 970 | dma_rd_request <= '0'; |
---|
| 971 | dma_wr_request <= '0'; |
---|
| 972 | Ram_data_out<=(others=>'0'); |
---|
| 973 | Result <=(others=>'0'); |
---|
| 974 | Ready<='0'; |
---|
| 975 | when decode_packet_type2 =>priority_rotation <='0'; |
---|
| 976 | fifo_rd_en <= '0'; |
---|
| 977 | switch_port_in_data <= data_to_send; |
---|
| 978 | switch_port_in_wr_en <= '0'; |
---|
| 979 | AppInitReq<='0'; |
---|
| 980 | Ram_rd<='0'; |
---|
| 981 | Ram_wr<='0'; |
---|
| 982 | dma_rd_request <= '0'; |
---|
| 983 | dma_wr_request <= '0'; |
---|
| 984 | Ram_data_out<=(others=>'0'); |
---|
| 985 | Result <=(others=>'0'); |
---|
| 986 | Ready<='0'; -- fin du module |
---|
| 987 | |
---|
| 988 | when ex1_barrier1 => priority_rotation <='0'; |
---|
| 989 | fifo_rd_en <= '0'; |
---|
| 990 | switch_port_in_data <= packet_type & pid_counter; |
---|
| 991 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
| 992 | AppInitReq<='0'; |
---|
| 993 | Ram_rd<='0'; |
---|
| 994 | Ram_wr<='0'; |
---|
| 995 | dma_rd_request <= '0'; |
---|
| 996 | dma_wr_request <= '0'; |
---|
| 997 | Ram_data_out<=(others=>'0'); |
---|
| 998 | Result <=(others=>'0'); |
---|
| 999 | Ready<='0'; -- fin du module |
---|
| 1000 | |
---|
| 1001 | when ex1_barrier2 => priority_rotation <='0'; |
---|
| 1002 | fifo_rd_en <= '0'; |
---|
| 1003 | switch_port_in_data <= p_len; |
---|
| 1004 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
| 1005 | AppInitReq<='0'; |
---|
| 1006 | Ram_rd<='0'; |
---|
| 1007 | Ram_wr<='0'; |
---|
| 1008 | dma_rd_request <= '0'; |
---|
| 1009 | dma_wr_request <= '0'; |
---|
| 1010 | Ram_data_out<=(others=>'0'); |
---|
| 1011 | Result <=(others=>'0'); |
---|
| 1012 | Ready<='0'; -- fin du module |
---|
| 1013 | |
---|
| 1014 | when ex1_barrier3 => priority_rotation <='0'; |
---|
| 1015 | fifo_rd_en <= '0'; |
---|
| 1016 | switch_port_in_data <= "0000" & pid; |
---|
| 1017 | switch_port_in_wr_en <= not(switch_port_in_full); |
---|
| 1018 | AppInitReq<='0'; |
---|
| 1019 | Ram_rd<='0'; |
---|
| 1020 | Ram_wr<='0'; |
---|
| 1021 | dma_rd_request <= '0'; |
---|
| 1022 | dma_wr_request <= '0'; |
---|
| 1023 | Ram_data_out<=(others=>'0'); |
---|
| 1024 | Result <=(others=>'0'); |
---|
| 1025 | Ready<='0'; -- fin du module |
---|
| 1026 | |
---|
| 1027 | when ex1_barrier4 => priority_rotation <='0'; |
---|
| 1028 | fifo_rd_en <= '0'; |
---|
| 1029 | switch_port_in_data <= "0000" & pid; |
---|
| 1030 | switch_port_in_wr_en <= '0'; |
---|
| 1031 | AppInitReq<='0'; |
---|
| 1032 | dma_rd_request <= '0'; |
---|
| 1033 | Ram_rd<='0'; |
---|
| 1034 | Ram_wr<='0'; |
---|
| 1035 | dma_wr_request <= '0'; |
---|
| 1036 | Ram_data_out<=(others=>'0'); |
---|
| 1037 | Result <=(others=>'0'); |
---|
| 1038 | Ready<='0'; -- fin du module |
---|
| 1039 | |
---|
| 1040 | when ex1_get1 => priority_rotation <='0'; |
---|
| 1041 | fifo_rd_en <= '0'; |
---|
| 1042 | switch_port_in_data <= data_to_send; |
---|
| 1043 | switch_port_in_wr_en <= Wr_ok; |
---|
| 1044 | AppInitReq<='0'; |
---|
| 1045 | Ram_rd<='0'; |
---|
| 1046 | Ram_wr<='0'; |
---|
| 1047 | dma_rd_request <= '0'; |
---|
| 1048 | dma_wr_request <= '0'; |
---|
| 1049 | Ram_data_out<=(others=>'0'); |
---|
| 1050 | Result <=(others=>'0'); |
---|
| 1051 | Ready<='0'; -- fin du module |
---|
| 1052 | when ex1_get2 => priority_rotation <='0'; |
---|
| 1053 | fifo_rd_en <= '0'; |
---|
| 1054 | switch_port_in_data <= data_to_send; |
---|
| 1055 | switch_port_in_wr_en <='0'; |
---|
| 1056 | AppInitReq<='0'; |
---|
| 1057 | Ram_rd<='0'; |
---|
| 1058 | Ram_wr<='0'; |
---|
| 1059 | dma_rd_request <= '0'; |
---|
[72] | 1060 | dma_wr_request <= dma_Wr; |
---|
[70] | 1061 | Ram_rd<='0'; |
---|
| 1062 | Ram_wr<='0'; |
---|
| 1063 | Ram_data_out<=(others=>'0'); |
---|
| 1064 | Result <=(others=>'0'); |
---|
| 1065 | Ready<='0'; -- fin du module |
---|
| 1066 | |
---|
| 1067 | when ex1_get3 => priority_rotation <='0'; |
---|
| 1068 | fifo_rd_en <= '0'; |
---|
[72] | 1069 | switch_port_in_data <= (others=>'0');---??? |
---|
[70] | 1070 | switch_port_in_wr_en <= '0'; |
---|
| 1071 | AppInitReq<='0'; |
---|
| 1072 | dma_rd_request <= '0'; |
---|
| 1073 | dma_wr_request <= '1'; |
---|
| 1074 | Ram_rd<='0'; |
---|
[72] | 1075 | Ram_wr<=wr_ok; |
---|
[70] | 1076 | Ram_data_out<=data_to_send; -- le résultat de l'exécution |
---|
| 1077 | Ready<='0'; -- fin du module |
---|
| 1078 | Result <=(2=>'1',others=>'0');--Get completed |
---|
| 1079 | when ex1_get4 => priority_rotation <='0'; |
---|
| 1080 | fifo_rd_en <= '0'; |
---|
| 1081 | switch_port_in_data <= ram_Data_in; |
---|
| 1082 | switch_port_in_wr_en <= '0'; |
---|
| 1083 | AppInitReq<='0'; |
---|
| 1084 | dma_rd_request <= dma_rd; |
---|
| 1085 | dma_wr_request <= dma_wr; |
---|
| 1086 | Ram_rd<=rd_ok; |
---|
| 1087 | Ram_wr<=wr_ok; |
---|
| 1088 | Ram_data_out<=data_to_send; --"00000001"; |
---|
| 1089 | Result <=(2=>'1',others=>'0'); --get completed |
---|
| 1090 | Ready<='0'; -- fin du module |
---|
| 1091 | when ex1_put1 => priority_rotation <='0'; |
---|
| 1092 | fifo_rd_en <= '0'; |
---|
| 1093 | switch_port_in_data <= data_to_send; |
---|
| 1094 | switch_port_in_wr_en <= '0'; |
---|
| 1095 | AppInitReq<='0'; |
---|
| 1096 | dma_rd_request <= '1'; |
---|
| 1097 | dma_wr_request <= '0'; |
---|
| 1098 | Ram_rd<='0'; |
---|
| 1099 | Ram_wr<='0'; |
---|
| 1100 | Ram_data_out<=(others=>'0'); |
---|
| 1101 | Result <=(others=>'0'); |
---|
| 1102 | Ready<='0'; -- fin du module |
---|
| 1103 | |
---|
| 1104 | when ex1_put2 => priority_rotation <='0'; |
---|
| 1105 | fifo_rd_en <= '0'; |
---|
| 1106 | switch_port_in_data <= data_to_send; |
---|
| 1107 | switch_port_in_wr_en <= wr_ok; |
---|
| 1108 | AppInitReq<='0'; |
---|
| 1109 | Ram_rd<='1'; |
---|
| 1110 | Ram_wr<='0'; |
---|
| 1111 | dma_rd_request <= '1'; |
---|
| 1112 | dma_wr_request <= '0'; |
---|
| 1113 | Ram_data_out<=(others=>'0'); |
---|
| 1114 | Result <=(others=>'0'); |
---|
| 1115 | Ready<='0'; -- fin du module |
---|
| 1116 | |
---|
| 1117 | when ex1_put3 => priority_rotation <='0'; |
---|
| 1118 | fifo_rd_en <= '0'; |
---|
| 1119 | switch_port_in_data <= ram_data_in; |
---|
| 1120 | switch_port_in_wr_en <= wr_ok; |
---|
| 1121 | AppInitReq<='0'; |
---|
| 1122 | dma_rd_request <= '1'; |
---|
| 1123 | dma_wr_request <= '0'; |
---|
| 1124 | Ram_rd<='1'; |
---|
| 1125 | Ram_wr<='0'; |
---|
| 1126 | Ram_data_out<=(others=>'0'); |
---|
| 1127 | Result <=(others=>'0'); |
---|
| 1128 | Ready<='0'; -- fin du module |
---|
| 1129 | |
---|
| 1130 | when ex1_put4 => priority_rotation <='0'; |
---|
| 1131 | fifo_rd_en <= '0'; |
---|
| 1132 | switch_port_in_data <= ram_data_in;---??? |
---|
| 1133 | switch_port_in_wr_en <= '0'; |
---|
| 1134 | AppInitReq<='0'; |
---|
| 1135 | dma_rd_request <= rd_ok; |
---|
| 1136 | dma_wr_request <= wr_ok; |
---|
| 1137 | Ram_rd<=rd_ok; |
---|
| 1138 | Ram_wr<=wr_ok; |
---|
| 1139 | Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution |
---|
| 1140 | --result(1)<='1'; |
---|
| 1141 | Result <=(1=>'1',others=>'0');--put completed |
---|
| 1142 | Ready<='0'; -- fin du module |
---|
| 1143 | when ex1_put5 => priority_rotation <='0'; |
---|
| 1144 | fifo_rd_en <= '0'; |
---|
| 1145 | switch_port_in_data <= ram_Data_in; |
---|
| 1146 | switch_port_in_wr_en <= '0'; |
---|
| 1147 | AppInitReq<='0'; |
---|
| 1148 | dma_rd_request <= dma_rd; |
---|
| 1149 | dma_wr_request <= dma_wr; |
---|
| 1150 | Ram_rd<=rd_ok; |
---|
| 1151 | Ram_wr<=wr_ok; |
---|
| 1152 | Ram_data_out<=data_to_send; --"00000001"; |
---|
| 1153 | Result <=(1=>'1',others=>'0'); --put completed |
---|
| 1154 | Ready<='0'; -- fin du module |
---|
| 1155 | when ex1_init1 => priority_rotation <='0'; |
---|
| 1156 | if fifo_empty='0' then |
---|
| 1157 | fifo_rd_en <= rd_ok; |
---|
| 1158 | else |
---|
| 1159 | fifo_rd_en<='0'; |
---|
| 1160 | end if; |
---|
| 1161 | switch_port_in_data <= data_to_send; |
---|
| 1162 | switch_port_in_wr_en <= wr_ok; |
---|
| 1163 | dma_rd_request <= '0'; |
---|
| 1164 | dma_wr_request <= '0'; |
---|
| 1165 | Ram_rd<='0'; |
---|
| 1166 | Ram_wr<='0'; |
---|
| 1167 | Ram_data_out<=(others=>'0'); |
---|
| 1168 | AppInitReq<='1'; |
---|
| 1169 | Result <=(others=>'0'); |
---|
| 1170 | when ex1_init_run => priority_rotation <='0'; |
---|
| 1171 | |
---|
| 1172 | fifo_rd_en <= fifo_rd; |
---|
| 1173 | |
---|
| 1174 | switch_port_in_data <= noc_fifo_in; |
---|
| 1175 | switch_port_in_wr_en <= fifo_wr; |
---|
| 1176 | dma_rd_request <= '0'; |
---|
| 1177 | dma_wr_request <= '0'; |
---|
| 1178 | Ram_rd<='0'; |
---|
| 1179 | Ram_wr<='0'; |
---|
| 1180 | Ram_data_out<=(others=>'0'); |
---|
| 1181 | AppInitReq<='1'; |
---|
| 1182 | Result <=(others=>'0'); |
---|
| 1183 | |
---|
| 1184 | |
---|
| 1185 | when ex1_init2=> priority_rotation <='0'; |
---|
| 1186 | fifo_rd_en <= '0'; |
---|
| 1187 | switch_port_in_data <= noc_fifo_in; |
---|
[74] | 1188 | switch_port_in_wr_en <= fifo_wr; |
---|
| 1189 | AppInitReq<='0'; |
---|
[70] | 1190 | dma_rd_request <= '0'; |
---|
| 1191 | dma_wr_request <= '1'; |
---|
| 1192 | Ram_rd<='0'; |
---|
| 1193 | Ram_wr<=wr_ok; |
---|
[74] | 1194 | Ram_data_out<=Data_to_send; -- le résultat de l'exécution |
---|
[70] | 1195 | -- dans le registre status |
---|
| 1196 | Result <=(others=>'0');-- |
---|
| 1197 | when ex1_init3=> priority_rotation <='0'; |
---|
| 1198 | fifo_rd_en <= '0'; |
---|
| 1199 | switch_port_in_data <= ram_Data_in; |
---|
| 1200 | switch_port_in_wr_en <= '0'; |
---|
| 1201 | AppInitReq<='0'; |
---|
| 1202 | dma_rd_request <= '0'; |
---|
| 1203 | dma_wr_request <= '1'; |
---|
| 1204 | Ram_rd<='0'; |
---|
| 1205 | Ram_wr<='1'; |
---|
| 1206 | Ram_data_out<="00010000"; |
---|
| 1207 | Ready<='0'; -- fin du module |
---|
| 1208 | Result<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit |
---|
| 1209 | |
---|
| 1210 | when ex1_spawn => priority_rotation <='0'; |
---|
| 1211 | fifo_rd_en <= rd_ok; |
---|
| 1212 | switch_port_in_data <= Data_to_send; |
---|
| 1213 | switch_port_in_wr_en <= wr_ok; |
---|
| 1214 | AppInitReq<='0'; |
---|
| 1215 | dma_rd_request <= '0'; |
---|
| 1216 | dma_wr_request <= '0'; |
---|
| 1217 | Ram_rd<='0'; |
---|
| 1218 | Ram_wr<='0'; |
---|
| 1219 | Ram_data_out<=(others=>'0'); |
---|
| 1220 | Result <=(others=>'0'); |
---|
[72] | 1221 | when ex1_send_ack|ex1_Wsync => priority_rotation <='0'; |
---|
[70] | 1222 | fifo_rd_en <= rd_ok; |
---|
| 1223 | switch_port_in_data <= Data_to_send; |
---|
| 1224 | switch_port_in_wr_en <= wr_ok; |
---|
| 1225 | AppInitReq<='0'; |
---|
| 1226 | dma_rd_request <= '0'; |
---|
| 1227 | dma_wr_request <= '0'; |
---|
| 1228 | Ram_rd<='0'; |
---|
| 1229 | Ram_wr<='0'; |
---|
| 1230 | Ram_data_out<=(others=>'0'); |
---|
| 1231 | Result <=(others=>'0'); |
---|
| 1232 | when ex1_ready => |
---|
| 1233 | Ready<='1'; -- fin du module |
---|
| 1234 | priority_rotation <='0'; |
---|
| 1235 | fifo_rd_en <= '0'; |
---|
[72] | 1236 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 1237 | switch_port_in_wr_en <= '0'; |
---|
| 1238 | dma_rd_request <= '0'; |
---|
| 1239 | dma_wr_request <= '0'; |
---|
| 1240 | Ram_rd<='0'; |
---|
| 1241 | Ram_wr<='0'; |
---|
| 1242 | Ram_data_out<=(others=>'0'); |
---|
| 1243 | AppInitReq<='0'; |
---|
| 1244 | --Result <=Result; |
---|
| 1245 | |
---|
| 1246 | when others => priority_rotation <='0'; |
---|
| 1247 | fifo_rd_en <= '0'; |
---|
[72] | 1248 | switch_port_in_data <= (others =>'0'); |
---|
[70] | 1249 | switch_port_in_wr_en <= '0'; |
---|
| 1250 | dma_rd_request <= '0'; |
---|
| 1251 | dma_wr_request <= '0'; |
---|
| 1252 | Ram_rd<='0'; |
---|
| 1253 | Ram_wr<='0'; |
---|
| 1254 | Ram_data_out<=(others=>'0'); |
---|
| 1255 | AppInitReq<='0'; |
---|
| 1256 | Result <=(others=>'0'); |
---|
| 1257 | end case; |
---|
| 1258 | |
---|
| 1259 | end process; |
---|
| 1260 | |
---|
| 1261 | end Behavioral; |
---|
| 1262 | |
---|