[70] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer:GAMOM /KIEGAING |
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| 4 | -- |
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| 5 | -- Create Date: 08:12:29 06/16/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: EX1_FSM - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Ce module est chargé de recevoir les instructions du programme MPI et |
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| 12 | -- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC |
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| 13 | -- (GET) |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: 09/07/2012 |
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| 18 | -- Revision 0.03 - File updated |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | library NocLib ; |
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| 27 | use Work.Packet_type.ALL; |
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| 28 | USE ieee.numeric_std.ALL; |
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| 29 | |
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| 30 | |
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| 31 | use NocLib.CoreTypes.all; |
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| 32 | ---- Uncomment the following library declaration if instantiating |
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| 33 | ---- any Xilinx primitives in this code. |
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| 34 | --library UNISIM; |
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| 35 | --use UNISIM.VComponents.all; |
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| 36 | |
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| 37 | entity EX1_FSM is |
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| 38 | -- parametres generiques du module : |
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| 39 | |
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| 40 | |
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| 41 | Port ( |
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| 42 | --instruction_available : in STD_LOGIC; |
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| 43 | clk : in STD_LOGIC; |
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| 44 | reset : in STD_LOGIC; |
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| 45 | instruction : in std_logic_vector(Word-1 downto 0); |
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| 46 | instruction_en : in std_logic:='0'; -- active le module instruction |
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| 47 | pid : in std_logic_vector(3 downto 0) ; -- id du processeur |
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| 48 | nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 |
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| 49 | Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module |
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| 50 | Ready : out std_logic; --indique la fin de l'éxécution d'une instruction |
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| 51 | AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application |
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| 52 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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| 53 | Initialized:in std_logic ; -- état de la Lib |
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| 54 | -- Accès au Fifo d'instructions |
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| 55 | priority_rotation : out STD_LOGIC:='0'; |
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| 56 | fifo_rd_en : out STD_LOGIC:='0'; |
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| 57 | fifo_empty : in STD_LOGIC; |
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| 58 | fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); |
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| 59 | fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service |
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| 60 | |
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| 61 | |
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| 62 | Snd_Data : IN Typ_PortIO(0 to 3); |
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| 63 | Snd_Start : IN std_logic; |
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| 64 | Snd_Ack : OUT std_logic; |
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| 65 | |
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| 66 | -- Accès au réseau sur puce |
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| 67 | switch_port_in_full : in std_logic; |
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| 68 | switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'-'); |
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| 69 | switch_port_in_wr_en : out STD_LOGIC:='0'; |
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| 70 | -- Accès à la mémoire RAM du PE |
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| 71 | ram_data_in : in std_logic_vector(7 downto 0); |
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| 72 | ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); |
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| 73 | ram_rd,ram_wr : out std_logic:='0'; |
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| 74 | ram_address : out std_logic_vector(15 downto 0):=(others=>'-'); |
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| 75 | |
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| 76 | dma_wr_request : OUT std_logic:='0'; |
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| 77 | dma_rd_request : OUT std_logic:='0'; |
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| 78 | dma_wr_grant : in STD_LOGIC; |
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| 79 | dma_rd_grant : in STD_LOGIC); |
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| 80 | end EX1_FSM; |
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| 81 | |
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| 82 | architecture Behavioral of EX1_FSM is |
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| 83 | |
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| 84 | component proto_send is |
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| 85 | generic (sizemem : natural := 64); |
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| 86 | port ( |
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| 87 | clk,reset : in std_logic; |
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| 88 | fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée |
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| 89 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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| 90 | fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie |
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| 91 | fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée |
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| 92 | fifo_in_data_out : in std_logic_vector(Word-1 downto 0); |
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| 93 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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| 94 | packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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| 95 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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| 96 | snd_start : in std_logic; --début de la réception |
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| 97 | snd_ack :in std_logic; -- acquittement de la réception |
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| 98 | snd_comp : out std_logic; -- fin de la réception |
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| 99 | mem :in memory(0 to sizemem-1)); --données à copier vers le fifo |
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| 100 | |
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| 101 | |
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| 102 | end component proto_send; |
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| 103 | -- definition du type etat pour le codage des etats des fsm |
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| 104 | type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, |
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| 105 | decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4, |
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| 106 | ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5, |
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| 107 | ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack); |
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| 108 | -- machine a etat du module |
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| 109 | signal ex1_state,Next_Ex1_state : fsm_states; |
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| 110 | |
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| 111 | -- les variables utilisées dans la fsm |
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| 112 | signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0'; |
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| 113 | signal mem : memory(0 to 3); |
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| 114 | signal data_to_send,noc_fifo_in : std_logic_vector(Word-1 downto 0); |
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| 115 | signal packet_type : std_logic_vector(3 downto 0); |
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| 116 | --signal dpid : std_logic_vector(3 downto 0); |
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| 117 | signal pid_counter : std_logic_vector(3 downto 0); |
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| 118 | signal p_len,p_len_i: std_logic_vector(Word-1 downto 0); |
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| 119 | signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0); |
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| 120 | signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; |
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| 121 | --signal res_address : std_logic_vector(15 downto 0); |
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| 122 | signal dest_address : std_logic_vector(ADRLEN-1 downto 0); |
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| 123 | signal n,n_i : natural range 0 to 15; |
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| 124 | signal len,len_i : natural range 0 to 255; |
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| 125 | signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0'; |
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| 126 | signal fifo_sel:std_logic:='0'; |
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| 127 | signal run_init:std_logic:='0'; |
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| 128 | begin |
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| 129 | -- connection des signaux avec les ports |
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| 130 | ram_address <= src_address; |
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| 131 | sw_send: proto_send generic map (sizemem=>4) |
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| 132 | port map ( |
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| 133 | clk=>clk, |
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| 134 | reset=>reset, |
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| 135 | fifo_in_empty=>fifo_empty, |
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| 136 | fifo_in_full=>'0',--pas utilisé |
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| 137 | fifo_out_empty=>'0', |
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| 138 | packet_len=>p_len, |
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| 139 | copy_mode=>fifo_copy, |
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| 140 | fifo_out_full => switch_port_in_full, |
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| 141 | fifo_in_rd_en=>fifo_rd, |
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| 142 | fifo_in_data_out=>fifo_data_out, |
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| 143 | fifo_out_wr_en =>fifo_wr, |
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| 144 | |
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| 145 | fifo_out_data_in =>noc_fifo_in, |
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| 146 | snd_start =>snd_start_sync, |
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| 147 | snd_ack =>snd_ack1, |
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| 148 | snd_comp=>snd_comp, |
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| 149 | mem =>mem |
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| 150 | ); |
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| 151 | ex1_fsm_sync:process(clk) |
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| 152 | |
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| 153 | begin |
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| 154 | if rising_edge(clk) then |
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| 155 | if reset = '1' then |
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| 156 | ex1_state <= fifo_select; |
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| 157 | n<=0; |
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| 158 | len<=0; |
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| 159 | p_len<=(others=>'0'); |
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| 160 | snd_ack<='0'; |
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| 161 | src_address<=(others=>'0'); |
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| 162 | else |
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| 163 | ex1_state<=next_ex1_state; |
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| 164 | n<=n_i; |
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| 165 | len<=len_i; |
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| 166 | p_len<=p_len_i; |
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| 167 | src_address <= src_address_i; |
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| 168 | snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4 |
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| 169 | snd_start_sync<=snd_start1; |
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| 170 | end if; |
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| 171 | end if; |
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| 172 | end process ex1_fsm_sync; |
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| 173 | -- processus de transistion entre les etats |
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| 174 | fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, |
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| 175 | pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address) |
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| 176 | variable tempval : std_logic_vector(Word-1 downto 0); |
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| 177 | variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé |
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| 178 | begin |
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| 179 | n_i<=n; --valeur par défaut |
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| 180 | Next_ex1_state <=Ex1_state; |
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| 181 | case ex1_state is |
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| 182 | when fifo_select => if instruction_en='1' and fifo_empty ='0' then |
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| 183 | Next_ex1_state <= fetch_packet_type; |
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| 184 | else |
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| 185 | Next_ex1_state <= fifo_select; |
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| 186 | end if; |
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| 187 | rd_ok<='0'; |
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| 188 | wr_ok<='0'; |
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| 189 | if instruction_en='1' and snd_start='1' then |
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| 190 | run_init<='1'; |
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| 191 | Next_ex1_state<=ex1_init_run; |
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| 192 | end if; |
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| 193 | --lecture du registre status de la mib MPI |
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| 194 | when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put |
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| 195 | Next_ex1_state <= read_status2; |
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| 196 | else |
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| 197 | Next_ex1_state <= read_status1; |
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| 198 | end if; |
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| 199 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); |
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| 200 | when read_status2 => |
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| 201 | Next_ex1_state <= fifo_select; |
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| 202 | when fetch_packet_type => rd_ok<='0'; |
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| 203 | if fifo_empty ='1' then |
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| 204 | Next_ex1_state <= fifo_select; |
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| 205 | else |
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| 206 | packet_type <= fifo_data_out(7 downto 4); |
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| 207 | data_to_send <= fifo_data_out; |
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| 208 | Next_ex1_state <= decode_packet_type; |
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| 209 | rd_ok<='1'; |
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| 210 | end if; |
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| 211 | when decode_packet_type => rd_ok<='0'; |
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| 212 | if fifo_empty='0' then |
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| 213 | if packet_type = MPI_PUT then |
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| 214 | p_len_i <= fifo_data_out + 4; |
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| 215 | n_i <= 0;rd_ok<='1'; |
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| 216 | Next_ex1_state <= fetch_addresses; |
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| 217 | elsif packet_type = MPI_GET then |
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| 218 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 219 | p_len_i <= fifo_data_out; |
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| 220 | n_i <= 0; rd_ok<='1'; |
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| 221 | Next_ex1_state <= fetch_addresses; |
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| 222 | elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then |
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| 223 | p_len_i <= "00000011"; -- = 3 |
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| 224 | pid_counter <= "0000"; |
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| 225 | rd_ok<='1'; |
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| 226 | Next_ex1_state <= ex1_barrier1; |
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| 227 | elsif packet_type = MPI_INIT then |
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| 228 | Next_ex1_state<=ex1_init1; |
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| 229 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 230 | p_len_i<=fifo_data_out; |
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| 231 | n_i<=0;rd_ok<='1'; |
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| 232 | elsif packet_type = MPI_ACK then |
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| 233 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 234 | p_len_i<=fifo_data_out; |
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| 235 | n_i <= 0; rd_ok<='0'; |
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| 236 | Next_ex1_state <= ex1_send_Ack; |
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| 237 | elsif packet_type = MPI_SPAWN then |
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| 238 | Next_ex1_state<=ex1_SPAWN; |
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| 239 | len_i <= to_integer(unsigned(fifo_data_out)); |
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| 240 | p_len_i<=fifo_data_out; |
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| 241 | onepop:='1';--il y a une donnée lue |
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| 242 | src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16)); |
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| 243 | rd_ok<='0'; |
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| 244 | else -- packet non reconnu |
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| 245 | --synthesis translate_off |
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| 246 | report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ; |
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| 247 | --synthesis translate_on |
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| 248 | if fifo_empty = '1' then |
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| 249 | Next_ex1_state <= fifo_select; |
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| 250 | |
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| 251 | else |
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| 252 | rd_ok<='1'; |
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| 253 | packet_type <= fifo_data_out(7 downto 4); --lire le prochain paquet |
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| 254 | data_to_send <= fifo_data_out; |
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| 255 | Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure |
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| 256 | end if; |
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| 257 | end if; |
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| 258 | end if; |
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| 259 | when fetch_addresses => n_i<=n;rd_ok<='1'; |
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| 260 | if fifo_empty = '0' and n = 0 then |
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| 261 | src_address_i(15 downto 8) <= fifo_data_out; |
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| 262 | n_i <= n + 1; |
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| 263 | Next_ex1_state <= fetch_addresses; |
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| 264 | elsif fifo_empty = '0' and n = 1 then |
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| 265 | src_address_i(7 downto 0) <= fifo_data_out; |
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| 266 | n_i <= n + 1; |
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| 267 | Next_ex1_state <= fetch_addresses; |
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| 268 | elsif fifo_empty = '0' and n = 2 then |
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| 269 | dest_address(15 downto 8) <= fifo_data_out; |
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| 270 | n_i <= n + 1; |
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| 271 | Next_ex1_state <= fetch_addresses; |
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| 272 | elsif fifo_empty = '0' and n = 3 then |
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| 273 | dest_address(7 downto 0) <= fifo_data_out; |
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| 274 | n_i <= n+1; |
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| 275 | elsif n=4 then |
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| 276 | rd_ok<='0'; |
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| 277 | n_i<=0; |
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| 278 | Next_ex1_state <= decode_packet_type2; |
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| 279 | elsif fifo_empty='1' then |
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| 280 | rd_ok<='0'; |
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| 281 | Next_ex1_state <= fetch_addresses; --attendre les données manquantes |
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| 282 | else |
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| 283 | Next_ex1_state <= fifo_select; |
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| 284 | end if; |
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| 285 | when decode_packet_type2 => if packet_type = MPI_PUT then |
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| 286 | Next_ex1_state <= ex1_put1; |
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| 287 | elsif packet_type = MPI_GET then |
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| 288 | Next_ex1_state <= ex1_get1; |
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| 289 | end if; |
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| 290 | -- execution du mpi put |
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| 291 | when ex1_put1 => if dma_rd_grant = '1' then |
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| 292 | Next_ex1_state <= ex1_put2; |
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| 293 | else |
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| 294 | Next_ex1_state <= ex1_put1; |
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| 295 | end if; |
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| 296 | Wr_ok<='0'; |
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| 297 | when ex1_put2 =>Wr_ok<='0'; |
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| 298 | if switch_port_in_full = '0' and n = 0 then |
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| 299 | --envoie du code MPI_PUT |
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| 300 | n_i<= n + 1; |
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| 301 | wr_ok<='1'; |
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| 302 | Next_ex1_state <= ex1_put2; |
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| 303 | elsif switch_port_in_full = '0' and n = 1 then |
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| 304 | data_to_send <= p_len; |
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| 305 | n_i<= n + 1; |
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| 306 | wr_ok<='1'; |
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| 307 | Next_ex1_state <= ex1_put2; |
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| 308 | elsif switch_port_in_full = '0' and n = 2 then |
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| 309 | data_to_send <= dest_address(15 downto 8); |
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| 310 | n_i<= n + 1; |
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| 311 | wr_ok<='1'; |
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| 312 | Next_ex1_state <= ex1_put2; |
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| 313 | elsif switch_port_in_full = '0' and n = 3 then |
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| 314 | data_to_send <= dest_address(7 downto 0); |
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| 315 | n_i<= n +1; |
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| 316 | wr_ok<='1'; |
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| 317 | Next_ex1_state <= ex1_put2; |
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| 318 | elsif switch_port_in_full = '0' and n = 4 then |
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| 319 | p_len_i <= p_len - 4; |
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| 320 | Next_ex1_state <= ex1_put3; |
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| 321 | Wr_ok<='0'; |
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| 322 | n_i<=0; |
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| 323 | else |
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| 324 | Next_ex1_state <= ex1_put2; |
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| 325 | end if; |
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| 326 | when ex1_put3 => wr_ok<='0'; |
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| 327 | if unsigned(p_len)>0 then |
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| 328 | --if n=0 then |
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| 329 | -- n_i<=1; --cycle d'attente pour la RAM |
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| 330 | -- Wr_ok<='0'; |
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| 331 | -- elsif n=1 then |
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| 332 | if switch_port_in_full = '0' then |
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| 333 | if n=1 then --creer un délai sur ces signaux par rapport à src_adress |
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| 334 | p_len_i <= p_len - 1; |
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| 335 | Wr_Ok<='1'; |
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| 336 | end if; |
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| 337 | n_i<=1; |
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| 338 | src_address_i <= src_address+1; |
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| 339 | Next_ex1_state <= ex1_put3; |
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| 340 | |
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| 341 | |
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| 342 | else |
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| 343 | Wr_Ok<='0'; |
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| 344 | src_address_i <= src_address; |
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| 345 | n_i<=0; |
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| 346 | end if; |
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| 347 | --elsif n=2 then |
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| 348 | -- n_i<=0; --cycle d'attente pour la RAM |
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| 349 | -- Wr_ok<='0'; |
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| 350 | -- src_address_i <= src_address ; --prochaine lecture |
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| 351 | -- |
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| 352 | -- end if; |
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| 353 | else |
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| 354 | Wr_Ok<='0'; |
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| 355 | Next_ex1_state <= ex1_put4; |
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| 356 | end if; |
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| 357 | when ex1_put4 => if dma_rd_grant = '1' then -- fin du mpi_put |
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| 358 | Next_ex1_state <= ex1_put5; |
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| 359 | n_i<=0; |
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| 360 | data_to_send<="00000001"; |
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| 361 | else |
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| 362 | Next_ex1_state <= ex1_put4; |
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| 363 | end if; |
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| 364 | rd_ok<='1'; |
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| 365 | wr_ok<='0'; |
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| 366 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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| 367 | |
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| 368 | when ex1_put5 => if n <6 then |
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| 369 | |
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| 370 | dma_wr<='1'; --demander un accès exclusif au bus |
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| 371 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
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| 372 | else |
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| 373 | dma_wr<='0'; |
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| 374 | dma_rd<='0'; |
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| 375 | end if; |
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| 376 | |
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| 377 | if n=0 then |
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| 378 | if dma_rd_grant='1' then |
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| 379 | n_i<=n+1; |
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| 380 | |
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| 381 | end if; |
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| 382 | rd_ok<='1'; |
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| 383 | wr_ok<='0'; |
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| 384 | dma_wr<='1'; |
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| 385 | dma_rd<='1'; |
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| 386 | elsif n=1 then |
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| 387 | if dma_rd_grant='1' then |
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| 388 | n_i<=n+1; |
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| 389 | dma_wr<='1'; |
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| 390 | end if; |
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| 391 | rd_ok<='1'; |
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| 392 | wr_ok<='0'; |
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| 393 | |
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| 394 | dma_rd<='1'; |
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| 395 | elsif n=2 then |
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| 396 | if dma_rd_grant='1' and dma_wr_grant='1' then |
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| 397 | n_i<=n+1; |
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| 398 | tempval:=Ram_data_in; |
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| 399 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
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| 400 | if fifo_src='0' then -- c'est un put qui est exécuté |
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| 401 | tempval(5):='1'; -- SET du bit DSENT |
---|
| 402 | else -- c'est un Get qui est exécuté |
---|
| 403 | tempval(2):='0'; --annuler le sending après un GET |
---|
| 404 | end if; |
---|
| 405 | data_to_send<=tempval; |
---|
| 406 | rd_ok<='0'; |
---|
| 407 | wr_ok<='1'; |
---|
| 408 | dma_wr<='1'; |
---|
| 409 | dma_rd<='1'; |
---|
| 410 | else |
---|
| 411 | rd_ok<='1'; |
---|
| 412 | wr_ok<='0'; |
---|
| 413 | dma_rd<='0'; --libérer le bus et revenir en arrière |
---|
| 414 | dma_wr<='0'; |
---|
| 415 | n_i<=n-1; |
---|
| 416 | end if; |
---|
| 417 | elsif n=3 then |
---|
| 418 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
---|
| 419 | n_i<=n+1; |
---|
| 420 | |
---|
| 421 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 422 | end if; |
---|
| 423 | rd_ok<='0'; |
---|
| 424 | wr_ok<='1'; |
---|
| 425 | dma_wr<='1'; |
---|
| 426 | dma_rd<='1'; |
---|
| 427 | elsif n=4 then |
---|
| 428 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
---|
| 429 | n_i<=n+1; |
---|
| 430 | |
---|
| 431 | src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16)); |
---|
| 432 | |
---|
| 433 | end if; |
---|
| 434 | rd_ok<='0'; |
---|
| 435 | wr_ok<='1'; |
---|
| 436 | dma_wr<='1'; |
---|
| 437 | dma_rd<='0'; |
---|
| 438 | elsif n=5 then |
---|
| 439 | if dma_wr_grant = '1' then |
---|
| 440 | n_i<=n+1; |
---|
| 441 | |
---|
| 442 | -- SET du bit DSENT |
---|
| 443 | data_to_send<="00000001"; |
---|
| 444 | end if; |
---|
| 445 | rd_ok<='0'; |
---|
| 446 | wr_ok<='1'; |
---|
| 447 | dma_wr<='1'; |
---|
| 448 | dma_rd<='0'; |
---|
| 449 | elsif n=6 then |
---|
| 450 | n_i<=0; |
---|
| 451 | Next_ex1_state <= fifo_select; |
---|
| 452 | rd_ok<='0'; |
---|
| 453 | wr_ok<='0'; |
---|
| 454 | dma_wr<='0'; |
---|
| 455 | dma_rd<='0'; |
---|
| 456 | end if; |
---|
| 457 | |
---|
| 458 | |
---|
| 459 | when ex1_get1 => wr_ok<='0'; |
---|
| 460 | if switch_port_in_full = '0' and n = 0 then -- execution du mpi get |
---|
| 461 | --écrire l'entête de la fonction |
---|
| 462 | n_i<= n + 1; |
---|
| 463 | Wr_ok<='1'; |
---|
| 464 | Next_ex1_state <= ex1_get1; |
---|
| 465 | elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get |
---|
| 466 | data_to_send <= "00001000"; -- longueur du paquet sur le réseau ? |
---|
| 467 | n_i<= n + 1; |
---|
| 468 | Wr_ok<='1'; |
---|
| 469 | Next_ex1_state <= ex1_get1; |
---|
| 470 | elsif switch_port_in_full = '0' and n = 2 then |
---|
| 471 | data_to_send <= "0000"&pid; -- Rang source |
---|
| 472 | n_i<= n + 1; |
---|
| 473 | Wr_ok<='1'; |
---|
| 474 | Next_ex1_state <= ex1_get1; |
---|
| 475 | elsif switch_port_in_full = '0' and n = 3 then |
---|
| 476 | data_to_send <= p_len; |
---|
| 477 | n_i<= n + 1; |
---|
| 478 | Wr_ok<='1'; |
---|
| 479 | Next_ex1_state <= ex1_get1; |
---|
| 480 | elsif switch_port_in_full = '0' and n = 4 then |
---|
| 481 | data_to_send <= src_address(15 downto 8); |
---|
| 482 | n_i<= n + 1; |
---|
| 483 | Wr_ok<='1'; |
---|
| 484 | Next_ex1_state <= ex1_get1; |
---|
| 485 | elsif switch_port_in_full = '0' and n = 5 then |
---|
| 486 | data_to_send <= src_address(7 downto 0); |
---|
| 487 | n_i<= n + 1; |
---|
| 488 | Wr_ok<='1'; |
---|
| 489 | Next_ex1_state <= ex1_get1; |
---|
| 490 | elsif switch_port_in_full = '0' and n = 6 then |
---|
| 491 | data_to_send <= dest_address(15 downto 8); |
---|
| 492 | n_i<= n + 1; |
---|
| 493 | Wr_ok<='1'; |
---|
| 494 | Next_ex1_state <= ex1_get1; |
---|
| 495 | elsif switch_port_in_full = '0' and n = 7 then |
---|
| 496 | data_to_send <= dest_address(7 downto 0); |
---|
| 497 | n_i<= n + 1; |
---|
| 498 | Wr_ok<='1'; |
---|
| 499 | Next_ex1_state <= ex1_get1; |
---|
| 500 | elsif switch_port_in_full = '0' and n = 8 then |
---|
| 501 | Next_ex1_state <= ex1_get2; |
---|
| 502 | n_i<=0; |
---|
| 503 | else |
---|
| 504 | Next_ex1_state <= ex1_get1; |
---|
| 505 | end if; |
---|
| 506 | when ex1_get2 => if dma_wr_grant = '1' then |
---|
| 507 | Next_ex1_state <= ex1_get3; |
---|
| 508 | src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); |
---|
| 509 | data_to_send<="00000001"; |
---|
| 510 | else |
---|
| 511 | Next_ex1_state <= ex1_get2; |
---|
| 512 | wr_ok<='1'; |
---|
| 513 | end if; |
---|
| 514 | when ex1_send_ack => rd_ok<='0'; |
---|
| 515 | if n = 0 then -- execution du mpi ack |
---|
| 516 | if switch_port_in_full = '0' then |
---|
| 517 | |
---|
| 518 | wr_Ok<='1'; --envoie de la première donnée(code ack) |
---|
| 519 | n_i<= n + 1; |
---|
| 520 | onepop:='0'; |
---|
| 521 | |
---|
| 522 | end if; |
---|
| 523 | elsif n = 1 then |
---|
| 524 | if fifo_empty='0' and onepop='0' then |
---|
| 525 | data_to_send <=p_len ; |
---|
| 526 | |
---|
| 527 | rd_Ok<='1'; --passe la longueur |
---|
| 528 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
---|
| 529 | |
---|
| 530 | else |
---|
| 531 | rd_Ok<='0'; |
---|
| 532 | end if; |
---|
| 533 | |
---|
| 534 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 535 | onepop:=not onepop; |
---|
| 536 | n_i<= n + 1; |
---|
| 537 | wr_ok<='1'; |
---|
| 538 | elsif (switch_port_in_full = '1') then |
---|
| 539 | wr_Ok<='0'; |
---|
| 540 | |
---|
| 541 | end if; |
---|
| 542 | |
---|
| 543 | elsif (n= 2) then |
---|
| 544 | if fifo_empty='0' and onepop='0' then |
---|
| 545 | |
---|
| 546 | data_to_send <=fifo_data_out; |
---|
| 547 | rd_Ok<='1'; |
---|
| 548 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
---|
| 549 | |
---|
| 550 | else |
---|
| 551 | rd_Ok<='0'; |
---|
| 552 | end if; |
---|
| 553 | |
---|
| 554 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 555 | onepop:=not onepop; |
---|
| 556 | n_i<= n + 1; |
---|
| 557 | wr_ok<='1'; |
---|
| 558 | else |
---|
| 559 | wr_Ok<='0'; |
---|
| 560 | |
---|
| 561 | end if; |
---|
| 562 | elsif (n= 3) then |
---|
| 563 | if fifo_empty='0' and onepop='0' then |
---|
| 564 | |
---|
| 565 | data_to_send <=fifo_data_out; |
---|
| 566 | rd_Ok<='1'; |
---|
| 567 | onepop:=not onepop; --une donnée lue il faut arrêter de dépiler |
---|
| 568 | |
---|
| 569 | else |
---|
| 570 | rd_Ok<='0'; |
---|
| 571 | end if; |
---|
| 572 | |
---|
| 573 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 574 | onepop:=not onepop; |
---|
| 575 | n_i<= n + 1; |
---|
| 576 | wr_ok<='1'; |
---|
| 577 | |
---|
| 578 | else |
---|
| 579 | wr_Ok<='0'; |
---|
| 580 | |
---|
| 581 | end if; |
---|
| 582 | elsif n = 4 then |
---|
| 583 | n_i<=0; |
---|
| 584 | Wr_Ok<='0'; |
---|
| 585 | rd_ok<='0';--vider le tampon |
---|
| 586 | Next_ex1_state <= fifo_select; |
---|
| 587 | |
---|
| 588 | end if; |
---|
| 589 | |
---|
| 590 | when ex1_get3 => if dma_wr_grant = '1' then -- fin du post de mpi_get |
---|
| 591 | Next_ex1_state <= ex1_get4; |
---|
| 592 | n_i<=0; |
---|
| 593 | data_to_send<="00000001"; |
---|
| 594 | wr_ok<='0'; |
---|
| 595 | rd_ok<='1'; |
---|
| 596 | else |
---|
| 597 | Next_ex1_state <= ex1_get3; |
---|
| 598 | end if; |
---|
| 599 | src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); |
---|
| 600 | when ex1_get4 => if n=0 then |
---|
| 601 | |
---|
| 602 | if dma_rd_grant='1' then |
---|
| 603 | n_i<=n+1; |
---|
| 604 | |
---|
| 605 | end if; |
---|
| 606 | rd_ok<='1'; |
---|
| 607 | wr_ok<='0'; |
---|
| 608 | dma_wr<='1'; |
---|
| 609 | dma_rd<='1'; |
---|
| 610 | elsif n=1 then |
---|
| 611 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 612 | if dma_rd_grant='1' then |
---|
| 613 | n_i<=n+1; |
---|
| 614 | |
---|
| 615 | end if; |
---|
| 616 | rd_ok<='1'; |
---|
| 617 | wr_ok<='0'; |
---|
| 618 | dma_wr<='1'; |
---|
| 619 | dma_rd<='1'; |
---|
| 620 | elsif n=2 then |
---|
| 621 | if dma_rd_grant='1' then |
---|
| 622 | n_i<=n+1; |
---|
| 623 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 624 | end if; |
---|
| 625 | dma_wr<='1'; |
---|
| 626 | dma_rd<='1'; |
---|
| 627 | elsif n=3 then |
---|
| 628 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
| 629 | n_i<=n+1; |
---|
| 630 | tempval:=Ram_data_in; |
---|
| 631 | rd_ok<='0'; |
---|
| 632 | wr_ok<='1'; |
---|
| 633 | dma_wr<='1'; |
---|
| 634 | dma_rd<='1'; |
---|
| 635 | else |
---|
| 636 | dma_wr<='0'; |
---|
| 637 | dma_rd<='0'; |
---|
| 638 | n_i<=n-1; |
---|
| 639 | end if; |
---|
| 640 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 641 | elsif n=4 then |
---|
| 642 | if dma_wr_grant = '1' and dma_rd_grant='1' then |
---|
| 643 | n_i<=n+1; |
---|
| 644 | |
---|
| 645 | --tempval(4):='0'; --RESET du bit DReceived |
---|
| 646 | tempval(1):='1'; -- SET du bit DReceiving |
---|
| 647 | data_to_send<=tempval; |
---|
| 648 | else |
---|
| 649 | rd_ok<='0'; |
---|
| 650 | wr_ok<='1'; |
---|
| 651 | end if; |
---|
| 652 | dma_wr<='1'; |
---|
| 653 | dma_rd<='1'; |
---|
| 654 | elsif n=5 then |
---|
| 655 | n_i<=0; |
---|
| 656 | Next_ex1_state <= fifo_select; |
---|
| 657 | dma_wr<='0'; |
---|
| 658 | dma_rd<='0'; |
---|
| 659 | end if; |
---|
| 660 | |
---|
| 661 | when ex1_spawn => rd_ok<='0'; |
---|
| 662 | if n = 0 then -- execution du mpi spawn |
---|
| 663 | if switch_port_in_full = '0' then |
---|
| 664 | |
---|
| 665 | wr_Ok<='1'; |
---|
| 666 | n_i<= n + 1; |
---|
| 667 | onepop:='0'; |
---|
| 668 | --data_to_send<=len; |
---|
| 669 | end if; |
---|
| 670 | elsif n = 1 then |
---|
| 671 | if fifo_empty='0' and onepop='0' then |
---|
| 672 | data_to_send <=p_len ; |
---|
| 673 | |
---|
| 674 | rd_Ok<='1'; |
---|
| 675 | onepop:='1'; --une donnée lue il faut arrêter de dépiler |
---|
| 676 | |
---|
| 677 | end if; |
---|
| 678 | |
---|
| 679 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 680 | onepop:='0'; |
---|
| 681 | n_i<= n + 1; |
---|
| 682 | wr_ok<='1'; |
---|
| 683 | else |
---|
| 684 | wr_Ok<='0'; |
---|
| 685 | |
---|
| 686 | end if; |
---|
| 687 | |
---|
| 688 | elsif (n= 2) or (n=3) then |
---|
| 689 | if fifo_empty='0' and onepop='0' then |
---|
| 690 | |
---|
| 691 | data_to_send <=fifo_data_out; |
---|
| 692 | rd_Ok<='1'; |
---|
| 693 | onepop:='1'; --une donnée lue il faut arrêter de dépiler |
---|
| 694 | |
---|
| 695 | end if; |
---|
| 696 | |
---|
| 697 | if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; |
---|
| 698 | onepop:='0'; |
---|
| 699 | n_i<= n + 1; |
---|
| 700 | wr_ok<='1'; |
---|
| 701 | else |
---|
| 702 | wr_Ok<='0'; |
---|
| 703 | |
---|
| 704 | end if; |
---|
| 705 | elsif n=4 then |
---|
| 706 | n_i<=0; |
---|
| 707 | Wr_Ok<='0'; |
---|
| 708 | rd_ok<='0'; |
---|
| 709 | Next_ex1_state <= fifo_select; |
---|
| 710 | end if; |
---|
| 711 | -- execution du barrier |
---|
| 712 | when ex1_barrier1 => if switch_port_in_full = '0' then |
---|
| 713 | Next_ex1_state <= ex1_barrier2; |
---|
| 714 | else |
---|
| 715 | Next_ex1_state <= ex1_barrier1; |
---|
| 716 | end if; |
---|
| 717 | when ex1_barrier2 => if switch_port_in_full = '0' then |
---|
| 718 | Next_ex1_state <= ex1_barrier3; |
---|
| 719 | else |
---|
| 720 | Next_ex1_state <= ex1_barrier2; |
---|
| 721 | end if; |
---|
| 722 | when ex1_barrier3 => if switch_port_in_full = '0' then |
---|
| 723 | Next_ex1_state <= ex1_barrier4; |
---|
| 724 | else |
---|
| 725 | Next_ex1_state <= ex1_barrier3; |
---|
| 726 | end if; |
---|
| 727 | when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then |
---|
| 728 | pid_counter <= pid_counter + 1; |
---|
| 729 | Next_ex1_state <= ex1_barrier1; |
---|
| 730 | else |
---|
| 731 | Next_ex1_state <= fifo_select; |
---|
| 732 | end if; |
---|
| 733 | when ex1_init1 => rd_ok<='0'; |
---|
| 734 | if n=0 then |
---|
| 735 | n_i<=n+1; |
---|
| 736 | Len_i<=len-2; --deux données a été dépilée |
---|
| 737 | elsif n=1 then --vider le fifo instruction |
---|
| 738 | if len>0 then |
---|
| 739 | if fifo_empty='0' then |
---|
| 740 | rd_ok<='1'; |
---|
| 741 | Len_i<=len-1; |
---|
| 742 | |
---|
| 743 | else |
---|
| 744 | rd_ok<='0'; |
---|
| 745 | Len_i<=Len; |
---|
| 746 | end if; |
---|
| 747 | else |
---|
| 748 | n_i<=n+1; |
---|
| 749 | end if; |
---|
| 750 | elsif n=2 then -- |
---|
| 751 | n_i<=0; |
---|
| 752 | rd_ok<='0'; |
---|
| 753 | Next_ex1_state<=ex1_init_run; |
---|
| 754 | |
---|
| 755 | end if; |
---|
| 756 | |
---|
| 757 | when ex1_init_run=> if n=0 then |
---|
| 758 | if snd_start='1' then --le module ex4 veut envoyer des données |
---|
| 759 | if snd_data(0)(7 downto 4)=MPI_INIT or snd_data(0)(7 downto 4)=MPI_SPAWN then |
---|
| 760 | n_i<=n+1; |
---|
| 761 | |
---|
| 762 | for i in 0 to 3 loop |
---|
| 763 | mem(i)<=snd_data(i); |
---|
| 764 | end loop; |
---|
| 765 | end if; |
---|
| 766 | P_len_i<=x"04"; |
---|
| 767 | fifo_copy<='0'; |
---|
| 768 | snd_ack1<='0'; |
---|
| 769 | |
---|
| 770 | end if; |
---|
| 771 | if AppInitAck='1' then |
---|
| 772 | Next_ex1_state<=ex1_init2; |
---|
| 773 | end if; |
---|
| 774 | elsif n=1 then |
---|
| 775 | fifo_sel<='0';--pas de rotation du fifo instruction |
---|
| 776 | snd_start1<='1'; |
---|
| 777 | P_len_i<=x"04"; |
---|
| 778 | fifo_copy<='0'; |
---|
| 779 | snd_ack1<='0'; |
---|
| 780 | |
---|
| 781 | n_i<=n+1; |
---|
| 782 | elsif n=2 then |
---|
| 783 | if snd_comp='1' then |
---|
| 784 | snd_ack1<='1'; |
---|
| 785 | |
---|
| 786 | snd_start1<='0'; |
---|
| 787 | n_i<=n+1; |
---|
| 788 | end if; |
---|
| 789 | elsif n=3 then |
---|
| 790 | snd_start1<='0'; |
---|
| 791 | snd_ack1<='1'; |
---|
| 792 | fifo_sel<='0'; |
---|
| 793 | if snd_start='0' then --attente l'annulation de l'envoie |
---|
| 794 | n_i<=0; |
---|
| 795 | snd_ack1<='0'; |
---|
| 796 | if run_init='1' then |
---|
| 797 | Next_EX1_state<=fifo_select; |
---|
| 798 | run_init<='0'; |
---|
| 799 | end if; |
---|
| 800 | end if; |
---|
| 801 | end if; |
---|
| 802 | |
---|
| 803 | |
---|
| 804 | when ex1_init2 => |
---|
| 805 | if n=0 then --envoie du message Spawn Ack sur le réseau |
---|
| 806 | if instruction(6)='1' then --Spawned=1 ? |
---|
| 807 | n_i<=1; |
---|
| 808 | else |
---|
| 809 | n_i<=4; --écrire le résultat de la fn |
---|
| 810 | end if; |
---|
| 811 | |
---|
| 812 | elsif n=1 then |
---|
| 813 | n_i<=n+1; |
---|
| 814 | mem(0)<=MPI_INIT & x"0"; --répondre au premier |
---|
| 815 | mem(1)<=x"04"; |
---|
| 816 | mem(2)<=x"00"; |
---|
| 817 | mem(3)<=INIT_SPAWN & pid;-- indiquer qui répond au |
---|
| 818 | elsif n=2 then |
---|
| 819 | snd_start1<='1'; |
---|
| 820 | n_i<=n+1; |
---|
| 821 | elsif n=3 then |
---|
| 822 | if snd_comp='1' then |
---|
| 823 | snd_ack1<='1'; |
---|
| 824 | snd_start1<='0'; |
---|
| 825 | n_i<=n+1; |
---|
| 826 | end if; |
---|
| 827 | elsif n=4 then |
---|
| 828 | wr_ok<='1'; |
---|
| 829 | if dma_wr_grant = '1' then -- fin du mpi_init |
---|
| 830 | n_i<=n+1; |
---|
| 831 | end if; |
---|
| 832 | elsif n=5 then |
---|
| 833 | Next_ex1_state <= ex1_init3; |
---|
| 834 | n_i<=0; |
---|
| 835 | wr_ok<='0'; |
---|
| 836 | end if; |
---|
| 837 | |
---|
| 838 | -- écriture dans le registre status reg. |
---|
| 839 | src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); |
---|
| 840 | when ex1_init3 =>--if AppInitAck='1' then |
---|
| 841 | Next_ex1_state <= fifo_select; |
---|
| 842 | --end if; |
---|
| 843 | when ex1_ready => Next_ex1_state <= fifo_select; |
---|
| 844 | when others => Next_ex1_state <= fifo_select; |
---|
| 845 | end case; |
---|
| 846 | |
---|
| 847 | end process; |
---|
| 848 | |
---|
| 849 | -- sortie de la machine à etat |
---|
| 850 | ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, |
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| 851 | pid_counter, ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok) |
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| 852 | variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); |
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| 853 | begin |
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| 854 | -- code fonctionnel |
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| 855 | case Next_ex1_state is |
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| 856 | when fifo_select => priority_rotation <='1'; -- on peut changer la priorité |
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| 857 | fifo_rd_en <= '0'; |
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| 858 | switch_port_in_data <= (others =>'-'); |
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| 859 | switch_port_in_wr_en <= '0'; |
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| 860 | dma_rd_request <= '0'; |
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| 861 | dma_wr_request <= '0'; |
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| 862 | Ram_rd<='0'; |
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| 863 | Ram_wr<='0'; |
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| 864 | Ram_data_out<=(others=>'0'); |
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| 865 | AppInitReq<='0'; |
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| 866 | Result <=(others=>'0'); |
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| 867 | Ready<='1'; |
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| 868 | when read_status1 => priority_rotation <='0'; |
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| 869 | fifo_rd_en <= '0'; |
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| 870 | switch_port_in_data <= (others =>'-'); |
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| 871 | switch_port_in_wr_en <= '0'; |
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| 872 | dma_rd_request <= '1'; |
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| 873 | dma_wr_request <= '0'; |
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| 874 | Ram_rd<='0'; |
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| 875 | Ram_wr<='0'; |
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| 876 | Ram_data_out<=(others=>'0'); |
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| 877 | AppInitReq<='0'; |
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| 878 | Result <=(others=>'0'); |
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| 879 | Ready<='0'; |
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| 880 | when read_status2 => priority_rotation <='0'; |
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| 881 | fifo_rd_en <= '0'; |
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| 882 | switch_port_in_data <= (others =>'-'); |
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| 883 | switch_port_in_wr_en <= '0'; |
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| 884 | dma_rd_request <= '1'; |
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| 885 | dma_wr_request <= '0'; |
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| 886 | Ram_rd<='1'; |
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| 887 | Ram_wr<='0'; |
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| 888 | Ram_data_out<=(others=>'0'); |
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| 889 | AppInitReq<='0'; |
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| 890 | status_reg:=Ram_data_in; |
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| 891 | Result <=(others=>'0'); |
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| 892 | Ready<='0'; |
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| 893 | when fetch_packet_type => priority_rotation <='0'; |
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| 894 | fifo_rd_en <= rd_ok; |
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| 895 | switch_port_in_data <= (others =>'-'); |
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| 896 | AppInitReq<='0'; |
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| 897 | switch_port_in_wr_en <= '0'; |
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| 898 | Ram_rd<='0'; |
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| 899 | Ram_wr<='0'; |
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| 900 | dma_rd_request <= '0'; |
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| 901 | dma_wr_request <= '0'; |
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| 902 | Ram_data_out<=(others=>'0'); |
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| 903 | Result <=(others=>'0'); |
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| 904 | Ready<='0'; |
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| 905 | |
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| 906 | when decode_packet_type => priority_rotation <='0'; |
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| 907 | fifo_rd_en <= rd_ok; |
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| 908 | switch_port_in_data <= (others =>'-'); |
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| 909 | switch_port_in_wr_en <= '0'; |
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| 910 | AppInitReq<='0'; |
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| 911 | Ram_rd<='0'; |
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| 912 | Ram_wr<='0'; |
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| 913 | dma_rd_request <= '0'; |
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| 914 | dma_wr_request <= '0'; |
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| 915 | Ram_data_out<=(others=>'0'); |
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| 916 | Result <=(others=>'0'); |
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| 917 | Ready<='0'; |
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| 918 | when fetch_addresses => priority_rotation <='0'; |
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| 919 | fifo_rd_en <= rd_ok; |
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| 920 | switch_port_in_data <= (others =>'-'); |
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| 921 | switch_port_in_wr_en <= '0'; |
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| 922 | AppInitReq<='0'; |
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| 923 | Ram_rd<='0'; |
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| 924 | Ram_wr<='0'; |
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| 925 | dma_rd_request <= '0'; |
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| 926 | dma_wr_request <= '0'; |
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| 927 | Ram_data_out<=(others=>'0'); |
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| 928 | Result <=(others=>'0'); |
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| 929 | Ready<='0'; |
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| 930 | when decode_packet_type2 =>priority_rotation <='0'; |
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| 931 | fifo_rd_en <= '0'; |
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| 932 | switch_port_in_data <= data_to_send; |
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| 933 | switch_port_in_wr_en <= '0'; |
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| 934 | AppInitReq<='0'; |
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| 935 | Ram_rd<='0'; |
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| 936 | Ram_wr<='0'; |
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| 937 | dma_rd_request <= '0'; |
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| 938 | dma_wr_request <= '0'; |
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| 939 | Ram_data_out<=(others=>'0'); |
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| 940 | Result <=(others=>'0'); |
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| 941 | Ready<='0'; -- fin du module |
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| 942 | |
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| 943 | when ex1_barrier1 => priority_rotation <='0'; |
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| 944 | fifo_rd_en <= '0'; |
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| 945 | switch_port_in_data <= packet_type & pid_counter; |
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| 946 | switch_port_in_wr_en <= not(switch_port_in_full); |
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| 947 | AppInitReq<='0'; |
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| 948 | Ram_rd<='0'; |
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| 949 | Ram_wr<='0'; |
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| 950 | dma_rd_request <= '0'; |
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| 951 | dma_wr_request <= '0'; |
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| 952 | Ram_data_out<=(others=>'0'); |
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| 953 | Result <=(others=>'0'); |
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| 954 | Ready<='0'; -- fin du module |
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| 955 | |
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| 956 | when ex1_barrier2 => priority_rotation <='0'; |
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| 957 | fifo_rd_en <= '0'; |
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| 958 | switch_port_in_data <= p_len; |
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| 959 | switch_port_in_wr_en <= not(switch_port_in_full); |
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| 960 | AppInitReq<='0'; |
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| 961 | Ram_rd<='0'; |
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| 962 | Ram_wr<='0'; |
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| 963 | dma_rd_request <= '0'; |
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| 964 | dma_wr_request <= '0'; |
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| 965 | Ram_data_out<=(others=>'0'); |
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| 966 | Result <=(others=>'0'); |
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| 967 | Ready<='0'; -- fin du module |
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| 968 | |
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| 969 | when ex1_barrier3 => priority_rotation <='0'; |
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| 970 | fifo_rd_en <= '0'; |
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| 971 | switch_port_in_data <= "0000" & pid; |
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| 972 | switch_port_in_wr_en <= not(switch_port_in_full); |
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| 973 | AppInitReq<='0'; |
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| 974 | Ram_rd<='0'; |
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| 975 | Ram_wr<='0'; |
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| 976 | dma_rd_request <= '0'; |
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| 977 | dma_wr_request <= '0'; |
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| 978 | Ram_data_out<=(others=>'0'); |
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| 979 | Result <=(others=>'0'); |
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| 980 | Ready<='0'; -- fin du module |
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| 981 | |
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| 982 | when ex1_barrier4 => priority_rotation <='0'; |
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| 983 | fifo_rd_en <= '0'; |
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| 984 | switch_port_in_data <= "0000" & pid; |
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| 985 | switch_port_in_wr_en <= '0'; |
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| 986 | AppInitReq<='0'; |
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| 987 | dma_rd_request <= '0'; |
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| 988 | Ram_rd<='0'; |
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| 989 | Ram_wr<='0'; |
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| 990 | dma_wr_request <= '0'; |
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| 991 | Ram_data_out<=(others=>'0'); |
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| 992 | Result <=(others=>'0'); |
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| 993 | Ready<='0'; -- fin du module |
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| 994 | |
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| 995 | when ex1_get1 => priority_rotation <='0'; |
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| 996 | fifo_rd_en <= '0'; |
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| 997 | switch_port_in_data <= data_to_send; |
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| 998 | switch_port_in_wr_en <= Wr_ok; |
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| 999 | AppInitReq<='0'; |
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| 1000 | Ram_rd<='0'; |
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| 1001 | Ram_wr<='0'; |
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| 1002 | dma_rd_request <= '0'; |
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| 1003 | dma_wr_request <= '0'; |
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| 1004 | Ram_data_out<=(others=>'0'); |
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| 1005 | Result <=(others=>'0'); |
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| 1006 | Ready<='0'; -- fin du module |
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| 1007 | when ex1_get2 => priority_rotation <='0'; |
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| 1008 | fifo_rd_en <= '0'; |
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| 1009 | switch_port_in_data <= data_to_send; |
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| 1010 | switch_port_in_wr_en <='0'; |
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| 1011 | AppInitReq<='0'; |
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| 1012 | Ram_rd<='0'; |
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| 1013 | Ram_wr<='0'; |
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| 1014 | dma_rd_request <= '0'; |
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| 1015 | dma_wr_request <= Wr_ok; |
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| 1016 | Ram_rd<='0'; |
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| 1017 | Ram_wr<='0'; |
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| 1018 | Ram_data_out<=(others=>'0'); |
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| 1019 | Result <=(others=>'0'); |
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| 1020 | Ready<='0'; -- fin du module |
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| 1021 | |
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| 1022 | when ex1_get3 => priority_rotation <='0'; |
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| 1023 | fifo_rd_en <= '0'; |
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| 1024 | switch_port_in_data <= ram_data_in;---??? |
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| 1025 | switch_port_in_wr_en <= '0'; |
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| 1026 | AppInitReq<='0'; |
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| 1027 | dma_rd_request <= '0'; |
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| 1028 | dma_wr_request <= '1'; |
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| 1029 | Ram_rd<='0'; |
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| 1030 | Ram_wr<='1'; |
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| 1031 | Ram_data_out<=data_to_send; -- le résultat de l'exécution |
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| 1032 | Ready<='0'; -- fin du module |
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| 1033 | Result <=(2=>'1',others=>'0');--Get completed |
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| 1034 | when ex1_get4 => priority_rotation <='0'; |
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| 1035 | fifo_rd_en <= '0'; |
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| 1036 | switch_port_in_data <= ram_Data_in; |
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| 1037 | switch_port_in_wr_en <= '0'; |
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| 1038 | AppInitReq<='0'; |
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| 1039 | dma_rd_request <= dma_rd; |
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| 1040 | dma_wr_request <= dma_wr; |
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| 1041 | Ram_rd<=rd_ok; |
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| 1042 | Ram_wr<=wr_ok; |
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| 1043 | Ram_data_out<=data_to_send; --"00000001"; |
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| 1044 | Result <=(2=>'1',others=>'0'); --get completed |
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| 1045 | Ready<='0'; -- fin du module |
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| 1046 | when ex1_put1 => priority_rotation <='0'; |
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| 1047 | fifo_rd_en <= '0'; |
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| 1048 | switch_port_in_data <= data_to_send; |
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| 1049 | switch_port_in_wr_en <= '0'; |
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| 1050 | AppInitReq<='0'; |
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| 1051 | dma_rd_request <= '1'; |
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| 1052 | dma_wr_request <= '0'; |
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| 1053 | Ram_rd<='0'; |
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| 1054 | Ram_wr<='0'; |
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| 1055 | Ram_data_out<=(others=>'0'); |
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| 1056 | Result <=(others=>'0'); |
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| 1057 | Ready<='0'; -- fin du module |
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| 1058 | |
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| 1059 | when ex1_put2 => priority_rotation <='0'; |
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| 1060 | fifo_rd_en <= '0'; |
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| 1061 | switch_port_in_data <= data_to_send; |
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| 1062 | switch_port_in_wr_en <= wr_ok; |
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| 1063 | AppInitReq<='0'; |
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| 1064 | Ram_rd<='1'; |
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| 1065 | Ram_wr<='0'; |
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| 1066 | dma_rd_request <= '1'; |
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| 1067 | dma_wr_request <= '0'; |
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| 1068 | Ram_data_out<=(others=>'0'); |
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| 1069 | Result <=(others=>'0'); |
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| 1070 | Ready<='0'; -- fin du module |
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| 1071 | |
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| 1072 | when ex1_put3 => priority_rotation <='0'; |
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| 1073 | fifo_rd_en <= '0'; |
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| 1074 | switch_port_in_data <= ram_data_in; |
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| 1075 | switch_port_in_wr_en <= wr_ok; |
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| 1076 | AppInitReq<='0'; |
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| 1077 | dma_rd_request <= '1'; |
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| 1078 | dma_wr_request <= '0'; |
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| 1079 | Ram_rd<='1'; |
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| 1080 | Ram_wr<='0'; |
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| 1081 | Ram_data_out<=(others=>'0'); |
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| 1082 | Result <=(others=>'0'); |
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| 1083 | Ready<='0'; -- fin du module |
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| 1084 | |
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| 1085 | when ex1_put4 => priority_rotation <='0'; |
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| 1086 | fifo_rd_en <= '0'; |
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| 1087 | switch_port_in_data <= ram_data_in;---??? |
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| 1088 | switch_port_in_wr_en <= '0'; |
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| 1089 | AppInitReq<='0'; |
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| 1090 | dma_rd_request <= rd_ok; |
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| 1091 | dma_wr_request <= wr_ok; |
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| 1092 | Ram_rd<=rd_ok; |
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| 1093 | Ram_wr<=wr_ok; |
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| 1094 | Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution |
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| 1095 | --result(1)<='1'; |
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| 1096 | Result <=(1=>'1',others=>'0');--put completed |
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| 1097 | Ready<='0'; -- fin du module |
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| 1098 | when ex1_put5 => priority_rotation <='0'; |
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| 1099 | fifo_rd_en <= '0'; |
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| 1100 | switch_port_in_data <= ram_Data_in; |
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| 1101 | switch_port_in_wr_en <= '0'; |
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| 1102 | AppInitReq<='0'; |
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| 1103 | dma_rd_request <= dma_rd; |
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| 1104 | dma_wr_request <= dma_wr; |
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| 1105 | Ram_rd<=rd_ok; |
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| 1106 | Ram_wr<=wr_ok; |
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| 1107 | Ram_data_out<=data_to_send; --"00000001"; |
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| 1108 | Result <=(1=>'1',others=>'0'); --put completed |
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| 1109 | Ready<='0'; -- fin du module |
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| 1110 | when ex1_init1 => priority_rotation <='0'; |
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| 1111 | if fifo_empty='0' then |
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| 1112 | fifo_rd_en <= rd_ok; |
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| 1113 | else |
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| 1114 | fifo_rd_en<='0'; |
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| 1115 | end if; |
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| 1116 | switch_port_in_data <= data_to_send; |
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| 1117 | switch_port_in_wr_en <= wr_ok; |
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| 1118 | dma_rd_request <= '0'; |
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| 1119 | dma_wr_request <= '0'; |
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| 1120 | Ram_rd<='0'; |
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| 1121 | Ram_wr<='0'; |
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| 1122 | Ram_data_out<=(others=>'0'); |
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| 1123 | AppInitReq<='1'; |
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| 1124 | Result <=(others=>'0'); |
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| 1125 | when ex1_init_run => priority_rotation <='0'; |
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| 1126 | |
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| 1127 | fifo_rd_en <= fifo_rd; |
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| 1128 | |
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| 1129 | switch_port_in_data <= noc_fifo_in; |
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| 1130 | switch_port_in_wr_en <= fifo_wr; |
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| 1131 | dma_rd_request <= '0'; |
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| 1132 | dma_wr_request <= '0'; |
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| 1133 | Ram_rd<='0'; |
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| 1134 | Ram_wr<='0'; |
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| 1135 | Ram_data_out<=(others=>'0'); |
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| 1136 | AppInitReq<='1'; |
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| 1137 | Result <=(others=>'0'); |
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| 1138 | |
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| 1139 | |
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| 1140 | when ex1_init2=> priority_rotation <='0'; |
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| 1141 | fifo_rd_en <= '0'; |
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| 1142 | switch_port_in_data <= noc_fifo_in; |
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| 1143 | switch_port_in_wr_en <= push; |
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| 1144 | AppInitReq<='1'; |
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| 1145 | dma_rd_request <= '0'; |
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| 1146 | dma_wr_request <= '1'; |
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| 1147 | Ram_rd<='0'; |
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| 1148 | Ram_wr<=wr_ok; |
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| 1149 | Ram_data_out<="00010000"; -- le résultat de l'exécution |
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| 1150 | -- dans le registre status |
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| 1151 | Result <=(others=>'0');-- |
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| 1152 | when ex1_init3=> priority_rotation <='0'; |
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| 1153 | fifo_rd_en <= '0'; |
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| 1154 | switch_port_in_data <= ram_Data_in; |
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| 1155 | switch_port_in_wr_en <= '0'; |
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| 1156 | AppInitReq<='0'; |
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| 1157 | dma_rd_request <= '0'; |
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| 1158 | dma_wr_request <= '1'; |
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| 1159 | Ram_rd<='0'; |
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| 1160 | Ram_wr<='1'; |
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| 1161 | Ram_data_out<="00010000"; |
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| 1162 | Ready<='0'; -- fin du module |
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| 1163 | Result<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit |
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| 1164 | |
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| 1165 | when ex1_spawn => priority_rotation <='0'; |
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| 1166 | fifo_rd_en <= rd_ok; |
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| 1167 | switch_port_in_data <= Data_to_send; |
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| 1168 | switch_port_in_wr_en <= wr_ok; |
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| 1169 | AppInitReq<='0'; |
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| 1170 | dma_rd_request <= '0'; |
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| 1171 | dma_wr_request <= '0'; |
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| 1172 | Ram_rd<='0'; |
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| 1173 | Ram_wr<='0'; |
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| 1174 | Ram_data_out<=(others=>'0'); |
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| 1175 | Result <=(others=>'0'); |
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| 1176 | when ex1_send_ack => priority_rotation <='0'; |
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| 1177 | fifo_rd_en <= rd_ok; |
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| 1178 | switch_port_in_data <= Data_to_send; |
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| 1179 | switch_port_in_wr_en <= wr_ok; |
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| 1180 | AppInitReq<='0'; |
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| 1181 | dma_rd_request <= '0'; |
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| 1182 | dma_wr_request <= '0'; |
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| 1183 | Ram_rd<='0'; |
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| 1184 | Ram_wr<='0'; |
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| 1185 | Ram_data_out<=(others=>'0'); |
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| 1186 | Result <=(others=>'0'); |
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| 1187 | when ex1_ready => |
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| 1188 | Ready<='1'; -- fin du module |
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| 1189 | priority_rotation <='0'; |
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| 1190 | fifo_rd_en <= '0'; |
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| 1191 | switch_port_in_data <= (others =>'-'); |
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| 1192 | switch_port_in_wr_en <= '0'; |
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| 1193 | dma_rd_request <= '0'; |
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| 1194 | dma_wr_request <= '0'; |
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| 1195 | Ram_rd<='0'; |
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| 1196 | Ram_wr<='0'; |
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| 1197 | Ram_data_out<=(others=>'0'); |
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| 1198 | AppInitReq<='0'; |
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| 1199 | --Result <=Result; |
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| 1200 | |
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| 1201 | when others => priority_rotation <='0'; |
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| 1202 | fifo_rd_en <= '0'; |
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| 1203 | switch_port_in_data <= (others =>'-'); |
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| 1204 | switch_port_in_wr_en <= '0'; |
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| 1205 | dma_rd_request <= '0'; |
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| 1206 | dma_wr_request <= '0'; |
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| 1207 | Ram_rd<='0'; |
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| 1208 | Ram_wr<='0'; |
---|
| 1209 | Ram_data_out<=(others=>'0'); |
---|
| 1210 | AppInitReq<='0'; |
---|
| 1211 | Result <=(others=>'0'); |
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| 1212 | end case; |
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| 1213 | |
---|
| 1214 | end process; |
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| 1215 | |
---|
| 1216 | end Behavioral; |
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| 1217 | |
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