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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd @ 71

Last change on this file since 71 was 70, checked in by rolagamo, 11 years ago

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1	----------------------------------------------------------------------------------
2	-- Company: GRIIA - ETIS - LIP6
3	-- Engineer: GAMOM, KIEGAING
4	--
5	-- Create Date: 01:02:10 06/17/2011
6	-- Design Name:
7	-- Module Name: EX2_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- machine a etat qui execute la reception des packet dans le core mpi
13	-- Dependencies:
14	--ss
15	-- Revision: 26/01/2012
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib ;
22	use IEEE.STD_LOGIC_1164.ALL;
23	use IEEE.Numeric_std.ALL;
24	use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use Work.Packet_type.ALL;
26	use NocLib.CoreTypes.all;
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity EX2_FSM is
33
34	generic (
35	pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
36	nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
37	);
38	Port ( clk : in STD_LOGIC;
39	reset : in STD_LOGIC;
40
41	Instruction_en : in std_logic;
42
43	dma_wr_grant : in STD_LOGIC;
44	dma_wr_request : out STD_LOGIC;
45	dma_rd_grant : in STD_LOGIC;
46	dma_rd_request : out STD_LOGIC;
47	ram_rd : out std_logic;
48	ram_wr : out std_logic;
49	ram_address : out std_logic_vector(ADRLEN-1 downto 0);
50	Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
51	Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
52
53	fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
54	fifo_wr_en : out STD_LOGIC;
55	fifo_full : in STD_LOGIC;
56	Rec_Rdy : OUT std_logic;
57	Rec_Data : OUT Typ_PortIO(0 to 3);
58	Rec_Ack : IN std_logic;
59	AppRank : in STD_LOGIC_VECTOR(3 downto 0);
60	AppSize : in STD_LOGIC_VECTOR(3 downto 0);
61	packet_received : out STD_LOGIC;
62	packet_ack : in STD_LOGIC;
63	barrier_completed : out STD_LOGIC;
64	Ready : Out std_logic;
65	AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
66	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
67	Initialized:in std_logic ; -- état de la Lib
68	Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
69	switch_data_available : in STD_LOGIC;
70	switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
71	switch_port_out_rd_en : out STD_LOGIC
72
73
74
75	);
76	end EX2_FSM;
77
78	architecture Behavioral of EX2_FSM is
79	--module pour la lecture des données sur le réseau
80	CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu
81	component Proto_receiv is
82	generic (sizemem : natural := 64);
83	port (
84	clk,reset : in std_logic;
85	fifo_empty,fifo_full : in std_logic;
86	rcv_start : in std_logic; --début de la réception
87	rcv_ack :in std_logic; -- acquittement de la réception
88	rcv_comp : out std_logic; -- fin de la réception
89	pop : out std_logic:='0';
90	fifo_out : in std_logic_vector(Word-1 downto 0);
91	mem :out memory(0 to sizemem-1));
92	end component Proto_receiv;
93
94	COMPONENT SetBit
95	PORT(
96	clk : IN std_logic;
97	reset : IN std_logic;
98	BitMask : IN std_logic_vector(7 downto 0);
99	BitVal : IN std_logic;
100	start : in std_logic;
101	done : out std_logic;
102	dma_wr_grant : IN std_logic;
103	dma_rd_grant : IN std_logic;
104	Ram_data_in : out std_logic_vector(7 downto 0);
105	dma_wr_request : OUT std_logic;
106	dma_rd_request : OUT std_logic;
107	ram_rd : OUT std_logic;
108	ram_wr : OUT std_logic;
109	ram_address : IN std_logic_vector(15 downto 0);
110	Ram_data_out : in std_logic_vector(7 downto 0)
111	);
112	End component SetBit;
113	-- définition du type etat de la machine à etat
114	type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2,
115	fetch_addresses,ex2_spawn,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4,
116	ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack,
117	ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
118	ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2);
119	type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6);
120	signal Next_Ex2_state,ex2_state :fsm_states;
121	signal ack_state,next_ack_state : fsm_ack;
122	-- machine a etat du module
123	signal packet_type : std_logic_vector(3 downto 0);
124	signal P_len_i,P_len : std_logic_vector(Word-1 downto 0);
125	signal barrier_counter : std_logic_vector(3 downto 0);
126	signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0');
127	signal n,n_i : natural range 0 to 15;
128	signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'-');
129	signal data_to_write_fifo : std_logic_vector(Word-1 downto 0);
130	--*******************************************
131	--signaux pour la fonction SetBit
132	signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
133	signal sb_BitVal,sb_start,sb_done : std_logic:='0';
134	signal sb_Ram_data_in : std_logic_vector(7 downto 0);
135	signal sb_dma_wr_request : std_logic;
136	signal sb_dma_rd_request : std_logic;
137	signal sb_ram_rd : std_logic;
138	signal sb_ram_wr : std_logic;
139	signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
140	signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
141	--*********************************************
142	signal Ex2_on : std_logic:='0';
143	signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
144	signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement
145	signal dest_ack:std_logic_vector(3 downto 0) :=(others=>'0');
146	signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0');
147	signal Result_i : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
148	--signaux pour l'untilisation du composant de réception
149	signal rfifo_empty,rfifo_full:std_logic;
150	signal rcv_start,rcv_comp,rcv_ack:std_logic;
151	signal rpop:std_logic;
152	--signal mem:memory(0 to Msize-1));
153	begin
154	ram_address <= dest_address;
155	--fifo_data <= data_to_write_fifo;
156	Result<=Result_i;
157	p_instr_fifo:process(ack_state,data_to_write_fifo,wr_ack,to_fifo_ack,instr_ack)
158	begin
159	if instr_ack='1' then
160	fifo_data<=to_fifo_ack;
161	else
162	fifo_data<=data_to_write_fifo;
163	end if;
164	end process p_instr_fifo;
165
166
167
168	R0:proto_receiv generic map (sizemem =>4)
169	port map (
170	clk=>clk,
171	reset=>reset,
172	rcv_start=>rcv_start,
173	rcv_comp=>rcv_comp,
174	rcv_ack=>rcv_ack,
175	fifo_empty=>rfifo_empty,
176	fifo_full=>rfifo_full,
177	fifo_out=>switch_port_out_data,
178	pop=>rpop,
179	mem=>open
180
181	);
182	--envoie de l'acquittement
183	setbit1:SetBit
184	PORT MAP (
185	clk =>clk,
186	reset =>reset,
187	BitMask =>sb_bitMask,
188	BitVal =>sb_bitval,
189	dma_wr_grant =>dma_wr_grant,
190	dma_rd_grant =>dma_rd_grant,
191	Ram_data_in => sb_Ram_data_in,
192	dma_wr_request =>sb_dma_wr_request,
193	dma_rd_request =>sb_dma_rd_request,
194	ram_rd =>sb_ram_rd,
195	ram_wr =>sb_ram_wr,
196	ram_address =>dest_address,
197	Ram_data_out =>sb_ram_data_out,
198	Start =>sb_start,
199	done =>sb_done
200	);
201
202	-- processus de transistion entre les etats
203	ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized,
204	switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len,
205	sent_ack,wr_ack,to_fifo_ack,dest_address)
206	variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
207	variable tempval : std_logic_vector(Word-1 downto 0);
208	variable n_e:natural range 0 to 15 :=0;
209	procedure read_nocdat_fsm(sdata_avail: std_logic;
210	signal rd,wr:out std_logic;
211	signal Plen : inout std_logic_vector(Word-1 downto 0);
212	variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is
213	--lit la suite des données qui sont dans le NoC et identifie le paramètre important
214	begin
215	if n_e<3 then
216	wr<='0';
217	if sdata_avail='1' then
218	n:=n_e+1;
219	rd<='1';
220	plen <=plen-1;
221	else
222	rd<='0';
223	end if;
224	--result_i<=(others=>'0');
225	elsif n_e=3 then
226	if sdata_avail='1' then
227	n:=n_e+1;
228	rd<='0';
229	--P_len <=P_len_i -1;
230	--data_to_ram<=sportdout;
231	--Result_i<=sport_out_data;
232	else
233	rd<='0';
234	end if;
235	end if;
236	end procedure;
237
238	begin
239
240	Next_Ex2_state <= Ex2_state;
241	Ex2_on<='0';
242	barrier_counter <= "0000";
243	--n_i<=n;
244	dest_address_i<=dest_address;
245	-- else
246	Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
247	n_i<=n; --valeur par défaut de n_i
248	P_len_i<=P_len;
249	case ex2_state is
250	when Ex2_ready => if Instruction_en='1' then
251	Next_Ex2_state <= fetch_packet_type;
252	end if;
253	rd_ok<='0';wr_ok<='0';
254	when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1'
255	Next_Ex2_state <= decode_packet_type;
256	packet_type<=switch_port_out_data(7 downto 4);
257	Dest_ack<=switch_port_out_data(3 downto 0);
258	Rec_Data(0)<=switch_port_out_data; --récupérer la première donnée reçue !
259	rd_ok<='1';
260	else
261	Next_Ex2_state <= Ex2_Ready;
262	rd_ok<='0';
263	end if;
264	n_i<=0;
265	when decode_packet_type => rd_ok<='0';
266	if switch_data_available ='0' then
267	Next_Ex2_state <= decode_packet_type;
268	else
269	rd_ok<='1';
270	if packet_type = MPI_PUT then
271	P_len_i <= switch_port_out_data - 2;
272	n_i<=0;
273	Next_Ex2_state <= decode_packet_type2;
274	elsif packet_type = MPI_GET then
275	P_len_i <=switch_port_out_data-2;
276	Next_Ex2_state <= decode_packet_type2;
277	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
278	P_len_i <= switch_port_out_data;
279	n_i<=0;
280	Next_Ex2_state <= ex2_barrier1;
281	elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
282	n_i<=0;
283	wr_ok<='0';
284	--rd_ok<='1';
285	P_len_i <= switch_port_out_data-2;
286	Rec_Data(1)<=switch_port_out_data;
287	Next_Ex2_state <= ex2_init1;
288	elsif packet_type = MPI_ACK then
289	n_i<=0;
290	wr_ok<='0';
291	rd_ok<='0';
292	P_len_i <= switch_port_out_data-2;
293	Next_Ex2_state <= ex2_ack;
294	elsif packet_type = MPI_SPAWN then
295	Next_Ex2_state <= ex2_spawn;
296	else
297	Next_Ex2_state <= decode_packet_type;
298	rd_ok<='0';
299	end if;
300	end if;
301	when decode_packet_type2 => if packet_type = MPI_PUT then
302	Next_Ex2_state <= fetch_addresses;
303	else
304	Next_Ex2_state <= ex2_get1;
305	end if;
306	when fetch_addresses => if n=0 then
307	if switch_data_available = '1' then
308	dest_address_i(15 downto 8) <= switch_port_out_data;
309	n_i <= n + 1;
310	rd_ok<='1';
311	else
312	rd_ok<='0';
313	end if;
314	elsif n=1 then
315	if switch_data_available = '1' then
316	dest_address_i(Word-1 downto 0) <= switch_port_out_data;
317	P_len_i <= P_len - 2;
318	Next_Ex2_state <= ex2_put1;
319	n_i<=0;
320	rd_ok<='1';
321	else
322	rd_ok<='0';
323	Next_Ex2_state <= fetch_addresses;
324	end if;
325	end if;
326
327	when ex2_ack => rd_ok<='0';
328	if n<2 then --réception de l'acquittement.
329	n_e:=n_i;
330	read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
331	n_i<=n_e;
332	elsif n=2 then
333	if switch_data_available='1' then
334	n_i<=n+1;
335	rd_ok<='1';
336
337	data_to_ram<=switch_port_out_data;
338	Result_i<=switch_port_out_data;
339	end if;
340
341	elsif n=3 then
342	n_i<=n+1;
343	if data_to_ram(7 downto 4)=MPI_PUT then
344	Result_i<=data_to_ram;
345	dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
346	wr_ok<='1';
347	elsif data_to_ram(7 downto 4)=MPI_GET then
348	Result_i<=data_to_ram;
349	wr_ok<='1'; --
350	dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
351	elsif data_to_ram(7 downto 4)=MPI_SPAWN then
352	Result_i<=data_to_ram;
353	wr_ok<='1'; --
354	dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16));
355	elsif data_to_ram(7 downto 4)=MPI_INIT then
356	Result_i<=data_to_ram;
357	dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16));
358	wr_ok<='1'; --
359	--
360	else
361	Result_i<="00000000";
362	wr_ok<='0'; --
363	end if;
364	elsif n=4 then --set acknowlege bit of the instruction
365	sb_start<='1';
366	sb_bitMask<=x"20";--cinquième bit à un
367	sb_bitval<='1';
368	if sb_done='1' then
369	n_i<=5;
370	sb_start<='0';
371	sb_bitval<='0';
372	end if;
373	elsif n=5 then
374	Next_Ex2_state<=Ex2_Ready;
375	n_i<=0;
376	end if;
377	when ex2_init1 => if n<2 then -- execution du mpi Init
378	wr_ok<='0';
379	if switch_data_available='1' then
380	n_i<=n+1;
381	rd_ok<='1';
382	P_len_i <=P_len-1;
383	Rec_Data(n+2)<=switch_port_out_data;
384	data_to_ram<=switch_port_out_data;
385	Result_i<=switch_port_out_data;
386	else
387	rd_ok<='0';
388	n_i<=n;
389	end if;
390	result_i<=(others=>'0');
391	elsif n=2 then
392	--if switch_data_available='1' then
393	n_i<=n+1;
394	rd_ok<='0';
395	-- --P_len <=P_len -1;
396	--
397	-- else
398	-- rd_ok<='0';
399	-- end if;
400	elsif n=3 then
401	rd_ok<='0'; -- normalement plus rien à lire
402	n_i<=n+1;
403	if Initialized='1' then
404	if data_to_ram(7 downto 4)=INIT_SEEKMAIN then
405	Result_i<=data_to_ram;
406	wr_ok<='1'; --permet d'activer Init de Ex_4
407	elsif data_to_ram(7 downto 4)=INIT_STAT then
408	Result_i<=data_to_ram;
409	wr_ok<='1'; --permet d'activer Init de Ex_4
410	elsif data_to_ram(7 downto 4)=INIT_REGISTER then
411	Result_i<=data_to_ram;
412	wr_ok<='1'; --permet d'activer Init de Ex_4
413	elsif data_to_ram(7 downto 4)=INIT_SPAWN then
414	Result_i<=data_to_ram;
415	wr_ok<='1'; --permet d'activer Init de Ex_4
416	-- il faut mettre à jour l'état de Spawn
417	else
418	Result_i<="00000000";
419	wr_ok<='0'; --permet d'activer Init de Ex_4
420	end if;
421	end if;
422	elsif n=4 then
423	n_i<=n+1;
424	elsif n=5 then
425	if p_len=0 then
426	Next_Ex2_state<=ex2_init2;
427	rd_ok<='0';
428	else
429	p_len_i <=p_len -1;
430	rd_ok<='1'; --vider le tampon de lecture pour ce paquet !
431	end if;
432
433	end if;
434	when ex2_init2=> if n=5 then
435	if AppInitAck='1' then
436	n_i<=n+1;
437	Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init
438	end if;
439	elsif n=6 then
440	Next_Ex2_state<=Ex2_Ready;
441	n_i<=0;
442	end if;
443
444	when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch
445	wr_ok<='0';
446	if n=0 then
447	instr_ack_i<='1'; --activer l'envoie de l'accusé de réception
448	data_to_write_fifo<=to_fifo_ack;
449	wr_ok<=wr_ack;
450	if sent_ack='1' then
451	n_i<=1;
452	instr_ack_i<='0';
453	end if;
454
455	elsif n=1 then
456	if dma_wr_grant = '1' then
457	Next_Ex2_state <= ex2_put2;
458	data_to_ram<=switch_port_out_data;
459	rd_ok<='1';
460	n_i<=0;
461	delai:=0;
462	else
463	Next_Ex2_state <= ex2_put1;
464	end if;
465	end if;
466	when ex2_put2 => if unsigned( P_len) > 1 then
467
468	if switch_data_available = '1' and dma_wr_grant='1' then
469
470	P_len_i <= P_len - 1;
471	dest_address_i <= dest_address + 1;
472	Next_Ex2_state <= ex2_put2;
473	rd_ok<='1';
474	wr_ok<='1';
475	data_to_ram<=switch_port_out_data;
476	else
477	if switch_data_available = '1' and dma_wr_grant='0' then
478	if delai=0 then
479	data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
480	end if;
481	delai:=1;--indique qu'un temps supplémentaire est
482	--nécessaire pour écrire la donnée en RAM
483	end if;
484	Next_Ex2_state <= ex2_put2;
485	rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données
486	end if;
487	else
488
489	if switch_data_available = '1' and n=0 then
490	--la dernière donnée à écrire en RAM
491	data_to_ram<=switch_port_out_data;
492	rd_ok<='0';
493	wr_ok<='1';
494	n_i<=n+1;
495	else
496	rd_ok<='1';
497	wr_ok<='0';
498	end if;
499	if dma_wr_grant='1' and n=1 then
500
501	Next_Ex2_state <= ex2_put3;
502	Wr_ok<='0';
503	n_i<=0;
504	end if;
505	end if;
506
507	when ex2_put3 => if dma_rd_grant='1' then
508	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
509	Next_Ex2_state <= ex2_put4;
510	n_i<=0;
511	rd_ok<='1';
512	wr_ok<='0';
513	end if;
514
515	when ex2_put4 => if n<=4 then
516
517	dma_wr<='1'; --demander un accès exclusif au bus
518	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
519	else
520	dma_wr<='0';
521	dma_rd<='0';
522	end if;
523	if n=0 then
524	if dma_rd_grant='1' then
525	n_i<=n+1;
526	else
527	rd_ok<='1';
528	wr_ok<='0';
529	end if;
530	elsif n=1 then
531	if dma_rd_grant='1' then
532	n_i<=n+1;
533	else
534	rd_ok<='1';
535	wr_ok<='0';
536	end if;
537	elsif n=2 then
538	if dma_rd_grant='1' then
539	n_i<=n+1;
540	tempval:=Ram_data_out;
541	tempval(4):='1'; --SET du bit DReceived
542	tempval(1):='0'; --reset du bit DRING !!
543	data_to_ram<=tempval;
544	rd_ok<='0';
545	wr_ok<='1';
546	else
547	rd_ok<='1';
548	wr_ok<='0';
549	n_i<=n-1;
550	end if;
551	elsif n=3 then
552	if dma_wr_grant='1' then
553	rd_ok<='0';
554	wr_ok<='1';
555	n_i<=n+1;
556	end if;
557	elsif n=4 then
558	if dma_wr_grant='1' then
559	rd_ok<='0';
560	wr_ok<='1';
561	Next_Ex2_state <= ex2_put5;
562	n_i<=0;
563	end if;
564	end if;
565
566
567
568	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
569	when ex2_put5 =>
570	Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put
571
572	when ex2_spawn =>
573
574	if n<2 then
575	n_e:=n;
576	read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
577	n_i<=n_e;
578	elsif n=2 then
579	Result_i<=Switch_port_out_data;
580	Data_to_ram<=Switch_port_out_data;
581	n_i<=n+1;
582	elsif n=3 then
583	if data_to_ram(7 downto 4)=SPAWN_LOAD then
584	Result_i<=data_to_ram;
585	wr_ok<='1'; --permet d'activer Init de Ex_4
586	elsif data_to_ram(7 downto 4)=SPAWN_ERR then
587	Result_i<=data_to_ram;
588	wr_ok<='0'; --permet d'activer Init de Ex_4
589	else
590	Result_i<=(others=>'0');
591
592	end if;
593	n_i<=n+1;
594	elsif n=4 then
595	if AppInitAck='1' then
596	wr_ok<='1';
597	rd_ok<='0';
598	n_i<=n+1;
599	end if;
600	elsif n=5 then
601	wr_ok<='0';
602	rd_ok<='0';
603	n_i<=0;
604	Next_Ex2_state <=Ex2_Ready;
605	end if;
606
607	when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch
608	--ack_state<=next_ack_state; --MAE d'envoie de AR
609	if n=0 then
610	instr_ack_i<='1'; --activer l'envoie de l'accusé de réception
611	data_to_write_fifo<=to_fifo_ack;
612	wr_ok<=wr_ack;
613	if sent_ack='1' then
614	n_i<=1;
615	instr_ack_i<='0';
616	wr_ok<='0';
617	--if switch_data_available='1' then
618	rd_ok<='0';--
619	--P_len<=P_len-1;
620	--end if;
621	end if;
622
623	elsif n=1 then
624	if switch_data_available='1' then
625	if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo
626	data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put
627	wr_ok<='1';
628	rd_ok<='1'; --autoriser la lecture du crossbar
629	P_len_i<=P_len-1;
630	n_i<=n+1;
631	else
632	Wr_ok<='0';
633	Rd_ok<='0';
634	end if;
635	else
636	Wr_ok<='0';
637	rd_ok<='0';
638	end if;
639	elsif n=2 then
640	if switch_data_available='1' then
641	if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo
642	--data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put
643	--P_len_i <= P_len-1;--le nombre d'octet qui restent à copier
644	Next_Ex2_state <= ex2_get2;
645	wr_ok<='0';
646	rd_ok<='0'; --autoriser la lecture du crossbar
647	n_i<=0;
648	else
649	rd_ok<='0';
650	wr_ok<='0';
651	end if;
652	else
653	rd_ok<='0';
654	wr_ok<='0';
655	end if;
656	end if;
657	when ex2_get2 => if P_len>0 then
658	if fifo_full = '0' and switch_data_available ='1' then
659	data_to_write_fifo <= switch_port_out_data;--la longueur initiale du GET
660	p_len_i <= P_len - 1;
661	Next_Ex2_state <= ex2_get2;
662	wr_ok<='1';
663	Rd_ok<='1';
664	elsE
665
666	wr_ok<='0';
667	Rd_ok<='0';
668	END IF;
669	else
670	if n=0 then
671	if fifo_full='0' then
672	wr_ok<='0';--une impulsion en plus
673	n_i<=n+1;
674	Next_Ex2_state <= ex2_get2;
675	else
676	wr_ok<='0';
677	end if;
678
679	else
680	Next_Ex2_state <= ex2_get3;
681	n_i<=0;
682	wr_ok<='0';
683	end if;
684	rd_ok<='0';
685	end if;
686	when ex2_get3 => wr_ok<='0';
687	if dma_rd_grant='1' then -- fin du mpi_get
688	Next_Ex2_state <= ex2_get4;
689	n_i<=0;
690	--activer le bit sending du registre de transfert
691	else
692	Next_Ex2_state <= ex2_get3;
693	end if;
694
695	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
696	when ex2_get4 => if n <4 then
697
698	dma_wr<='1'; --demander un accès exclusif au bus
699	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
700	else
701	dma_wr<='0';
702	dma_rd<='0';
703	end if;
704	if n=0 then
705	if dma_rd_grant='1' then
706	n_i<=n+1;
707
708	end if;
709	rd_ok<='1';
710	wr_ok<='0';
711	elsif n=1 then
712	if dma_rd_grant='1' then
713	n_i<=n+1;
714
715	end if;
716	rd_ok<='1';
717	wr_ok<='0';
718
719	elsif n=2 then
720	if dma_rd_grant='1' and dma_wr_grant='1' then
721	n_i<=n+1;
722	tempval:=Ram_data_out;
723	tempval(2):='1'; --mise à 1 du Bit Dreceiving
724	--tempval(5):='0'; --Mise à 0 du Bit Sent
725	data_to_ram<=tempval;
726	rd_ok<='0';
727	wr_ok<='1';
728	else
729	rd_ok<='1';
730	wr_ok<='0';
731	end if;
732
733	elsif n=3 then
734	if dma_wr_grant = '1' then
735	n_i<=n+1;
736	rd_ok<='0';
737	wr_ok<='1';
738	end if;
739	elsif n=4 then
740	if dma_wr_grant = '1' then
741	n_i<=0;
742	Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get
743	else
744	rd_ok<='0';
745	wr_ok<='1';
746	--n<=n-1;
747	end if;
748	end if;
749
750
751	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
752	-- execution du barrier
753	when ex2_barrier1 => if switch_data_available = '1' then
754	pading_data <= switch_port_out_data;
755	Next_Ex2_state <= ex2_barrier2;
756	else
757	Next_Ex2_state <= ex2_barrier1;
758	end if;
759	when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then
760	barrier_counter <= barrier_counter + 1;
761	Next_Ex2_state <= ex2_barrier4;
762	else
763	Next_Ex2_state <= ex2_barrier3;
764	end if;
765	when ex2_barrier3 => if n < 10 then
766	n_i<= n + 1;
767	Next_Ex2_state <= ex2_barrier3;
768	else
769	Next_Ex2_state <= Ex2_Ready;
770	end if;
771	when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED
772	data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000";
773	Next_Ex2_state <= ex2_barrier5;
774	else
775	Next_Ex2_state <= Ex2_Ready;
776	end if;
777	when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED
778	data_to_write_fifo <= "00000011";
779	Next_Ex2_state <= ex2_barrier6;
780	else
781	Next_Ex2_state <= ex2_barrier5;
782	end if;
783	when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
784	data_to_write_fifo <= "00000000";
785	Next_Ex2_state <= ex2_barrier7;
786	else
787	Next_Ex2_state <= ex2_barrier6;
788	end if;
789	when ex2_barrier7 => if fifo_full = '0' then
790	barrier_counter <= "0000";
791	Next_Ex2_state <= Ex2_Ready;
792	else
793	Next_Ex2_state <= ex2_barrier7;
794	end if;
795
796	when others => Next_Ex2_state <= Ex2_Ready;
797	end case;
798
799	end process;
800
801	-- sortie de la machine à etat
802	--
803	ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,
804	switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_dma_rd_request,n)
805	variable transact : std_logic_vector(Word-1 downto 0);
806	begin
807	-- code fonctionnel
808	case Ex2_state is
809	when Ex2_Ready => fifo_wr_en <= '0';
810	switch_port_out_rd_en <= '0';
811	packet_received <= '0';
812	dma_wr_request <= '0';
813	dma_rd_request <= '0';
814	barrier_completed <= '0';
815	Ram_data_in<=(others=>'-');
816	Ram_rd<='0';
817	Ram_wr<='0';
818	Ready<='1';
819	AppInitReq<='0';
820	when fetch_packet_type => fifo_wr_en <= '0';
821	switch_port_out_rd_en <= rd_ok;
822	packet_received <= '0';
823	dma_wr_request <= '0';
824	dma_rd_request <= '0';
825	barrier_completed <= '0';
826	Ram_data_in<=(others=>'-');
827	Ram_rd<='0';
828	Ram_wr<='0';
829	Ready<='0';
830	AppInitReq<='0';
831
832
833	when decode_packet_type => fifo_wr_en <= '0';
834	switch_port_out_rd_en <= rd_ok;
835	packet_received <= '0';
836	dma_wr_request <= '0';
837	dma_rd_request <= '0';
838	Ram_rd<='0';
839	Ram_wr<='0';
840	Ram_data_in<=(others=>'-');
841	barrier_completed <= '0';
842	AppInitReq<='0';
843	Ready<='0';
844
845	when decode_packet_type2 => fifo_wr_en <= '0';
846	switch_port_out_rd_en <= '0';
847	packet_received <= '0';
848	dma_wr_request <= '0';
849	dma_rd_request <= '0';
850	Ram_rd<='0';
851	Ram_wr<='0';
852	Ram_data_in<=(others=>'-');
853	barrier_completed <= '0';
854	AppInitReq<='0';
855	Ready<='0';
856	when fetch_addresses => fifo_wr_en <= '0';
857	switch_port_out_rd_en <= rd_ok;
858	packet_received <= '0';
859	dma_wr_request <= '0';
860	dma_rd_request <= '0';
861	Ram_rd<='0';
862	Ram_wr<='0';
863	Ram_data_in<=(others=>'-');
864	barrier_completed <= '0';
865	AppInitReq<='0';
866	Ready<='0';
867	when ex2_ack =>
868	Ready<='0';
869	switch_port_out_rd_en<=rd_ok;
870	fifo_wr_en <= '0';
871	packet_received <= '0';
872	AppInitReq<='0';
873	barrier_completed <= '0';
874	dma_rd_request <= sb_dma_rd_request;
875	dma_wr_request <= sb_dma_wr_request;
876	Ram_rd<=sb_ram_rd;
877	Ram_wr<=sb_ram_wr;
878	sb_ram_data_out<=Ram_data_out;
879	Ram_data_in<=sb_ram_data_in;
880	when ex2_put1 => fifo_wr_en <= wr_ok;
881	switch_port_out_rd_en <= '0';
882	packet_received <= '0';
883	dma_wr_request <= '1';
884	dma_rd_request <= '0';
885	Ram_rd<='0';
886	Ram_wr<='0';
887	Ram_data_in<=(others=>'-');
888	barrier_completed <= '0';
889	AppInitReq<='0';
890	Ready<='0';
891
892	when ex2_put2 => Ready<='0';
893	fifo_wr_en <= '0';
894	switch_port_out_rd_en <=rd_ok;
895
896	if rd_ok = '1' then
897
898	Ram_data_in<=switch_port_out_data;
899	else
900	Ram_data_in<=data_to_ram;
901	end if;
902	Ram_wr<='1';
903	Ram_rd<='0';
904	packet_received <= '0';
905	dma_rd_request <= '0';
906	dma_wr_request <= '1';
907	AppInitReq<='0';
908	barrier_completed <= '0';
909	when ex2_put3 => Ready<='0';
910	fifo_wr_en <= '0';
911	switch_port_out_rd_en <=rd_ok;
912	--ne pas corrompre le contenu de la RAM
913	--Ram_data_in<=data_to_ram;
914	Ram_wr<='0';
915	Ram_rd<='1';
916	packet_received <= '0';
917	dma_rd_request <= '1';
918	dma_wr_request <= '0';
919	AppInitReq<='0';
920	barrier_completed <= '0';
921
922
923	when ex2_put4 => fifo_wr_en <= '0';
924	Ready<='0';
925	switch_port_out_rd_en <= '0';
926	packet_received <= '1';
927	dma_rd_request <= dma_rd;
928	dma_wr_request <=dma_wr;
929	Ram_wr<=wr_ok;
930	Ram_rd<=rd_ok;
931	AppInitReq<='0';
932	barrier_completed <= '0';
933	Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution
934
935	when ex2_put5 =>
936	Ready<='0';
937	switch_port_out_rd_en<='0';
938	fifo_wr_en <= '0';
939	packet_received <= '1';
940	AppInitReq<='0';
941	barrier_completed <= '0';
942	dma_rd_request <= dma_rd;
943	dma_wr_request <= dma_wr;
944	Ram_rd<=rd_ok;
945	Ram_wr<=wr_ok;
946	Ram_data_in<=data_to_ram;
947	--Result <=(1=>'1',others=>'0'); --put completed
948
949	when ex2_get1=> fifo_wr_en <= wr_ok;
950	switch_port_out_rd_en <= rd_ok;
951	packet_received <= '0';
952	dma_wr_request <= '0';
953	dma_rd_request <= '0';
954	Ram_rd<='0';
955	Ram_wr<='0';
956	Ram_data_in<=(others=>'-');
957	barrier_completed <= '0';
958	AppInitReq<='0';
959	Ready<='0';
960
961	when ex2_get2 =>
962	switch_port_out_rd_en <=rd_ok;
963	fifo_wr_en <= Wr_ok;
964	Ready<='0';
965	packet_received <= '0';
966	dma_rd_request <= '0';
967	dma_wr_request <= '0';
968	Ram_rd<='0';
969	Ram_wr<='0';
970	Ram_data_in<=(others=>'-');
971	barrier_completed <= '0';
972	AppInitReq<='0';
973
974	when ex2_get3 => fifo_wr_en <= '0';
975	Ready<='0';
976	switch_port_out_rd_en <= '0';
977	packet_received <= '1';
978	dma_rd_request <= '1';
979	dma_wr_request <='0';
980	Ram_wr<='0';
981	Ram_rd<='1';
982	AppInitReq<='0';
983	barrier_completed <= '0';
984	--Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
985
986	when ex2_get4 =>
987	Ready<='0';
988	barrier_completed <= '0';
989	switch_port_out_rd_en<='0';
990	fifo_wr_en <= '0';
991	packet_received <= '1';
992	AppInitReq<='0';
993	dma_rd_request <= dma_rd;
994	dma_wr_request <= dma_wr;
995	Ram_rd<=rd_ok;
996	Ram_wr<=wr_ok;
997	Ram_data_in<=data_to_ram; --activer le bit DSending
998
999
1000	when ex2_barrier1 => fifo_wr_en <= '0';
1001	switch_port_out_rd_en <= switch_data_available;
1002	packet_received <= '0';
1003	dma_wr_request <= '0';
1004	dma_rd_request <= '0';
1005	Ram_rd<='0';
1006	Ram_wr<='0';
1007	Ram_data_in<=(others=>'-');
1008	barrier_completed <= '0';
1009	Ready<='0';
1010	AppInitReq<='0';
1011
1012	when ex2_barrier2 => fifo_wr_en <= '0';
1013	Ready<='0';
1014	switch_port_out_rd_en <='0';
1015	packet_received <= '0';
1016	dma_wr_request <= '0';
1017	dma_rd_request <= '0';
1018	Ram_rd<='0';
1019	Ram_wr<='0';
1020	Ram_data_in<=(others=>'-');
1021	barrier_completed <= '0';
1022	AppInitReq<='0';
1023
1024	when ex2_barrier3 => fifo_wr_en <= '0';
1025	switch_port_out_rd_en <='0';
1026	Ready<='0';
1027	packet_received <= '0';
1028	dma_wr_request <= '0';
1029	dma_rd_request <= '0';
1030	Ram_rd<='0';
1031	Ram_wr<='0';
1032	Ram_data_in<=(others=>'-');
1033	barrier_completed <= '1';
1034	AppInitReq<='0';
1035
1036	when ex2_barrier4 => fifo_wr_en <= '0';
1037	switch_port_out_rd_en <='0';
1038	packet_received <= '0';
1039	dma_wr_request <= '0';
1040	dma_rd_request <= '0';
1041	Ram_rd<='0';
1042	Ram_wr<='0';
1043	Ram_data_in<=(others=>'-');
1044	barrier_completed <= '0';
1045	AppInitReq<='0';
1046	Ready<='0';
1047
1048
1049	when ex2_barrier5 => fifo_wr_en <= not(fifo_full);
1050	switch_port_out_rd_en <='0';
1051	packet_received <= '0';
1052	dma_wr_request <= '0';
1053	dma_rd_request <= '0';
1054	Ram_rd<='0';
1055	Ram_wr<='0';
1056	Ram_data_in<=(others=>'-');
1057	barrier_completed <= '0';
1058	AppInitReq<='0';
1059	Ready<='0';
1060
1061	when ex2_barrier6 => fifo_wr_en <= not(fifo_full);
1062	switch_port_out_rd_en <= '0';
1063	packet_received <= '0';
1064	dma_wr_request <= '0';
1065	dma_rd_request <= '0';
1066	Ram_rd<='0';
1067	Ram_wr<='0';
1068	Ram_data_in<=(others=>'-');
1069	barrier_completed <= '0';
1070	AppInitReq<='0';
1071	Ready<='0';
1072
1073	when ex2_barrier7 => fifo_wr_en <= not(fifo_full);
1074	switch_port_out_rd_en <= '0';
1075	packet_received <= '0';
1076	dma_wr_request <= '0';
1077	dma_rd_request <= '0';
1078	Ram_rd<='0';
1079	Ram_wr<='0';
1080	Ram_data_in<=(others=>'-');
1081	barrier_completed <= '0';
1082	AppInitReq<='0';
1083	Ready<='0';
1084
1085	when ex2_spawn => fifo_wr_en <= '0';
1086	switch_port_out_rd_en <= rd_ok;--switch_data_available;
1087	packet_received <= '0';
1088	dma_wr_request <= '0';
1089	dma_rd_request <= '0';
1090	Ram_rd<='0';
1091	Ram_wr<='0';
1092	barrier_completed <= '0';
1093	Ready<='0';
1094	Ram_data_in<=(others =>'-');
1095	AppInitReq<=wr_ok;
1096	when ex2_init1 => fifo_wr_en <= '0';
1097	switch_port_out_rd_en <= rd_ok;--switch_data_available;
1098	packet_received <= '0';
1099	dma_wr_request <= '0';
1100	dma_rd_request <= '0';
1101	Ram_rd<='0';
1102	Ram_wr<='0';
1103	barrier_completed <= '0';
1104	Ready<='0';
1105	Ram_data_in<=(others =>'-');
1106	AppInitReq<=wr_ok;
1107
1108
1109	when ex2_init2 => fifo_wr_en <= '0';
1110	switch_port_out_rd_en <='0';
1111	packet_received <= '0';
1112	dma_wr_request <= '0';
1113	dma_rd_request <= '0';
1114	Ram_rd<='0';
1115	Ram_wr<='0';
1116	barrier_completed <= '0';
1117	Ram_data_in<=(others =>'-');
1118	AppInitReq<= not(AppInitAck);
1119	Ready<='0';
1120
1121	when others => Ready<='1'; -- le module est à nouveau libre
1122	fifo_wr_en <= '0';
1123	switch_port_out_rd_en <= '0';
1124	packet_received <= '0';
1125	dma_wr_request <= '0';
1126	dma_rd_request <= '0';
1127	barrier_completed <= '0';
1128	Ram_data_in<=(others=>'-');
1129	Ram_rd<='0';
1130	Ram_wr<='0';
1131	Ready<='1';
1132	AppInitReq<='0';
1133	end case;
1134
1135	end process;
1136
1137	ex2_fsm_sync:process(clk)
1138
1139	begin
1140	if rising_edge(clk) then
1141	if reset = '1' then
1142	ex2_state <= Ex2_Ready;
1143	ack_state<=ack0; --MAE d'envoie de AR
1144	n<=0;
1145	P_len<=(others=>'0');
1146	else
1147	ex2_state<=next_ex2_state;
1148	ack_state<=next_ack_state; --MAE d'envoie de AR
1149	n<=n_i;
1150	P_len<=P_len_i;
1151	dest_address <= dest_address_i;
1152	Sent_ack<=sent_ack_i;
1153	Instr_ack<=Instr_ack_i;
1154	end if;
1155	end if;
1156	end process ex2_fsm_sync;
1157	snd_ack:process (ack_state,reset,fifo_full,instr_ack)
1158	--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu
1159	begin
1160	-- if rising_edge(clk) then
1161
1162	if reset='1' then
1163	next_ack_state<=ack0;
1164	else
1165	next_ack_state<=ack_state;
1166	case ack_state is
1167	when ack0 =>to_fifo_ack<=(others=>'0');
1168	Wr_ack<='0';
1169	if instr_ack='1' then
1170	next_ack_state<=ack1;
1171	to_fifo_ack <= MPI_ACK & Dest_ack;
1172	wr_ack<='0';
1173	end if;
1174
1175	sent_ack_i<='0';
1176
1177	when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur
1178	-- en empilement dans le fifo
1179	to_fifo_ack <= MPI_ACK & Dest_ack;
1180	next_ack_state <= ack2;
1181	wr_ack<='1';
1182	else
1183	wr_ack<='0';
1184	end if;
1185	sent_ack_i<='0';
1186	when ack2 => if fifo_full = '0' then
1187	to_fifo_ack <= "00000100";--la longueur
1188
1189	next_ack_state <= ack3;
1190	wr_ack<='1';
1191	else --
1192	next_ack_state <= ack2;
1193	wr_ack<='0';
1194
1195	end if;
1196	sent_ack_i<='0';
1197	when ack3 => if fifo_full = '0' then
1198	to_fifo_ack <= "00000000";--
1199	next_ack_state <= ack4;
1200	wr_ack<='1';
1201	else --
1202	next_ack_state <= ack3;
1203	wr_ack<='0';
1204
1205	end if;
1206	sent_ack_i<='0';
1207	when ack4 => if fifo_full = '0' then
1208	to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur
1209	next_ack_state <= ack5;
1210	wr_ack<='1';
1211	sent_ack_i<='0';
1212	else --
1213	next_ack_state <= ack4;
1214	wr_ack<='0';
1215	sent_ack_i<='0';
1216	end if;
1217	when ack5 => if Instr_ack='0' then --dernier pulse
1218	next_ack_state <= ack0;
1219	else
1220	next_ack_state <= ack6;
1221	end if;
1222	wr_ack<='0';
1223	sent_ack_i<='1';
1224	to_fifo_ack<=(others=>'1');
1225	when ack6 => if Instr_ack='0' then
1226	next_ack_state <= ack0;
1227
1228	end if;
1229	wr_ack<='0';
1230	sent_ack_i<='1';
1231	to_fifo_ack<=(others=>'1');
1232	end case;
1233	end if;
1234	--end if;
1235	end process;
1236	end Behavioral;
1237

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