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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd @ 72

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1	----------------------------------------------------------------------------------
2	-- Company: GRIIA - ETIS - LIP6
3	-- Engineer: GAMOM, KIEGAING
4	--
5	-- Create Date: 01:02:10 06/17/2011
6	-- Design Name:
7	-- Module Name: EX2_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- machine a etat qui execute la reception des packet dans le core mpi
13	-- Dependencies:
14	--ss
15	-- Revision: 26/01/2012
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib ;
22	use IEEE.STD_LOGIC_1164.ALL;
23	use IEEE.Numeric_std.ALL;
24	use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use Work.Packet_type.ALL;
26	use NocLib.CoreTypes.all;
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity EX2_FSM is
33
34	generic (
35	pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
36	nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
37	);
38	Port ( clk : in STD_LOGIC;
39	reset : in STD_LOGIC;
40
41	Instruction_en : in std_logic;
42
43	dma_wr_grant : in STD_LOGIC;
44	dma_wr_request : out STD_LOGIC;
45	dma_rd_grant : in STD_LOGIC;
46	dma_rd_request : out STD_LOGIC;
47	ram_rd : out std_logic;
48	ram_wr : out std_logic;
49	ram_address : out std_logic_vector(ADRLEN-1 downto 0);
50	Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
51	Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
52
53	fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
54	fifo_wr_en : out STD_LOGIC;
55	fifo_full : in STD_LOGIC;
56	Rec_Rdy : OUT std_logic;
57	Rec_Data : OUT Typ_PortIO(0 to 3);
58	Rec_Ack : IN std_logic;
59	AppRank : in STD_LOGIC_VECTOR(3 downto 0);
60	AppSize : in STD_LOGIC_VECTOR(3 downto 0);
61	packet_received : out STD_LOGIC;
62	packet_ack : in STD_LOGIC;
63	barrier_completed : out STD_LOGIC;
64	Ready : Out std_logic;
65	AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
66	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
67	Initialized:in std_logic ; -- état de la Lib
68	Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
69	switch_data_available : in STD_LOGIC;
70	switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
71	switch_port_out_rd_en : out STD_LOGIC
72
73
74
75	);
76	end EX2_FSM;
77
78	architecture Behavioral of EX2_FSM is
79	--module pour la lecture des données sur le réseau
80	CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu
81	component Proto_receiv is
82	generic (sizemem : natural := 64);
83	port (
84	clk,reset : in std_logic;
85	fifo_empty,fifo_full : in std_logic;
86	rcv_start : in std_logic; --début de la réception
87	rcv_ack :in std_logic; -- acquittement de la réception
88	rcv_comp : out std_logic; -- fin de la réception
89	pop : out std_logic:='0';
90	fifo_out : in std_logic_vector(Word-1 downto 0);
91	mem :out memory(0 to sizemem-1));
92	end component Proto_receiv;
93
94	COMPONENT SetBit
95	PORT(
96	clk : IN std_logic;
97	reset : IN std_logic;
98	BitMask : IN std_logic_vector(7 downto 0);
99	BitVal : IN std_logic;
100	start : in std_logic;
101	done : out std_logic;
102	dma_wr_grant : IN std_logic;
103	dma_rd_grant : IN std_logic;
104	Ram_data_in : out std_logic_vector(7 downto 0);
105	dma_wr_request : OUT std_logic;
106	dma_rd_request : OUT std_logic;
107	ram_rd : OUT std_logic;
108	ram_wr : OUT std_logic;
109	ram_address : IN std_logic_vector(15 downto 0);
110	Ram_data_out : in std_logic_vector(7 downto 0)
111	);
112	End component SetBit;
113	-- définition du type etat de la machine à etat
114	type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2,
115	fetch_addresses,ex2_spawn,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4,
116	ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3,
117	Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
118	ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy);
119	type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6);
120	type mem32 is array (natural range <>) of std_logic_vector (31 downto 0);
121	signal Next_Ex2_state,ex2_state :fsm_states;
122	signal ack_state,next_ack_state : fsm_ack;
123	-- machine a etat du module
124	signal packet_type : std_logic_vector(3 downto 0);
125	signal P_len_i,P_len : std_logic_vector(Word-1 downto 0);
126	signal barrier_counter : std_logic_vector(3 downto 0);
127	signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0');
128	signal n,n_i : natural range 0 to 15;
129	signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
130	signal data_to_write_fifo : std_logic_vector(Word-1 downto 0);
131	--*******************************************
132	--signaux pour la fonction SetBit
133	signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
134	signal sb_BitVal,sb_start,sb_done : std_logic:='0';
135	signal sb_Ram_data_in : std_logic_vector(7 downto 0);
136	signal sb_dma_wr_request : std_logic;
137	signal sb_dma_rd_request : std_logic;
138	signal sb_ram_rd : std_logic;
139	signal sb_ram_wr : std_logic;
140	signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
141	signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
142	-- deuxième module pour set busy bit
143	signal bu_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
144	signal bu_BitVal,bu_start,bu_done : std_logic:='0';
145	signal bu_Ram_data_in : std_logic_vector(7 downto 0);
146	signal bu_dma_wr_request : std_logic;
147	signal bu_dma_rd_request : std_logic;
148	signal bu_ram_rd : std_logic;
149	signal bu_ram_wr : std_logic;
150	signal bu_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
151	signal bu_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
152	signal Set_Wbusy : std_logic:='0'; --choix du Mux
153	signal b_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
154	signal b_BitVal,b_start,b_done : std_logic:='0';
155	signal b_Ram_data_in : std_logic_vector(7 downto 0);
156	signal b_dma_wr_request : std_logic;
157	signal b_dma_rd_request : std_logic;
158	signal b_ram_rd : std_logic;
159	signal b_ram_wr : std_logic;
160	signal b_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
161	signal b_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
162
163	--*********************************************
164	signal Ex2_on : std_logic:='0';
165	signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
166	signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement
167	signal dest_ack:std_logic_vector(3 downto 0) :=(others=>'0');
168	signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0');
169	signal Result_i : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
170	--signaux pour l'untilisation du composant de réception
171	signal rfifo_empty,rfifo_full:std_logic;
172	signal rcv_start,rcv_comp,rcv_ack:std_logic;
173	signal rpop:std_logic;
174	--signal mem:memory(0 to Msize-1));
175	--jusqu'à 16 Get peuvent être attendus!
176	signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés
177	signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; --
178	signal Rec_WPost, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0');
179	signal Waited_Get : mem32(0 to 15);
180	Signal Rec_Data_i : Typ_PortIO(0 to 3);
181	signal Get_Instr,Put_instr :memory(0 to 8);
182	signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0');
183	signal P_G: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get
184	signal Ptr_Get,Ptr_Get_i : natural range 0 to 15:=0;
185	signal Received_get : std_logic_vector(15 downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu
186	begin
187	ram_address <= dest_address;
188	--fifo_data <= data_to_write_fifo;
189	Result<=Result_i;
190	p_instr_fifo:process(ack_state,data_to_write_fifo,wr_ack,to_fifo_ack,instr_ack)
191	begin
192	if instr_ack='1' then
193	fifo_data<=to_fifo_ack;
194	else
195	fifo_data<=data_to_write_fifo;
196	end if;
197	end process p_instr_fifo;
198
199
200
201	R0:proto_receiv generic map (sizemem =>4)
202	port map (
203	clk=>clk,
204	reset=>reset,
205	rcv_start=>rcv_start,
206	rcv_comp=>rcv_comp,
207	rcv_ack=>rcv_ack,
208	fifo_empty=>rfifo_empty,
209	fifo_full=>rfifo_full,
210	fifo_out=>switch_port_out_data,
211	pop=>rpop,
212	mem=>open
213
214	);
215	--envoie de l'acquittement
216	setbit1:SetBit
217	PORT MAP (
218	clk =>clk,
219	reset =>reset,
220	BitMask =>sb_bitMask,
221	BitVal =>sb_bitval,
222	dma_wr_grant =>dma_wr_grant,
223	dma_rd_grant =>dma_rd_grant,
224	Ram_data_in => sb_Ram_data_in,
225	dma_wr_request =>sb_dma_wr_request,
226	dma_rd_request =>sb_dma_rd_request,
227	ram_rd =>sb_ram_rd,
228	ram_wr =>sb_ram_wr,
229	ram_address =>dest_address,
230	Ram_data_out =>sb_ram_data_out,
231	Start =>sb_start,
232	done =>sb_done
233	);
234	--b_BitVal<=bu_Bitval when Set_Wbusy='1' else Sb_BitVal;
235	--b_BitMask<=bu_BitMask when Set_Wbusy='1' else Sb_BitVal;
236	--b_start<= bu_start when Set_wBusy='1' else sb_start;
237	--b_ram_rd<=bu_ram_rd when Set_Wbusy='1' else Sb_ram_rd;
238	--b_ram_wr<=bu_ram_wr when Set_Wbusy='1' else Sb_ram_wr;
239	--b_dma_ram_request_rd<=bu__dma_ram_request_rd when Set_Wbusy='1' else Sb_dma_ram_request_rd;
240	--b_dma_ram_request_wr<=bu_dma_ram_request_wr when Set_Wbusy='1' else Sb_dma_ram_request_wr;
241	-- processus de transistion entre les etats
242	ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized,
243	switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len,
244	sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy)
245	variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
246	variable tempval : std_logic_vector(Word-1 downto 0);
247	variable n_e,i:natural range 0 to 15 :=0;
248	procedure read_nocdat_fsm(sdata_avail: std_logic;
249	signal rd,wr:out std_logic;
250	signal Plen : inout std_logic_vector(Word-1 downto 0);
251	variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is
252	--lit la suite des données qui sont dans le NoC et identifie le paramètre important
253	begin
254	if n_e<3 then
255	wr<='0';
256	if sdata_avail='1' then
257	n:=n_e+1;
258	rd<='1';
259	plen <=plen-1;
260	else
261	rd<='0';
262	end if;
263	--result_i<=(others=>'0');
264	elsif n_e=3 then
265	if sdata_avail='1' then
266	n:=n_e+1;
267	rd<='0';
268	--P_len <=P_len_i -1;
269	--data_to_ram<=sportdout;
270	--Result_i<=sport_out_data;
271	else
272	rd<='0';
273	end if;
274	end if;
275	end procedure;
276
277	begin
278
279	Next_Ex2_state <= Ex2_state;
280	Ex2_on<='0';
281	barrier_counter <= "0000";
282	--n_i<=n;
283	dest_address_i<=dest_address;
284	-- else
285	Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
286	n_i<=n; --valeur par défaut de n_i
287	P_len_i<=P_len;
288	case ex2_state is
289	when Ex2_ready => if Instruction_en='1' then
290	Next_Ex2_state <= fetch_packet_type;
291	end if;
292	rd_ok<='0';wr_ok<='0';
293	when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1'
294	Next_Ex2_state <= decode_packet_type;
295	packet_type<=switch_port_out_data(7 downto 4);
296	Dest_ack<=switch_port_out_data(3 downto 0);
297	Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue !
298	rd_ok<='1';
299	else
300	Next_Ex2_state <= Ex2_Ready;
301	rd_ok<='0';
302	end if;
303	n_i<=0;
304	when decode_packet_type => rd_ok<='0';
305	if switch_data_available ='0' then
306	Next_Ex2_state <= decode_packet_type;
307	else
308	rd_ok<='1';
309	Rec_Data_i(1)<=switch_port_out_data-2;
310	if packet_type = MPI_PUT then
311	P_len_i <= switch_port_out_data - 2;
312	n_i<=0;
313
314	Next_Ex2_state <= decode_packet_type2;
315	elsif packet_type = MPI_GET then
316	P_len_i <=switch_port_out_data-2;
317	Next_Ex2_state <= decode_packet_type2;
318	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
319	P_len_i <= switch_port_out_data;
320	n_i<=0;
321	Next_Ex2_state <= ex2_barrier1;
322	elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
323	n_i<=0;
324	wr_ok<='0';
325	--rd_ok<='1';
326	P_len_i <= switch_port_out_data-2;
327	Rec_Data_i(1)<=switch_port_out_data;
328	Next_Ex2_state <= ex2_init1;
329	elsif packet_type = MPI_ACK then
330	n_i<=0;
331	wr_ok<='0';
332	rd_ok<='0';
333	P_len_i <= switch_port_out_data-2;
334	Next_Ex2_state <= ex2_ack1;
335	elsif packet_type = MPI_WIN_SYNC then
336	n_i<=0;
337	wr_ok<='0';
338	rd_ok<='0';
339	P_len_i <= switch_port_out_data-2;
340	Next_Ex2_state <= ex2_Wsync;
341	elsif packet_type = MPI_SPAWN then
342	Next_Ex2_state <= ex2_spawn;
343	else
344	Next_Ex2_state <= decode_packet_type;
345	rd_ok<='0';
346	end if;
347	end if;
348	when decode_packet_type2 => if packet_type = MPI_PUT then
349	Next_Ex2_state <= fetch_addresses;
350	else
351	Next_Ex2_state <= ex2_get1;
352	end if;
353	when fetch_addresses => if n=0 then
354	if switch_data_available = '1' then
355	dest_address_i(15 downto 8) <= switch_port_out_data;
356	Rec_data_i(2)<=switch_port_out_data;
357	n_i <= n + 1;
358	rd_ok<='1';
359	else
360	rd_ok<='0';
361	end if;
362	elsif n=1 then
363	if switch_data_available = '1' then
364	dest_address_i(Word-1 downto 0) <= switch_port_out_data;
365	Rec_data_i(3)<=switch_port_out_data;
366	P_len_i <= P_len - 2;
367	Next_Ex2_state <= ex2_put1;
368	n_i<=0;
369	rd_ok<='1';
370	else
371	rd_ok<='0';
372	Next_Ex2_state <= fetch_addresses;
373	end if;
374	end if;
375	when Ex2_ack2 =>if unsigned(p_len)>0 then
376	If Dma_rd_grant='1' then
377	if n=0 then
378	n_i<=n+1; --cycle d'attente pour la RAM
379	elsif n=1 then
380	dest_address_i <= dest_address+1;
381	n_i<=2;
382	elsif n>=2 then
383
384	--creer un délai sur ces signaux par rapport à src_adress
385
386	n_i<=n+1;
387	rd_ok<='1';
388	-- if n>1 then
389	dest_address_i <= dest_address+1;
390	p_len_i <= p_len - 1;
391	--end if;
392	Get_Instr(n-2)<=Ram_data_out; --deux cycles de retard
393	Next_ex2_state <= ex2_ack2;
394	end if;
395	end if;
396	dma_rd<='1';
397	rd_ok<='1';
398	else
399	if P_G=1 then
400	dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
401	else
402	dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
403	Waited_get(ptr_get)(7 downto 0)<=Get_instr(0); --id
404	Waited_get(ptr_get)(15 downto 8)<=Get_instr(1); --longueur
405	Waited_get(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas
406	Waited_get(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut
407	RGET<='1';
408
409	Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter
410	end if;
411	Next_ex2_state <= ex2_ack3;
412	n_i<=0; --suite du process ack
413	rd_ok<='0';
414	dma_rd<='0';
415	end if;
416	when ex2_ack1 => rd_ok<='0';
417	if n<2 then --réception de l'acquittement.
418	n_e:=n_i;
419	read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
420	n_i<=n_e;
421	elsif n=2 then
422	if switch_data_available='1' then
423	n_i<=n+1;
424	rd_ok<='1';
425
426	data_to_ram<=switch_port_out_data;
427	Result_i<=switch_port_out_data;
428	end if;
429
430	elsif n=3 then
431	n_i<=n+1;P_G<=0;
432	if data_to_ram(7 downto 4)=MPI_PUT then
433	Result_i<=data_to_ram;
434	dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16));
435	wr_ok<='1';
436	P_G<=1; --put ou get
437	P_len_i<=x"06"; --longueur de l'entête à parcourir
438	elsif data_to_ram(7 downto 4)=MPI_GET then
439	Result_i<=data_to_ram;
440	wr_ok<='1'; --
441	P_G<=2; --put get
442	P_len_i<=x"06";--taille de l'instruction en mémoire
443	dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16));
444	elsif data_to_ram(7 downto 4)=MPI_SPAWN then
445	Result_i<=data_to_ram;
446	wr_ok<='1'; --
447	dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16));
448	elsif data_to_ram(7 downto 4)=MPI_INIT then
449	Result_i<=data_to_ram;
450	dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16));
451	wr_ok<='1'; --
452	--
453	else
454	Result_i<="00000000";
455	wr_ok<='0'; --
456	n_i<=n; --code inconnu !
457	end if;
458	elsif n=4 then
459	if P_G=1 or P_G=2 then
460	Next_ex2_state<=ex2_ack2;
461	else
462	Next_ex2_state<=ex2_ack3;
463	end if;
464	n_i<=0;
465	end if;
466
467	when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction
468	sb_start<='1';
469	sb_bitMask<=x"20";--cinquième bit à un
470	sb_bitval<='1';
471	if sb_done='1' then
472	n_i<=1;
473	sb_start<='0';
474	sb_bitval<='0';
475	end if;
476	elsif n=1 then
477	Next_Ex2_state<=Ex2_Ready;
478	n_i<=0;
479	end if;
480
481	when ex2_Wsync => rd_ok<='0';
482	if n<2 then --réception de la synchronisation.
483	n_e:=n_i;
484	read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
485	n_i<=n_e;
486	elsif n=2 then
487	if switch_data_available='1' then
488	n_i<=n+1;
489	rd_ok<='1';
490
491	data_to_ram<=switch_port_out_data;
492	Result_i<=switch_port_out_data;
493	end if;
494
495	elsif n=3 then
496	n_i<=n+1;P_G<=0;
497	if data_to_ram(7 downto 4)=SYNC_WSTART then
498	Result_i<=data_to_ram;
499	dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
500	wr_ok<='1';
501	P_G<=1; --put ou get
502	P_len_i<=x"06"; --longueur de l'entête à parcourir
503	elsif data_to_ram(7 downto 4)=SYNC_WPOST then
504	Result_i<=data_to_ram;
505	wr_ok<='1'; --
506	P_G<=2; --put get
507	P_len_i<=x"06";--taille de l'instruction en mémoire
508	dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
509	elsif data_to_ram(7 downto 4)=SYNC_WWAIT then
510	Result_i<=data_to_ram;
511	wr_ok<='1'; --
512	dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16));
513	elsif data_to_ram(7 downto 4)=SYNC_WCOMP then
514	Result_i<=data_to_ram;
515	dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));
516	wr_ok<='1'; --
517	Next_Ex2_State<=Ex2_WCOMP;
518	n_i<=0;
519	else
520	Result_i<="00000000";
521	wr_ok<='0'; --
522	n_i<=n; --code inconnu !
523	end if;
524
525	end if;
526	when Ex2_Wcomp => dma_rd<='1';
527	rd_ok<='1';
528	If Dma_rd_grant='1' then
529	if n=0 then
530	n_i<=n+1; --cycle d'attente pour la RAM
531	elsif n=1 then
532	dest_address_i <= dest_address+1;
533	n_i<=2;
534	elsif n=2 then
535
536	--creer un délai sur ces signaux par rapport à dest_adress
537	n_i<=n+1;
538	rd_ok<='1';
539	dest_address_i <= dest_address;
540	GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard
541	elsif n=3 then
542	GPost_i(15 downto 8)<=Ram_data_out;
543	n_i<=n+1;
544	rd_ok<='1';
545	dma_rd<='1';
546	elsif n=4 then
547	GPost_i(15 downto 8)<=Ram_data_out;
548	rd_ok<='0';
549	dma_rd<='1';
550	n_i<=0;
551	Next_ex2_state <= ex2_set_busy;
552	end if;
553	end if;
554
555	when ex2_init1 => if n<2 then -- execution du mpi Init
556	wr_ok<='0';
557	if switch_data_available='1' then
558	n_i<=n+1;
559	rd_ok<='1';
560	P_len_i <=P_len-1;
561	Rec_Data_i(n+2)<=switch_port_out_data;
562	data_to_ram<=switch_port_out_data;
563	Result_i<=switch_port_out_data;
564	else
565	rd_ok<='0';
566	n_i<=n;
567	end if;
568	result_i<=(others=>'0');
569	elsif n=2 then
570	--if switch_data_available='1' then
571	n_i<=n+1;
572	rd_ok<='0';
573	-- --P_len <=P_len -1;
574	--
575	-- else
576	-- rd_ok<='0';
577	-- end if;
578	elsif n=3 then
579	rd_ok<='0'; -- normalement plus rien à lire
580	n_i<=n+1;
581	if Initialized='1' then
582	if data_to_ram(7 downto 4)=INIT_SEEKMAIN then
583	Result_i<=data_to_ram;
584	wr_ok<='1'; --permet d'activer Init de Ex_4
585	elsif data_to_ram(7 downto 4)=INIT_STAT then
586	Result_i<=data_to_ram;
587	wr_ok<='1'; --permet d'activer Init de Ex_4
588	elsif data_to_ram(7 downto 4)=INIT_REGISTER then
589	Result_i<=data_to_ram;
590	wr_ok<='1'; --permet d'activer Init de Ex_4
591	elsif data_to_ram(7 downto 4)=INIT_SPAWN then
592	Result_i<=data_to_ram;
593	wr_ok<='1'; --permet d'activer Init de Ex_4
594	-- il faut mettre à jour l'état de Spawn
595	else
596	Result_i<="00000000";
597	wr_ok<='0'; --permet d'activer Init de Ex_4
598	end if;
599	end if;
600	elsif n=4 then
601	n_i<=n+1;
602	elsif n=5 then
603	if p_len=0 then
604	Next_Ex2_state<=ex2_init2;
605	rd_ok<='0';
606	else
607	p_len_i <=p_len -1;
608	rd_ok<='1'; --vider le tampon de lecture pour ce paquet !
609	end if;
610
611	end if;
612	when ex2_init2=> if n=5 then
613	if AppInitAck='1' then
614	n_i<=n+1;
615	Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init
616	end if;
617	elsif n=6 then
618	Next_Ex2_state<=Ex2_Ready;
619	n_i<=0;
620	end if;
621
622	when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch
623	wr_ok<='0';
624	if n=0 then
625	instr_ack_i<='1'; --activer l'envoie de l'accusé de réception
626	data_to_write_fifo<=to_fifo_ack;
627	wr_ok<=wr_ack;
628	if sent_ack='1' then
629	n_i<=1;
630	instr_ack_i<='0';
631	end if;
632
633	elsif n=1 then
634	if dma_wr_grant = '1' then
635	Next_Ex2_state <= ex2_put2;
636	data_to_ram<=switch_port_out_data;
637	rd_ok<='0';
638	n_i<=0;
639	delai:=0;
640	else
641	Next_Ex2_state <= ex2_put1;
642	end if;
643	end if;
644	when ex2_put2 => rd_ok<='0';
645	n_i<=1;
646	i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0)));
647	Rec_WPost(i)<='1'; --indiquer que ce port a emis des données !
648	if unsigned( P_len) > 0 then
649
650	if switch_data_available = '1' and delai=0 then
651	delai:=1; --une donné lue
652	P_len_i <= P_len - 1;
653	Next_Ex2_state <= ex2_put2;
654	rd_ok<='1';
655	data_to_ram<=switch_port_out_data;
656	end if;
657	if dma_wr_grant='1' and delai=1 then
658	-- if n=1 then
659	wr_ok<='1';
660	dest_address_i <= dest_address + 1;
661	delai:=0;--une donnée écrite
662	-- else
663	-- dest_address_i <= dest_address ;
664	-- end if;
665	--if delai=1 then
666	--data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
667	--end if;
668
669	else
670	dest_address_i<=dest_address;
671	wr_ok<='0';
672	n_i<=0;
673	end if;
674
675	Next_Ex2_state <= ex2_put2;
676
677	else
678	rd_ok<='0';
679
680
681	if dma_wr_grant='1' and n=1 then
682
683	Next_Ex2_state <= ex2_put3;
684	Wr_ok<='0';
685	n_i<=0;
686	end if;
687	end if;
688
689	when ex2_put3 => if dma_rd_grant='1' then
690	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
691	Next_Ex2_state <= ex2_put4;
692	n_i<=0;
693	rd_ok<='1';
694	wr_ok<='0';
695	end if;
696
697	when ex2_put4 => if n<=4 and n>0 then
698
699	dma_wr<='1'; --demander un accès exclusif au bus
700	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
701	else
702	dma_wr<='0';
703	dma_rd<='0';
704	end if;
705	if n=0 then
706	if RGET='1' then
707	for i in 1 to Ptr_get loop
708	if waited_get(i-1)(3 downto 0)=rec_data_i(0)(3 downto 0) and
709	waited_get(i-1)(15 downto 8)=(rec_data_i(1)-2) and
710	waited_get(i-1)(23 downto 16)=rec_data_i(2) and
711	waited_get(i-1)(31 downto 24)=rec_data_i(3) then
712	if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data_i(0)(7 downto 4)=MPI_PUT) then
713	received_get(i-1)<='1';
714	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
715	end if;
716	else
717
718	end if;
719	end loop;
720	end if;
721
722	n_i<=n+1;
723	rd_ok<='1';
724	wr_ok<='0';
725
726	elsif n=1 then
727
728	if dma_rd_grant='1' then
729	if RGET='1' then --si on est en mode attente d'un Get
730	RGET<='0'; --Supposons tous les Gets reçus !
731	test_wcomp:for i in 1 to Ptr_get loop --Tous les Get reçus ?
732	if received_get(i-1)='0' then
733	RGET<='1'; --Non !
734	end if;
735	end loop;
736
737	end if;
738	n_i<=n+1;
739	else
740	rd_ok<='1';
741	wr_ok<='0';
742	end if;
743	elsif n=2 then
744	if dma_rd_grant='1' and dma_wr_grant='1' then
745	n_i<=n+1;
746	tempval:=Ram_data_out;
747	tempval(4):='1'; --SET du bit DReceived
748	--si get ack est détecté
749	--tempval(6):=WBusy or RGET; -- Bit 6 Busy=0 si dernier get reçu !!
750	data_to_ram<=tempval;
751	rd_ok<='0';
752	wr_ok<='1';
753	else
754	rd_ok<='1';
755	wr_ok<='0';
756	n_i<=0;
757	end if;
758	elsif n=3 then
759	if dma_wr_grant='1' then
760	rd_ok<='0';
761	wr_ok<='1';
762	n_i<=n+1;
763	end if;
764	elsif n=4 then
765	if dma_wr_grant='1' then
766	rd_ok<='0';
767	wr_ok<='1';
768
769	n_i<=5;
770	end if;
771	elsif n=5 then
772	Next_Ex2_state <= ex2_set_busy;
773	n_i<=0;
774	rd_ok<='0';
775	wr_ok<='0';
776	end if;
777
778
779
780	-- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
781	when ex2_put5 =>
782	Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put
783
784	when ex2_spawn =>
785
786	if n<2 then
787	n_e:=n;
788	read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
789	n_i<=n_e;
790	elsif n=2 then
791	Result_i<=Switch_port_out_data;
792	Data_to_ram<=Switch_port_out_data;
793	n_i<=n+1;
794	elsif n=3 then
795	if data_to_ram(7 downto 4)=SPAWN_LOAD then
796	Result_i<=data_to_ram;
797	wr_ok<='1'; --permet d'activer Init de Ex_4
798	elsif data_to_ram(7 downto 4)=SPAWN_ERR then
799	Result_i<=data_to_ram;
800	wr_ok<='0'; --permet d'activer Init de Ex_4
801	else
802	Result_i<=(others=>'0');
803
804	end if;
805	n_i<=n+1;
806	elsif n=4 then
807	if AppInitAck='1' then
808	wr_ok<='1';
809	rd_ok<='0';
810	n_i<=n+1;
811	end if;
812	elsif n=5 then
813	wr_ok<='0';
814	rd_ok<='0';
815	n_i<=0;
816	Next_Ex2_state <=Ex2_Ready;
817	end if;
818
819	when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch
820	--ack_state<=next_ack_state; --MAE d'envoie de AR
821	if n=0 then
822	instr_ack_i<='1'; --activer l'envoie de l'accusé de réception
823	data_to_write_fifo<=to_fifo_ack;
824	wr_ok<=wr_ack;
825	if sent_ack='1' then
826	n_i<=1;
827	instr_ack_i<='0';
828	wr_ok<='0';
829	--if switch_data_available='1' then
830	rd_ok<='0';--
831	--P_len<=P_len-1;
832	--end if;
833	end if;
834
835	elsif n=1 then
836	if switch_data_available='1' then
837	if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo
838	data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put
839	wr_ok<='1';
840	rd_ok<='1'; --autoriser la lecture du crossbar
841	P_len_i<=P_len-1;
842	n_i<=n+1;
843	else
844	Wr_ok<='0';
845	Rd_ok<='0';
846	end if;
847	else
848	Wr_ok<='0';
849	rd_ok<='0';
850	end if;
851	elsif n=2 then
852	if switch_data_available='1' then
853	if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo
854	--data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put
855	--P_len_i <= P_len-1;--le nombre d'octet qui restent à copier
856	Next_Ex2_state <= ex2_get2;
857	wr_ok<='0';
858	rd_ok<='0'; --autoriser la lecture du crossbar
859	n_i<=0;
860	else
861	rd_ok<='0';
862	wr_ok<='0';
863	end if;
864	else
865	rd_ok<='0';
866	wr_ok<='0';
867	end if;
868	end if;
869	when ex2_get2 => if P_len>0 then
870	if fifo_full = '0' and switch_data_available ='1' then
871	data_to_write_fifo <= switch_port_out_data;--la longueur initiale du GET
872	p_len_i <= P_len - 1;
873	Next_Ex2_state <= ex2_get2;
874	wr_ok<='1';
875	Rd_ok<='1';
876	elsE
877
878	wr_ok<='0';
879	Rd_ok<='0';
880	END IF;
881	else
882	if n=0 then
883	if fifo_full='0' then
884	wr_ok<='0';--une impulsion en plus
885	n_i<=n+1;
886	Next_Ex2_state <= ex2_get2;
887	else
888	wr_ok<='0';
889	end if;
890
891	else
892	Next_Ex2_state <= ex2_get3;
893	n_i<=0;
894	wr_ok<='0';
895	end if;
896	rd_ok<='0';
897	end if;
898	i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0)));
899	Rec_WPost(i)<='1'; --indiquer que ce port a emis des données !
900
901	--préparer en avance l'adresse de lecture/écriture
902	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
903	when ex2_get3 => wr_ok<='0';
904	if dma_rd_grant='1' then -- fin du mpi_get
905	Next_Ex2_state <= ex2_get4;
906	n_i<=0;
907	--activer le bit sending du registre de transfert
908	else
909	Next_Ex2_state <= ex2_get3;
910	end if;
911
912	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
913	when ex2_get4 => if n <4 then
914
915	dma_wr<='1'; --demander un accès exclusif au bus
916	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
917	else
918	dma_wr<='0';
919	dma_rd<='0';
920	end if;
921	if n=0 then
922	if dma_rd_grant='1' then
923	n_i<=n+1;
924
925	end if;
926	rd_ok<='1';
927	wr_ok<='0';
928	elsif n=1 then
929	if dma_rd_grant='1' then
930	n_i<=n+1;
931
932	end if;
933	rd_ok<='1';
934	wr_ok<='0';
935
936	elsif n=2 then
937	if dma_rd_grant='1' and dma_wr_grant='1' then
938	n_i<=n+1;
939	tempval:=Ram_data_out;
940	tempval(2):='1'; --mise à 1 du Bit DSending
941	--tempval(5):='0'; --Mise à 0 du Bit Sent
942	data_to_ram<=tempval;
943	rd_ok<='1';
944	wr_ok<='0';
945	else
946	rd_ok<='1';
947	wr_ok<='0';
948	n_i<=0;
949	end if;
950
951	elsif n=3 then
952	if dma_wr_grant = '1' then
953	n_i<=n+1;
954	rd_ok<='0';
955	wr_ok<='1';
956	end if;
957	elsif n=4 then
958	if dma_wr_grant = '1' then
959	n_i<=0;
960	Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get
961	else
962	rd_ok<='0';
963	wr_ok<='1';
964	--n<=n-1;
965	end if;
966	end if;
967
968
969	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
970	when ex2_Set_Busy => if n=0 then --set busy bit of the instruction
971	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
972	n_i<=1;
973	if Gpost>0 then
974	if (rec_wpost=gpost) and RGET='0' then
975	Wbusy<='0';
976	else
977	Wbusy<='1';
978	end if;
979	else
980	n_i<=2;
981	end if;
982	if RGET='1' then
983	WBusy<='1';
984	end if;
985	elsif n=1 then
986	sb_start<='1';
987	sb_bitMask<=x"40";--6e bit à 1
988	sb_bitval<=WBusy;
989	if sb_done='1' then
990	n_i<=2;
991	sb_start<='0';
992	sb_bitval<='0';
993	end if;
994	elsif n=2 then
995	Next_Ex2_state<=Ex2_Ready;
996	n_i<=0;
997	end if;
998	-- execution du barrier
999	when ex2_barrier1 => if switch_data_available = '1' then
1000	pading_data <= switch_port_out_data;
1001	Next_Ex2_state <= ex2_barrier2;
1002	else
1003	Next_Ex2_state <= ex2_barrier1;
1004	end if;
1005	when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then
1006	barrier_counter <= barrier_counter + 1;
1007	Next_Ex2_state <= ex2_barrier4;
1008	else
1009	Next_Ex2_state <= ex2_barrier3;
1010	end if;
1011	when ex2_barrier3 => if n < 10 then
1012	n_i<= n + 1;
1013	Next_Ex2_state <= ex2_barrier3;
1014	else
1015	Next_Ex2_state <= Ex2_Ready;
1016	end if;
1017	when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED
1018	data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000";
1019	Next_Ex2_state <= ex2_barrier5;
1020	else
1021	Next_Ex2_state <= Ex2_Ready;
1022	end if;
1023	when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED
1024	data_to_write_fifo <= "00000011";
1025	Next_Ex2_state <= ex2_barrier6;
1026	else
1027	Next_Ex2_state <= ex2_barrier5;
1028	end if;
1029	when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
1030	data_to_write_fifo <= "00000000";
1031	Next_Ex2_state <= ex2_barrier7;
1032	else
1033	Next_Ex2_state <= ex2_barrier6;
1034	end if;
1035	when ex2_barrier7 => if fifo_full = '0' then
1036	barrier_counter <= "0000";
1037	Next_Ex2_state <= Ex2_Ready;
1038	else
1039	Next_Ex2_state <= ex2_barrier7;
1040	end if;
1041
1042	when others => Next_Ex2_state <= Ex2_Ready;
1043	end case;
1044
1045	end process;
1046
1047	-- sortie de la machine à etat
1048	--
1049	ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,
1050	switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,n)
1051	variable transact : std_logic_vector(Word-1 downto 0);
1052	begin
1053	-- code fonctionnel
1054	case Ex2_state is
1055	when Ex2_Ready => fifo_wr_en <= '0';
1056	switch_port_out_rd_en <= '0';
1057	packet_received <= '0';
1058	dma_wr_request <= '0';
1059	dma_rd_request <= '0';
1060	barrier_completed <= '0';
1061	Ram_data_in<=(others=>'0');
1062	Ram_rd<='0';
1063	Ram_wr<='0';
1064	Ready<='1';
1065	AppInitReq<='0';
1066	when fetch_packet_type => fifo_wr_en <= '0';
1067	switch_port_out_rd_en <= rd_ok;
1068	packet_received <= '0';
1069	dma_wr_request <= '0';
1070	dma_rd_request <= '0';
1071	barrier_completed <= '0';
1072	Ram_data_in<=(others=>'0');
1073	Ram_rd<='0';
1074	Ram_wr<='0';
1075	Ready<='0';
1076	AppInitReq<='0';
1077
1078
1079	when decode_packet_type => fifo_wr_en <= '0';
1080	switch_port_out_rd_en <= rd_ok;
1081	packet_received <= '0';
1082	dma_wr_request <= '0';
1083	dma_rd_request <= '0';
1084	Ram_rd<='0';
1085	Ram_wr<='0';
1086	Ram_data_in<=(others=>'0');
1087	barrier_completed <= '0';
1088	AppInitReq<='0';
1089	Ready<='0';
1090
1091	when decode_packet_type2 => fifo_wr_en <= '0';
1092	switch_port_out_rd_en <= '0';
1093	packet_received <= '0';
1094	dma_wr_request <= '0';
1095	dma_rd_request <= '0';
1096	Ram_rd<='0';
1097	Ram_wr<='0';
1098	Ram_data_in<=(others=>'0');
1099	barrier_completed <= '0';
1100	AppInitReq<='0';
1101	Ready<='0';
1102	when fetch_addresses => fifo_wr_en <= '0';
1103	switch_port_out_rd_en <= rd_ok;
1104	packet_received <= '0';
1105	dma_wr_request <= '0';
1106	dma_rd_request <= '0';
1107	Ram_rd<='0';
1108	Ram_wr<='0';
1109	Ram_data_in<=(others=>'0');
1110	barrier_completed <= '0';
1111	AppInitReq<='0';
1112	Ready<='0';
1113	when ex2_ack1 \|ex2_Wsync =>
1114	Ready<='0';
1115	switch_port_out_rd_en<=rd_ok;
1116	fifo_wr_en <= '0';
1117	packet_received <= '0';
1118	AppInitReq<='0';
1119	barrier_completed <= '0';
1120	dma_rd_request <= sb_dma_rd_request;
1121	dma_wr_request <= sb_dma_wr_request;
1122	Ram_rd<=sb_ram_rd;
1123	Ram_wr<=sb_ram_wr;
1124	sb_ram_data_out<=Ram_data_out;
1125	Ram_data_in<=sb_ram_data_in;
1126	when ex2_ack2\|Ex2_WCOMP =>
1127	Ready<='0';
1128	switch_port_out_rd_en<='0';
1129	fifo_wr_en <= '0';
1130	packet_received <= '0';
1131	AppInitReq<='0';
1132	barrier_completed <= '0';
1133	dma_rd_request <= dma_rd;
1134	dma_wr_request <= '0';
1135	Ram_rd<=rd_ok;
1136	Ram_wr<='0';
1137	when ex2_ack3 =>
1138	Ready<='0';
1139	switch_port_out_rd_en<=rd_ok;
1140	fifo_wr_en <= '0';
1141	packet_received <= '0';
1142	AppInitReq<='0';
1143	barrier_completed <= '0';
1144	dma_rd_request <= sb_dma_rd_request;
1145	dma_wr_request <= sb_dma_wr_request;
1146	Ram_rd<=sb_ram_rd;
1147	Ram_wr<=sb_ram_wr;
1148	sb_ram_data_out<=Ram_data_out;
1149	Ram_data_in<=sb_ram_data_in;
1150	when ex2_put1 => fifo_wr_en <= wr_ok;
1151	switch_port_out_rd_en <= '0';
1152	packet_received <= '0';
1153	dma_wr_request <= '1';
1154	dma_rd_request <= '0';
1155	Ram_rd<='0';
1156	Ram_wr<='0';
1157	Ram_data_in<=(others=>'0');
1158	barrier_completed <= '0';
1159	AppInitReq<='0';
1160	Ready<='0';
1161
1162	when ex2_put2 => Ready<='0';
1163	fifo_wr_en <= '0';
1164	switch_port_out_rd_en <=rd_ok;
1165
1166	if rd_ok = '1' then
1167
1168	Ram_data_in<=switch_port_out_data;
1169	else
1170	Ram_data_in<=data_to_ram;
1171	end if;
1172	Ram_wr<=wr_ok;
1173	Ram_rd<='0';
1174	packet_received <= '0';
1175	dma_rd_request <= '0';
1176	dma_wr_request <= '1';
1177	AppInitReq<='0';
1178	barrier_completed <= '0';
1179	when ex2_put3 => Ready<='0';
1180	fifo_wr_en <= '0';
1181	switch_port_out_rd_en <='0';
1182	--ne pas corrompre le contenu de la RAM
1183	--Ram_data_in<=data_to_ram;
1184	Ram_wr<='0';
1185	Ram_rd<='1';
1186	packet_received <= '0';
1187	dma_rd_request <= '1';
1188	dma_wr_request <= '0';
1189	AppInitReq<='0';
1190	barrier_completed <= '0';
1191
1192
1193	when ex2_put4 => fifo_wr_en <= '0';
1194	Ready<='0';
1195	switch_port_out_rd_en <= '0';
1196	packet_received <= '1';
1197	dma_rd_request <= dma_rd;
1198	dma_wr_request <=dma_wr;
1199	Ram_wr<=wr_ok;
1200	Ram_rd<=rd_ok;
1201	AppInitReq<='0';
1202	barrier_completed <= '0';
1203	Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution
1204
1205	when ex2_put5 =>
1206	Ready<='0';
1207	switch_port_out_rd_en<='0';
1208	fifo_wr_en <= '0';
1209	packet_received <= '1';
1210	AppInitReq<='0';
1211	barrier_completed <= '0';
1212	dma_rd_request <= dma_rd;
1213	dma_wr_request <= dma_wr;
1214	Ram_rd<=rd_ok;
1215	Ram_wr<=wr_ok;
1216	Ram_data_in<=data_to_ram;
1217	--Result <=(1=>'1',others=>'0'); --put completed
1218
1219	when ex2_get1=> fifo_wr_en <= wr_ok;
1220	switch_port_out_rd_en <= rd_ok;
1221	packet_received <= '0';
1222	dma_wr_request <= '0';
1223	dma_rd_request <= '0';
1224	Ram_rd<='0';
1225	Ram_wr<='0';
1226	Ram_data_in<=(others=>'0');
1227	barrier_completed <= '0';
1228	AppInitReq<='0';
1229	Ready<='0';
1230
1231	when ex2_get2 =>
1232	switch_port_out_rd_en <=rd_ok;
1233	fifo_wr_en <= Wr_ok;
1234	Ready<='0';
1235	packet_received <= '0';
1236	dma_rd_request <= '0';
1237	dma_wr_request <= '0';
1238	Ram_rd<='0';
1239	Ram_wr<='0';
1240	Ram_data_in<=(others=>'0');
1241	barrier_completed <= '0';
1242	AppInitReq<='0';
1243
1244	when ex2_get3 => fifo_wr_en <= '0';
1245	Ready<='0';
1246	switch_port_out_rd_en <= '0';
1247	packet_received <= '1';
1248	dma_rd_request <= '1';
1249	dma_wr_request <='0';
1250	Ram_wr<='0';
1251	Ram_rd<='1';
1252	AppInitReq<='0';
1253	barrier_completed <= '0';
1254	--Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
1255
1256	when ex2_get4 =>
1257	Ready<='0';
1258	barrier_completed <= '0';
1259	switch_port_out_rd_en<='0';
1260	fifo_wr_en <= '0';
1261	packet_received <= '1';
1262	AppInitReq<='0';
1263	dma_rd_request <= dma_rd;
1264	dma_wr_request <= dma_wr;
1265	Ram_rd<=rd_ok;
1266	Ram_wr<=wr_ok;
1267	Ram_data_in<=data_to_ram; --activer le bit DSending
1268
1269
1270	when ex2_barrier1 => fifo_wr_en <= '0';
1271	switch_port_out_rd_en <= switch_data_available;
1272	packet_received <= '0';
1273	dma_wr_request <= '0';
1274	dma_rd_request <= '0';
1275	Ram_rd<='0';
1276	Ram_wr<='0';
1277	Ram_data_in<=(others=>'0');
1278	barrier_completed <= '0';
1279	Ready<='0';
1280	AppInitReq<='0';
1281
1282	when ex2_barrier2 => fifo_wr_en <= '0';
1283	Ready<='0';
1284	switch_port_out_rd_en <='0';
1285	packet_received <= '0';
1286	dma_wr_request <= '0';
1287	dma_rd_request <= '0';
1288	Ram_rd<='0';
1289	Ram_wr<='0';
1290	Ram_data_in<=(others=>'0');
1291	barrier_completed <= '0';
1292	AppInitReq<='0';
1293
1294	when ex2_barrier3 => fifo_wr_en <= '0';
1295	switch_port_out_rd_en <='0';
1296	Ready<='0';
1297	packet_received <= '0';
1298	dma_wr_request <= '0';
1299	dma_rd_request <= '0';
1300	Ram_rd<='0';
1301	Ram_wr<='0';
1302	Ram_data_in<=(others=>'0');
1303	barrier_completed <= '1';
1304	AppInitReq<='0';
1305
1306	when ex2_barrier4 => fifo_wr_en <= '0';
1307	switch_port_out_rd_en <='0';
1308	packet_received <= '0';
1309	dma_wr_request <= '0';
1310	dma_rd_request <= '0';
1311	Ram_rd<='0';
1312	Ram_wr<='0';
1313	Ram_data_in<=(others=>'0');
1314	barrier_completed <= '0';
1315	AppInitReq<='0';
1316	Ready<='0';
1317
1318
1319	when ex2_barrier5 => fifo_wr_en <= not(fifo_full);
1320	switch_port_out_rd_en <='0';
1321	packet_received <= '0';
1322	dma_wr_request <= '0';
1323	dma_rd_request <= '0';
1324	Ram_rd<='0';
1325	Ram_wr<='0';
1326	Ram_data_in<=(others=>'0');
1327	barrier_completed <= '0';
1328	AppInitReq<='0';
1329	Ready<='0';
1330
1331	when ex2_barrier6 => fifo_wr_en <= not(fifo_full);
1332	switch_port_out_rd_en <= '0';
1333	packet_received <= '0';
1334	dma_wr_request <= '0';
1335	dma_rd_request <= '0';
1336	Ram_rd<='0';
1337	Ram_wr<='0';
1338	Ram_data_in<=(others=>'0');
1339	barrier_completed <= '0';
1340	AppInitReq<='0';
1341	Ready<='0';
1342
1343	when ex2_barrier7 => fifo_wr_en <= not(fifo_full);
1344	switch_port_out_rd_en <= '0';
1345	packet_received <= '0';
1346	dma_wr_request <= '0';
1347	dma_rd_request <= '0';
1348	Ram_rd<='0';
1349	Ram_wr<='0';
1350	Ram_data_in<=(others=>'0');
1351	barrier_completed <= '0';
1352	AppInitReq<='0';
1353	Ready<='0';
1354
1355	when ex2_spawn => fifo_wr_en <= '0';
1356	switch_port_out_rd_en <= rd_ok;--switch_data_available;
1357	packet_received <= '0';
1358	dma_wr_request <= '0';
1359	dma_rd_request <= '0';
1360	Ram_rd<='0';
1361	Ram_wr<='0';
1362	barrier_completed <= '0';
1363	Ready<='0';
1364	Ram_data_in<=(others =>'0');
1365	AppInitReq<=wr_ok;
1366	when ex2_init1 => fifo_wr_en <= '0';
1367	switch_port_out_rd_en <= rd_ok;--switch_data_available;
1368	packet_received <= '0';
1369	dma_wr_request <= '0';
1370	dma_rd_request <= '0';
1371	Ram_rd<='0';
1372	Ram_wr<='0';
1373	barrier_completed <= '0';
1374	Ready<='0';
1375	Ram_data_in<=(others =>'0');
1376	AppInitReq<=wr_ok;
1377
1378
1379	when ex2_init2 => fifo_wr_en <= '0';
1380	switch_port_out_rd_en <='0';
1381	packet_received <= '0';
1382	dma_wr_request <= '0';
1383	dma_rd_request <= '0';
1384	Ram_rd<='0';
1385	Ram_wr<='0';
1386	barrier_completed <= '0';
1387	Ram_data_in<=(others =>'0');
1388	AppInitReq<= not(AppInitAck);
1389	Ready<='0';
1390
1391
1392	when ex2_Set_Busy =>
1393	Ready<='0';
1394	switch_port_out_rd_en<='0';
1395	fifo_wr_en <= '0';
1396	packet_received <= '0';
1397	AppInitReq<='0';
1398	barrier_completed <= '0';
1399	dma_rd_request <= sb_dma_rd_request;
1400	dma_wr_request <= sb_dma_wr_request;
1401	Ram_rd<=sb_ram_rd;
1402	Ram_wr<=sb_ram_wr;
1403	sb_ram_data_out<=Ram_data_out;
1404	Ram_data_in<=sb_ram_data_in;
1405	when others => Ready<='1'; -- le module est à nouveau libre
1406	fifo_wr_en <= '0';
1407	switch_port_out_rd_en <= '0';
1408	packet_received <= '0';
1409	dma_wr_request <= '0';
1410	dma_rd_request <= '0';
1411	barrier_completed <= '0';
1412	Ram_data_in<=(others=>'0');
1413	Ram_rd<='0';
1414	Ram_wr<='0';
1415	Ready<='1';
1416	AppInitReq<='0';
1417	end case;
1418
1419	end process;
1420
1421	ex2_fsm_sync:process(clk)
1422
1423	begin
1424	if rising_edge(clk) then
1425	if reset = '1' then
1426	ex2_state <= Ex2_Ready;
1427	ack_state<=ack0; --MAE d'envoie de AR
1428	n<=0;
1429	P_len<=(others=>'0');
1430	GPost<=(others =>'0');
1431	else
1432	ex2_state<=next_ex2_state;
1433	ack_state<=next_ack_state; --MAE d'envoie de AR
1434	n<=n_i;
1435	P_len<=P_len_i;
1436	dest_address <= dest_address_i;
1437	Sent_ack<=sent_ack_i;
1438	Instr_ack<=Instr_ack_i;
1439	Ptr_Get<=Ptr_Get_i;
1440	GPost<=GPost_i;
1441	for i in 0 to 3 loop
1442	Rec_Data(i)<=Rec_Data_i(i);
1443	end loop;
1444	end if;
1445	end if;
1446	end process ex2_fsm_sync;
1447	snd_ack:process (ack_state,reset,fifo_full,instr_ack)
1448	--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu
1449	begin
1450	-- if rising_edge(clk) then
1451
1452	if reset='1' then
1453	next_ack_state<=ack0;
1454	else
1455	next_ack_state<=ack_state;
1456	case ack_state is
1457	when ack0 =>to_fifo_ack<=(others=>'0');
1458	Wr_ack<='0';
1459	if instr_ack='1' then
1460	next_ack_state<=ack1;
1461	to_fifo_ack <= MPI_ACK & Dest_ack;
1462	wr_ack<='0';
1463	end if;
1464
1465	sent_ack_i<='0';
1466
1467	when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur
1468	-- en empilement dans le fifo
1469	to_fifo_ack <= MPI_ACK & Dest_ack;
1470	next_ack_state <= ack2;
1471	wr_ack<='1';
1472	else
1473	wr_ack<='0';
1474	end if;
1475	sent_ack_i<='0';
1476	when ack2 => if fifo_full = '0' then
1477	to_fifo_ack <= "00000100";--la longueur
1478
1479	next_ack_state <= ack3;
1480	wr_ack<='1';
1481	else --
1482	next_ack_state <= ack2;
1483	wr_ack<='0';
1484
1485	end if;
1486	sent_ack_i<='0';
1487	when ack3 => if fifo_full = '0' then
1488	to_fifo_ack <= "00000000";--
1489	next_ack_state <= ack4;
1490	wr_ack<='1';
1491	else --
1492	next_ack_state <= ack3;
1493	wr_ack<='0';
1494
1495	end if;
1496	sent_ack_i<='0';
1497	when ack4 => if fifo_full = '0' then
1498	to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur
1499	next_ack_state <= ack5;
1500	wr_ack<='1';
1501	sent_ack_i<='0';
1502	else --
1503	next_ack_state <= ack4;
1504	wr_ack<='0';
1505	sent_ack_i<='0';
1506	end if;
1507	when ack5 => if Instr_ack='0' then --dernier pulse
1508	next_ack_state <= ack0;
1509	else
1510	next_ack_state <= ack6;
1511	end if;
1512	wr_ack<='0';
1513	sent_ack_i<='1';
1514	to_fifo_ack<=(others=>'1');
1515	when ack6 => if Instr_ack='0' then
1516	next_ack_state <= ack0;
1517
1518	end if;
1519	wr_ack<='0';
1520	sent_ack_i<='1';
1521	to_fifo_ack<=(others=>'1');
1522	end case;
1523	end if;
1524	--end if;
1525	end process;
1526	Win_busy:process(Rec_wpost,GPost,RGET)
1527	begin
1528	-- if Gpost>0 then
1529	-- if rec_wpost=gpost and RGET='0' then
1530	-- Wbusy<='0';
1531	-- else
1532	-- Wbusy<='1';
1533	-- end if;
1534	-- end if;
1535	-- if RGET='1' then
1536	-- WBusy<='1';
1537	-- end if;
1538	end process Win_busy;
1539
1540	end Behavioral;
1541

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