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Changeset 72 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd
- Timestamp:
- Jan 6, 2014, 3:16:44 PM (10 years ago)
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd
r70 r72 114 114 type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, 115 115 fetch_addresses,ex2_spawn,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, 116 ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack ,117 ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,118 ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2 );116 ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, 117 Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, 118 ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); 119 119 type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6); 120 type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); 120 121 signal Next_Ex2_state,ex2_state :fsm_states; 121 122 signal ack_state,next_ack_state : fsm_ack; … … 126 127 signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0'); 127 128 signal n,n_i : natural range 0 to 15; 128 signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>' -');129 signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); 129 130 signal data_to_write_fifo : std_logic_vector(Word-1 downto 0); 130 131 --******************************************* … … 139 140 signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); 140 141 signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); 142 -- deuxième module pour set busy bit 143 signal bu_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); 144 signal bu_BitVal,bu_start,bu_done : std_logic:='0'; 145 signal bu_Ram_data_in : std_logic_vector(7 downto 0); 146 signal bu_dma_wr_request : std_logic; 147 signal bu_dma_rd_request : std_logic; 148 signal bu_ram_rd : std_logic; 149 signal bu_ram_wr : std_logic; 150 signal bu_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); 151 signal bu_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); 152 signal Set_Wbusy : std_logic:='0'; --choix du Mux 153 signal b_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); 154 signal b_BitVal,b_start,b_done : std_logic:='0'; 155 signal b_Ram_data_in : std_logic_vector(7 downto 0); 156 signal b_dma_wr_request : std_logic; 157 signal b_dma_rd_request : std_logic; 158 signal b_ram_rd : std_logic; 159 signal b_ram_wr : std_logic; 160 signal b_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); 161 signal b_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); 162 141 163 --********************************************* 142 164 signal Ex2_on : std_logic:='0'; … … 151 173 signal rpop:std_logic; 152 174 --signal mem:memory(0 to Msize-1)); 175 --jusqu'à 16 Get peuvent être attendus! 176 signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés 177 signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; -- 178 signal Rec_WPost, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0'); 179 signal Waited_Get : mem32(0 to 15); 180 Signal Rec_Data_i : Typ_PortIO(0 to 3); 181 signal Get_Instr,Put_instr :memory(0 to 8); 182 signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); 183 signal P_G: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get 184 signal Ptr_Get,Ptr_Get_i : natural range 0 to 15:=0; 185 signal Received_get : std_logic_vector(15 downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu 153 186 begin 154 187 ram_address <= dest_address; … … 199 232 done =>sb_done 200 233 ); 201 234 --b_BitVal<=bu_Bitval when Set_Wbusy='1' else Sb_BitVal; 235 --b_BitMask<=bu_BitMask when Set_Wbusy='1' else Sb_BitVal; 236 --b_start<= bu_start when Set_wBusy='1' else sb_start; 237 --b_ram_rd<=bu_ram_rd when Set_Wbusy='1' else Sb_ram_rd; 238 --b_ram_wr<=bu_ram_wr when Set_Wbusy='1' else Sb_ram_wr; 239 --b_dma_ram_request_rd<=bu__dma_ram_request_rd when Set_Wbusy='1' else Sb_dma_ram_request_rd; 240 --b_dma_ram_request_wr<=bu_dma_ram_request_wr when Set_Wbusy='1' else Sb_dma_ram_request_wr; 202 241 -- processus de transistion entre les etats 203 242 ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, 204 243 switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, 205 sent_ack,wr_ack,to_fifo_ack,dest_address )244 sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy) 206 245 variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée 207 246 variable tempval : std_logic_vector(Word-1 downto 0); 208 variable n_e :natural range 0 to 15 :=0;247 variable n_e,i:natural range 0 to 15 :=0; 209 248 procedure read_nocdat_fsm(sdata_avail: std_logic; 210 249 signal rd,wr:out std_logic; … … 256 295 packet_type<=switch_port_out_data(7 downto 4); 257 296 Dest_ack<=switch_port_out_data(3 downto 0); 258 Rec_Data (0)<=switch_port_out_data; --récupérer la première donnée reçue !297 Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! 259 298 rd_ok<='1'; 260 299 else … … 268 307 else 269 308 rd_ok<='1'; 309 Rec_Data_i(1)<=switch_port_out_data-2; 270 310 if packet_type = MPI_PUT then 271 311 P_len_i <= switch_port_out_data - 2; 272 312 n_i<=0; 313 273 314 Next_Ex2_state <= decode_packet_type2; 274 315 elsif packet_type = MPI_GET then … … 284 325 --rd_ok<='1'; 285 326 P_len_i <= switch_port_out_data-2; 286 Rec_Data (1)<=switch_port_out_data;327 Rec_Data_i(1)<=switch_port_out_data; 287 328 Next_Ex2_state <= ex2_init1; 288 329 elsif packet_type = MPI_ACK then … … 291 332 rd_ok<='0'; 292 333 P_len_i <= switch_port_out_data-2; 293 Next_Ex2_state <= ex2_ack; 334 Next_Ex2_state <= ex2_ack1; 335 elsif packet_type = MPI_WIN_SYNC then 336 n_i<=0; 337 wr_ok<='0'; 338 rd_ok<='0'; 339 P_len_i <= switch_port_out_data-2; 340 Next_Ex2_state <= ex2_Wsync; 294 341 elsif packet_type = MPI_SPAWN then 295 342 Next_Ex2_state <= ex2_spawn; … … 307 354 if switch_data_available = '1' then 308 355 dest_address_i(15 downto 8) <= switch_port_out_data; 356 Rec_data_i(2)<=switch_port_out_data; 309 357 n_i <= n + 1; 310 358 rd_ok<='1'; … … 315 363 if switch_data_available = '1' then 316 364 dest_address_i(Word-1 downto 0) <= switch_port_out_data; 365 Rec_data_i(3)<=switch_port_out_data; 317 366 P_len_i <= P_len - 2; 318 367 Next_Ex2_state <= ex2_put1; … … 324 373 end if; 325 374 end if; 326 327 when ex2_ack => rd_ok<='0'; 375 when Ex2_ack2 =>if unsigned(p_len)>0 then 376 If Dma_rd_grant='1' then 377 if n=0 then 378 n_i<=n+1; --cycle d'attente pour la RAM 379 elsif n=1 then 380 dest_address_i <= dest_address+1; 381 n_i<=2; 382 elsif n>=2 then 383 384 --creer un délai sur ces signaux par rapport à src_adress 385 386 n_i<=n+1; 387 rd_ok<='1'; 388 -- if n>1 then 389 dest_address_i <= dest_address+1; 390 p_len_i <= p_len - 1; 391 --end if; 392 Get_Instr(n-2)<=Ram_data_out; --deux cycles de retard 393 Next_ex2_state <= ex2_ack2; 394 end if; 395 end if; 396 dma_rd<='1'; 397 rd_ok<='1'; 398 else 399 if P_G=1 then 400 dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); 401 else 402 dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); 403 Waited_get(ptr_get)(7 downto 0)<=Get_instr(0); --id 404 Waited_get(ptr_get)(15 downto 8)<=Get_instr(1); --longueur 405 Waited_get(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas 406 Waited_get(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut 407 RGET<='1'; 408 409 Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter 410 end if; 411 Next_ex2_state <= ex2_ack3; 412 n_i<=0; --suite du process ack 413 rd_ok<='0'; 414 dma_rd<='0'; 415 end if; 416 when ex2_ack1 => rd_ok<='0'; 328 417 if n<2 then --réception de l'acquittement. 329 418 n_e:=n_i; … … 340 429 341 430 elsif n=3 then 342 n_i<=n+1; 431 n_i<=n+1;P_G<=0; 343 432 if data_to_ram(7 downto 4)=MPI_PUT then 344 433 Result_i<=data_to_ram; 345 dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); 346 wr_ok<='1'; 434 dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); 435 wr_ok<='1'; 436 P_G<=1; --put ou get 437 P_len_i<=x"06"; --longueur de l'entête à parcourir 347 438 elsif data_to_ram(7 downto 4)=MPI_GET then 348 439 Result_i<=data_to_ram; 349 440 wr_ok<='1'; -- 350 dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); 441 P_G<=2; --put get 442 P_len_i<=x"06";--taille de l'instruction en mémoire 443 dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); 351 444 elsif data_to_ram(7 downto 4)=MPI_SPAWN then 352 445 Result_i<=data_to_ram; … … 361 454 Result_i<="00000000"; 362 455 wr_ok<='0'; -- 363 end if; 364 elsif n=4 then --set acknowlege bit of the instruction 456 n_i<=n; --code inconnu ! 457 end if; 458 elsif n=4 then 459 if P_G=1 or P_G=2 then 460 Next_ex2_state<=ex2_ack2; 461 else 462 Next_ex2_state<=ex2_ack3; 463 end if; 464 n_i<=0; 465 end if; 466 467 when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction 365 468 sb_start<='1'; 366 469 sb_bitMask<=x"20";--cinquième bit à un 367 470 sb_bitval<='1'; 368 471 if sb_done='1' then 369 n_i<= 5;472 n_i<=1; 370 473 sb_start<='0'; 371 474 sb_bitval<='0'; 372 475 end if; 373 elsif n= 5then476 elsif n=1 then 374 477 Next_Ex2_state<=Ex2_Ready; 375 478 n_i<=0; 376 479 end if; 480 481 when ex2_Wsync => rd_ok<='0'; 482 if n<2 then --réception de la synchronisation. 483 n_e:=n_i; 484 read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); 485 n_i<=n_e; 486 elsif n=2 then 487 if switch_data_available='1' then 488 n_i<=n+1; 489 rd_ok<='1'; 490 491 data_to_ram<=switch_port_out_data; 492 Result_i<=switch_port_out_data; 493 end if; 494 495 elsif n=3 then 496 n_i<=n+1;P_G<=0; 497 if data_to_ram(7 downto 4)=SYNC_WSTART then 498 Result_i<=data_to_ram; 499 dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); 500 wr_ok<='1'; 501 P_G<=1; --put ou get 502 P_len_i<=x"06"; --longueur de l'entête à parcourir 503 elsif data_to_ram(7 downto 4)=SYNC_WPOST then 504 Result_i<=data_to_ram; 505 wr_ok<='1'; -- 506 P_G<=2; --put get 507 P_len_i<=x"06";--taille de l'instruction en mémoire 508 dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); 509 elsif data_to_ram(7 downto 4)=SYNC_WWAIT then 510 Result_i<=data_to_ram; 511 wr_ok<='1'; -- 512 dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); 513 elsif data_to_ram(7 downto 4)=SYNC_WCOMP then 514 Result_i<=data_to_ram; 515 dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); 516 wr_ok<='1'; -- 517 Next_Ex2_State<=Ex2_WCOMP; 518 n_i<=0; 519 else 520 Result_i<="00000000"; 521 wr_ok<='0'; -- 522 n_i<=n; --code inconnu ! 523 end if; 524 525 end if; 526 when Ex2_Wcomp => dma_rd<='1'; 527 rd_ok<='1'; 528 If Dma_rd_grant='1' then 529 if n=0 then 530 n_i<=n+1; --cycle d'attente pour la RAM 531 elsif n=1 then 532 dest_address_i <= dest_address+1; 533 n_i<=2; 534 elsif n=2 then 535 536 --creer un délai sur ces signaux par rapport à dest_adress 537 n_i<=n+1; 538 rd_ok<='1'; 539 dest_address_i <= dest_address; 540 GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard 541 elsif n=3 then 542 GPost_i(15 downto 8)<=Ram_data_out; 543 n_i<=n+1; 544 rd_ok<='1'; 545 dma_rd<='1'; 546 elsif n=4 then 547 GPost_i(15 downto 8)<=Ram_data_out; 548 rd_ok<='0'; 549 dma_rd<='1'; 550 n_i<=0; 551 Next_ex2_state <= ex2_set_busy; 552 end if; 553 end if; 554 377 555 when ex2_init1 => if n<2 then -- execution du mpi Init 378 556 wr_ok<='0'; … … 381 559 rd_ok<='1'; 382 560 P_len_i <=P_len-1; 383 Rec_Data (n+2)<=switch_port_out_data;561 Rec_Data_i(n+2)<=switch_port_out_data; 384 562 data_to_ram<=switch_port_out_data; 385 563 Result_i<=switch_port_out_data; … … 457 635 Next_Ex2_state <= ex2_put2; 458 636 data_to_ram<=switch_port_out_data; 459 rd_ok<=' 1';637 rd_ok<='0'; 460 638 n_i<=0; 461 639 delai:=0; … … 464 642 end if; 465 643 end if; 466 when ex2_put2 => if unsigned( P_len) > 1 then 644 when ex2_put2 => rd_ok<='0'; 645 n_i<=1; 646 i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0))); 647 Rec_WPost(i)<='1'; --indiquer que ce port a emis des données ! 648 if unsigned( P_len) > 0 then 467 649 468 if switch_data_available = '1' and d ma_wr_grant='1'then469 650 if switch_data_available = '1' and delai=0 then 651 delai:=1; --une donné lue 470 652 P_len_i <= P_len - 1; 471 dest_address_i <= dest_address + 1;472 653 Next_Ex2_state <= ex2_put2; 473 654 rd_ok<='1'; 474 wr_ok<='1';475 655 data_to_ram<=switch_port_out_data; 476 else 477 if switch_data_available = '1' and dma_wr_grant='0' then 478 if delai=0 then 479 data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch 480 end if; 481 delai:=1;--indique qu'un temps supplémentaire est 482 --nécessaire pour écrire la donnée en RAM 483 end if; 656 end if; 657 if dma_wr_grant='1' and delai=1 then 658 -- if n=1 then 659 wr_ok<='1'; 660 dest_address_i <= dest_address + 1; 661 delai:=0;--une donnée écrite 662 -- else 663 -- dest_address_i <= dest_address ; 664 -- end if; 665 --if delai=1 then 666 --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch 667 --end if; 668 669 else 670 dest_address_i<=dest_address; 671 wr_ok<='0'; 672 n_i<=0; 673 end if; 674 484 675 Next_Ex2_state <= ex2_put2; 485 rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données 486 end if; 676 487 677 else 678 rd_ok<='0'; 488 679 489 if switch_data_available = '1' and n=0 then 490 --la dernière donnée à écrire en RAM 491 data_to_ram<=switch_port_out_data; 492 rd_ok<='0'; 493 wr_ok<='1'; 494 n_i<=n+1; 495 else 496 rd_ok<='1'; 497 wr_ok<='0'; 498 end if; 680 499 681 if dma_wr_grant='1' and n=1 then 500 682 … … 504 686 end if; 505 687 end if; 506 688 507 689 when ex2_put3 => if dma_rd_grant='1' then 508 690 dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); … … 513 695 end if; 514 696 515 when ex2_put4 => if n<=4 then697 when ex2_put4 => if n<=4 and n>0 then 516 698 517 699 dma_wr<='1'; --demander un accès exclusif au bus … … 522 704 end if; 523 705 if n=0 then 524 if dma_rd_grant='1' then 525 n_i<=n+1; 526 else 706 if RGET='1' then 707 for i in 1 to Ptr_get loop 708 if waited_get(i-1)(3 downto 0)=rec_data_i(0)(3 downto 0) and 709 waited_get(i-1)(15 downto 8)=(rec_data_i(1)-2) and 710 waited_get(i-1)(23 downto 16)=rec_data_i(2) and 711 waited_get(i-1)(31 downto 24)=rec_data_i(3) then 712 if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data_i(0)(7 downto 4)=MPI_PUT) then 713 received_get(i-1)<='1'; 714 dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); 715 end if; 716 else 717 718 end if; 719 end loop; 720 end if; 721 722 n_i<=n+1; 527 723 rd_ok<='1'; 528 724 wr_ok<='0'; 529 end if;725 530 726 elsif n=1 then 727 531 728 if dma_rd_grant='1' then 729 if RGET='1' then --si on est en mode attente d'un Get 730 RGET<='0'; --Supposons tous les Gets reçus ! 731 test_wcomp:for i in 1 to Ptr_get loop --Tous les Get reçus ? 732 if received_get(i-1)='0' then 733 RGET<='1'; --Non ! 734 end if; 735 end loop; 736 737 end if; 532 738 n_i<=n+1; 533 739 else … … 536 742 end if; 537 743 elsif n=2 then 538 if dma_rd_grant='1' then744 if dma_rd_grant='1' and dma_wr_grant='1' then 539 745 n_i<=n+1; 540 746 tempval:=Ram_data_out; 541 747 tempval(4):='1'; --SET du bit DReceived 542 tempval(1):='0'; --reset du bit DRING !! 748 --si get ack est détecté 749 --tempval(6):=WBusy or RGET; -- Bit 6 Busy=0 si dernier get reçu !! 543 750 data_to_ram<=tempval; 544 751 rd_ok<='0'; … … 547 754 rd_ok<='1'; 548 755 wr_ok<='0'; 549 n_i<= n-1;756 n_i<=0; 550 757 end if; 551 758 elsif n=3 then … … 559 766 rd_ok<='0'; 560 767 wr_ok<='1'; 561 Next_Ex2_state <= ex2_put5; 562 n_i<=0; 563 end if; 768 769 n_i<=5; 770 end if; 771 elsif n=5 then 772 Next_Ex2_state <= ex2_set_busy; 773 n_i<=0; 774 rd_ok<='0'; 775 wr_ok<='0'; 564 776 end if; 565 777 566 778 567 779 568 dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction780 -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction 569 781 when ex2_put5 => 570 782 Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put … … 684 896 rd_ok<='0'; 685 897 end if; 898 i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0))); 899 Rec_WPost(i)<='1'; --indiquer que ce port a emis des données ! 900 901 --préparer en avance l'adresse de lecture/écriture 902 dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 686 903 when ex2_get3 => wr_ok<='0'; 687 904 if dma_rd_grant='1' then -- fin du mpi_get … … 721 938 n_i<=n+1; 722 939 tempval:=Ram_data_out; 723 tempval(2):='1'; --mise à 1 du Bit D receiving940 tempval(2):='1'; --mise à 1 du Bit DSending 724 941 --tempval(5):='0'; --Mise à 0 du Bit Sent 725 942 data_to_ram<=tempval; 726 rd_ok<=' 0';727 wr_ok<=' 1';943 rd_ok<='1'; 944 wr_ok<='0'; 728 945 else 729 946 rd_ok<='1'; 730 947 wr_ok<='0'; 948 n_i<=0; 731 949 end if; 732 950 … … 750 968 751 969 dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 970 when ex2_Set_Busy => if n=0 then --set busy bit of the instruction 971 dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); 972 n_i<=1; 973 if Gpost>0 then 974 if (rec_wpost=gpost) and RGET='0' then 975 Wbusy<='0'; 976 else 977 Wbusy<='1'; 978 end if; 979 else 980 n_i<=2; 981 end if; 982 if RGET='1' then 983 WBusy<='1'; 984 end if; 985 elsif n=1 then 986 sb_start<='1'; 987 sb_bitMask<=x"40";--6e bit à 1 988 sb_bitval<=WBusy; 989 if sb_done='1' then 990 n_i<=2; 991 sb_start<='0'; 992 sb_bitval<='0'; 993 end if; 994 elsif n=2 then 995 Next_Ex2_state<=Ex2_Ready; 996 n_i<=0; 997 end if; 752 998 -- execution du barrier 753 999 when ex2_barrier1 => if switch_data_available = '1' then … … 796 1042 when others => Next_Ex2_state <= Ex2_Ready; 797 1043 end case; 798 1044 799 1045 end process; 800 1046 801 1047 -- sortie de la machine à etat 802 1048 -- 803 ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type, 804 switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ dma_rd_request,n)1049 ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram, 1050 switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,n) 805 1051 variable transact : std_logic_vector(Word-1 downto 0); 806 1052 begin … … 813 1059 dma_rd_request <= '0'; 814 1060 barrier_completed <= '0'; 815 Ram_data_in<=(others=>' -');1061 Ram_data_in<=(others=>'0'); 816 1062 Ram_rd<='0'; 817 1063 Ram_wr<='0'; … … 824 1070 dma_rd_request <= '0'; 825 1071 barrier_completed <= '0'; 826 Ram_data_in<=(others=>' -');1072 Ram_data_in<=(others=>'0'); 827 1073 Ram_rd<='0'; 828 1074 Ram_wr<='0'; … … 838 1084 Ram_rd<='0'; 839 1085 Ram_wr<='0'; 840 Ram_data_in<=(others=>' -');1086 Ram_data_in<=(others=>'0'); 841 1087 barrier_completed <= '0'; 842 1088 AppInitReq<='0'; … … 850 1096 Ram_rd<='0'; 851 1097 Ram_wr<='0'; 852 Ram_data_in<=(others=>' -');1098 Ram_data_in<=(others=>'0'); 853 1099 barrier_completed <= '0'; 854 1100 AppInitReq<='0'; … … 861 1107 Ram_rd<='0'; 862 1108 Ram_wr<='0'; 863 Ram_data_in<=(others=>' -');1109 Ram_data_in<=(others=>'0'); 864 1110 barrier_completed <= '0'; 865 1111 AppInitReq<='0'; 866 1112 Ready<='0'; 867 when ex2_ack =>1113 when ex2_ack1 |ex2_Wsync => 868 1114 Ready<='0'; 869 1115 switch_port_out_rd_en<=rd_ok; … … 878 1124 sb_ram_data_out<=Ram_data_out; 879 1125 Ram_data_in<=sb_ram_data_in; 1126 when ex2_ack2|Ex2_WCOMP => 1127 Ready<='0'; 1128 switch_port_out_rd_en<='0'; 1129 fifo_wr_en <= '0'; 1130 packet_received <= '0'; 1131 AppInitReq<='0'; 1132 barrier_completed <= '0'; 1133 dma_rd_request <= dma_rd; 1134 dma_wr_request <= '0'; 1135 Ram_rd<=rd_ok; 1136 Ram_wr<='0'; 1137 when ex2_ack3 => 1138 Ready<='0'; 1139 switch_port_out_rd_en<=rd_ok; 1140 fifo_wr_en <= '0'; 1141 packet_received <= '0'; 1142 AppInitReq<='0'; 1143 barrier_completed <= '0'; 1144 dma_rd_request <= sb_dma_rd_request; 1145 dma_wr_request <= sb_dma_wr_request; 1146 Ram_rd<=sb_ram_rd; 1147 Ram_wr<=sb_ram_wr; 1148 sb_ram_data_out<=Ram_data_out; 1149 Ram_data_in<=sb_ram_data_in; 880 1150 when ex2_put1 => fifo_wr_en <= wr_ok; 881 1151 switch_port_out_rd_en <= '0'; … … 885 1155 Ram_rd<='0'; 886 1156 Ram_wr<='0'; 887 Ram_data_in<=(others=>' -');1157 Ram_data_in<=(others=>'0'); 888 1158 barrier_completed <= '0'; 889 1159 AppInitReq<='0'; … … 900 1170 Ram_data_in<=data_to_ram; 901 1171 end if; 902 Ram_wr<= '1';1172 Ram_wr<=wr_ok; 903 1173 Ram_rd<='0'; 904 1174 packet_received <= '0'; … … 909 1179 when ex2_put3 => Ready<='0'; 910 1180 fifo_wr_en <= '0'; 911 switch_port_out_rd_en <= rd_ok;1181 switch_port_out_rd_en <='0'; 912 1182 --ne pas corrompre le contenu de la RAM 913 1183 --Ram_data_in<=data_to_ram; … … 954 1224 Ram_rd<='0'; 955 1225 Ram_wr<='0'; 956 Ram_data_in<=(others=>' -');1226 Ram_data_in<=(others=>'0'); 957 1227 barrier_completed <= '0'; 958 1228 AppInitReq<='0'; … … 968 1238 Ram_rd<='0'; 969 1239 Ram_wr<='0'; 970 Ram_data_in<=(others=>' -');1240 Ram_data_in<=(others=>'0'); 971 1241 barrier_completed <= '0'; 972 1242 AppInitReq<='0'; … … 1005 1275 Ram_rd<='0'; 1006 1276 Ram_wr<='0'; 1007 Ram_data_in<=(others=>' -');1277 Ram_data_in<=(others=>'0'); 1008 1278 barrier_completed <= '0'; 1009 1279 Ready<='0'; … … 1018 1288 Ram_rd<='0'; 1019 1289 Ram_wr<='0'; 1020 Ram_data_in<=(others=>' -');1290 Ram_data_in<=(others=>'0'); 1021 1291 barrier_completed <= '0'; 1022 1292 AppInitReq<='0'; … … 1030 1300 Ram_rd<='0'; 1031 1301 Ram_wr<='0'; 1032 Ram_data_in<=(others=>' -');1302 Ram_data_in<=(others=>'0'); 1033 1303 barrier_completed <= '1'; 1034 1304 AppInitReq<='0'; … … 1041 1311 Ram_rd<='0'; 1042 1312 Ram_wr<='0'; 1043 Ram_data_in<=(others=>' -');1313 Ram_data_in<=(others=>'0'); 1044 1314 barrier_completed <= '0'; 1045 1315 AppInitReq<='0'; … … 1054 1324 Ram_rd<='0'; 1055 1325 Ram_wr<='0'; 1056 Ram_data_in<=(others=>' -');1326 Ram_data_in<=(others=>'0'); 1057 1327 barrier_completed <= '0'; 1058 1328 AppInitReq<='0'; … … 1066 1336 Ram_rd<='0'; 1067 1337 Ram_wr<='0'; 1068 Ram_data_in<=(others=>' -');1338 Ram_data_in<=(others=>'0'); 1069 1339 barrier_completed <= '0'; 1070 1340 AppInitReq<='0'; … … 1078 1348 Ram_rd<='0'; 1079 1349 Ram_wr<='0'; 1080 Ram_data_in<=(others=>' -');1350 Ram_data_in<=(others=>'0'); 1081 1351 barrier_completed <= '0'; 1082 1352 AppInitReq<='0'; … … 1092 1362 barrier_completed <= '0'; 1093 1363 Ready<='0'; 1094 Ram_data_in<=(others =>' -');1364 Ram_data_in<=(others =>'0'); 1095 1365 AppInitReq<=wr_ok; 1096 1366 when ex2_init1 => fifo_wr_en <= '0'; … … 1103 1373 barrier_completed <= '0'; 1104 1374 Ready<='0'; 1105 Ram_data_in<=(others =>' -');1375 Ram_data_in<=(others =>'0'); 1106 1376 AppInitReq<=wr_ok; 1107 1377 … … 1115 1385 Ram_wr<='0'; 1116 1386 barrier_completed <= '0'; 1117 Ram_data_in<=(others =>' -');1387 Ram_data_in<=(others =>'0'); 1118 1388 AppInitReq<= not(AppInitAck); 1119 1389 Ready<='0'; 1120 1390 1391 1392 when ex2_Set_Busy => 1393 Ready<='0'; 1394 switch_port_out_rd_en<='0'; 1395 fifo_wr_en <= '0'; 1396 packet_received <= '0'; 1397 AppInitReq<='0'; 1398 barrier_completed <= '0'; 1399 dma_rd_request <= sb_dma_rd_request; 1400 dma_wr_request <= sb_dma_wr_request; 1401 Ram_rd<=sb_ram_rd; 1402 Ram_wr<=sb_ram_wr; 1403 sb_ram_data_out<=Ram_data_out; 1404 Ram_data_in<=sb_ram_data_in; 1121 1405 when others => Ready<='1'; -- le module est à nouveau libre 1122 1406 fifo_wr_en <= '0'; … … 1126 1410 dma_rd_request <= '0'; 1127 1411 barrier_completed <= '0'; 1128 Ram_data_in<=(others=>' -');1412 Ram_data_in<=(others=>'0'); 1129 1413 Ram_rd<='0'; 1130 1414 Ram_wr<='0'; … … 1144 1428 n<=0; 1145 1429 P_len<=(others=>'0'); 1430 GPost<=(others =>'0'); 1146 1431 else 1147 1432 ex2_state<=next_ex2_state; … … 1152 1437 Sent_ack<=sent_ack_i; 1153 1438 Instr_ack<=Instr_ack_i; 1439 Ptr_Get<=Ptr_Get_i; 1440 GPost<=GPost_i; 1441 for i in 0 to 3 loop 1442 Rec_Data(i)<=Rec_Data_i(i); 1443 end loop; 1154 1444 end if; 1155 1445 end if; … … 1233 1523 end if; 1234 1524 --end if; 1235 end process; 1525 end process; 1526 Win_busy:process(Rec_wpost,GPost,RGET) 1527 begin 1528 -- if Gpost>0 then 1529 -- if rec_wpost=gpost and RGET='0' then 1530 -- Wbusy<='0'; 1531 -- else 1532 -- Wbusy<='1'; 1533 -- end if; 1534 -- end if; 1535 -- if RGET='1' then 1536 -- WBusy<='1'; 1537 -- end if; 1538 end process Win_busy; 1539 1236 1540 end Behavioral; 1237 1541
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