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HT_process.vhd @ 76

Last change on this file since 76 was 76, checked in by rolagamo, 10 years ago

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 12:04:21 04/22/2013
6	-- Design Name:
7	-- Module Name: HT_process - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	USE ieee.numeric_std.ALL;
23	library NocLib ;
24	use std.textio.all;
25	use NocLib.CoreTypes.all;
26	use work.Packet_type.all;
27	use work.MPI_RMA.all;
28	-- Uncomment the following library declaration if using
29	-- arithmetic functions with Signed or Unsigned values
30	--use IEEE.NUMERIC_STD.ALL;
31
32	-- Uncomment the following library declaration if instantiating
33	-- any Xilinx primitives in this code.
34	--library UNISIM;
35	--use UNISIM.VComponents.all;
36
37	entity HT_process is
38	generic (Task_id : natural:=0);
39	Port ( clk : in STD_LOGIC;
40	reset : in STD_LOGIC;
41	en : in std_logic; -- active la tâche
42	Interf_i : in core_i; --signaux pour l'interface IO
43	Interf_o : out core_o; --signaux pour l'interface IO
44	mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire
45	mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire
46	);
47	end HT_process;
48
49	architecture Behavioral of HT_process is
50
51	type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart,
52	putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout);
53	signal sram : typ_dpram;
54	signal MyGroup:mpi_group;
55	signal MyWin : mpi_win;
56	signal MyRank :std_logic_vector(3 downto 0);
57	signal intercomm,array_of_errcodes : natural;
58	signal ct_state:natural:=0;
59	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
60	signal RunState : typ_mae;
61
62	begin
63
64	--MAE du PE
65	--=======================================================================
66	-- Interf<=Libr;
67
68
69	pPutGet:process(clk,reset,en)
70
71	constant DATAPTR : natural :=256;
72	variable nb_rma:natural range 0 to 15:=0;
73	variable bfill,destrank,pid,mport : natural range 0 to 15;
74	variable fsrc,ret : natural range 0 to 15:=0;
75	variable timeout,ct,dlen,dcount : natural range 0 to 255;
76	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
77	variable mywin : Mpi_win;
78	variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn
79	variable comm : natural :=0;
80	variable iack : std_logic:='0';
81	variable adresse,adresse_rd :natural range 0 to 65536;
82	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
83
84	--=======================================================
85	--variables pour la création du fichier de résultats
86	-- synthesis translate_off
87	type char_file is file of character;
88	file f: text;
89	variable status :file_open_status ;
90	variable char_count: integer range 0 to 65536 := 0;
91	variable str: string (1 to 79) ;
92	variable L: line;
93	variable fopened: std_logic:='0';
94
95	constant simres : time :=1 ps; --simulation resolution
96	constant realres : real :=1.0e-3; --ramener le temps en ns
97	-- returns real value of time parameter using pure VHDL
98	function rt(t : time) return real is
99	begin
100	return real(t/simres) * realres;
101	end;
102	-- synthesis translate_on
103	--======================================================
104	begin
105	--=== Partie combinatoire du process ===================================
106
107	--=== Fin de la partie combinatoire du process ==========================
108
109
110
111	--end loop;
112
113	if (clk'event and clk='1') and en='1' then
114
115
116	if reset='1' then
117	RunState<=start;
118
119	else
120	--==========================================================
121	--affectation des entrées sorties mémoires
122	sram.i.data_out<=mem_I.data_out;
123	mem_o.addr_wr<=sram.O.addr_wr;
124	mem_o.addr_rd<=sram.O.addr_rd ;
125	mem_o.we<=sram.O.we;
126	mem_o.ena<=sram.O.ena;
127	mem_o.enb<=sram.O.enb;
128	mem_o.data_in<=sram.O.data_in;
129	--affectation des entrées sorties MPI_HCL
130	Interf_o.Instr_EN<=Libr.O.instr_en;
131	Interf_o.Membusy<=Libr.O.MemBusy;
132	Interf_o.Instruction<=Libr.O.Instruction;
133	Libr.i.Instr_ack<=Interf_i.Instr_ack;
134	Libr.i.InitOk<=Interf_i.InitOk;
135	Libr.i.Hold_Req<=Interf_i.Hold_req;
136	Libr.I.Spawned<=Interf_i.Spawned;
137	--Libr.i.Hold_Ack<=Interf_i.Hold_Ack;
138	Libr.i.RamSel<=Interf_i.RamSel;
139	--ct_state<=ct; --pour débogage
140	--============================================================
141
142	case RunState is
143	when start =>
144	--Dcount<=0;
145	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
146	RunState<=InitApp;
147	end if;
148	--Ram_busy<='0';
149	Libr.O.MemBusy<='0';
150	Libr.O.Instr_En<='0';
151	iack:='0';
152	adresse:=10;--DATAPTR;
153
154	adresse_rd:=0;
155	timeout:=0;
156	--dcount<=0;
157	sram.O.we<='0';
158	sram.O.ena<='0';
159	sram.O.enb<='0';
160	-- synthesis translate_off
161	if fopened='0' then
162	file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE);
163	--while not endfile(c_file_handle) loop
164	--end if;
165
166	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
167	--report l.all;
168	-- writeline (f, l) ;
169	fopened:='1';
170	end if;
171	-- synthesis translate_on
172	when Fillmem =>
173	sram.O.we<='1';
174	sram.O.ena<='1';
175	sram.O.enb<='0';
176	if Libr.I.Ramsel='0' then
177
178	sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
179	sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
180	Libr.O.Instr_En<='0';
181	dcount:=dcount+1;
182
183	if dcount=250 then
184	bfill:=bfill+1;
185
186	if bfill=4 then
187	RunState<=WinCreate;
188	else
189	RunState<=nextfill;
190	end if;
191	else
192	adresse:=adresse+1;
193	RunState<=Fillmem;
194	end if;
195	else -- attente de la libéraion de la mémoire
196	timeout:=timeout+1;
197	if timeout=100 then
198	RunState<=st_timeout;
199	end if;
200
201	end if;
202	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
203	adresse:=250*bfill+10;
204
205	dcount:=0;
206	ct:=0;
207	RunState<=Fillmem;
208	Libr.O.Instr_En<='0';
209	sram.O.we<='1';
210	sram.O.ena<='1';
211	sram.O.enb<='0';
212	when InitApp =>
213	--code pour Init
214	dlen:=10;
215	if ct=0 then
216	-- synthesis translate_off
217	write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
218
219	report l.all;
220	writeline (f, l) ;
221	-- synthesis translate_on
222	end if;
223	pMPI_Init(ct,Libr,Clk,SRam);
224
225	adresse:=to_integer(unsigned(sram.O.addr_wr));
226	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
227
228	--if Libr.InitOk='1' then
229	if ct=0 then
230	RunState<=GetRank;
231	-- synthesis translate_off
232	write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
233	report l.all;
234	writeline (f, l) ;
235	-- synthesis translate_on
236	end if;
237
238
239
240	when GetRank =>
241	if ct=0 then
242	-- synthesis translate_off
243	write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
244	report l.all;
245	writeline (f, l) ;
246	-- synthesis translate_on
247	end if;
248	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
249	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
250
251
252	if ct=0 then
253	RunState<=Fillmem;
254	-- synthesis translate_off
255	write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
256	report l.all;
257	writeline (f, l) ;
258	-- synthesis translate_on
259	end if;
260
261
262	when Wincreate => --par défaut la fenêtre 0 est utilisée !
263	case MyRank is
264	when x"0"=>
265	Mygroup.grp<=x"000E";-- rank 1,2,3
266	MyGroup.nb<=2;
267	destRank:=1;
268	DestAdr:=X"043F";
269	nb_rma:=1;
270	when x"1" =>
271	Mygroup.grp<=x"0000";-- rank 0
272	destRank:=0;
273	DestAdr:=X"043F";
274	when x"2" =>
275	Mygroup.grp<=x"0000";-- rank
276	destRank:=0;
277	DestAdr:=X"044F";
278	when x"3" =>
279	Mygroup.grp<=x"0000";-- rank
280	destRank:=0;
281	DestAdr:=X"045F";
282	when others => --cas des processus spawn
283	Mygroup.grp<=x"0000";-- rank 0
284	destRank:=0;
285	end case;
286	RunState<=WinPost;
287	when WinPost =>
288	if ct=0 then
289	-- synthesis translate_off
290	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
291	report l.all;
292	writeline (f, l) ;
293	-- synthesis translate_on
294	end if;
295
296	pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin);
297
298	if ct=0 then
299	RunState<=WinStart;
300	-- synthesis translate_off
301	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
302	report l.all;
303	writeline (f, l) ;
304	-- synthesis translate_on
305	end if;
306
307	when WinStart =>
308	if ct=0 then
309	-- synthesis translate_off
310	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
311	report l.all;
312	writeline (f, l) ;
313	-- synthesis translate_on
314	end if;
315	pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
316	adresse:=to_integer(unsigned(sram.O.addr_wr));
317	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
318
319	dcount:=ct;
320
321	if ct=0 then
322	RunState<=PutData;
323	-- synthesis translate_off
324	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
325	report l.all;
326	writeline (f, l) ;
327	-- synthesis translate_on
328	end if;
329
330
331	when putdata => --construire le packet pour le Put
332
333	--dlen:=251; ---
334	if ct=0 then
335	-- synthesis translate_off
336	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
337	report l.all;
338	writeline (f, l) ;
339	-- synthesis translate_on
340	end if;
341
342	SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
343	--DestAdr:=X"033F";
344	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
345
346	adresse:=to_integer(unsigned(sram.O.addr_wr));
347	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
348
349	dcount:=ct;
350
351	if ct=0 then
352	RunState<=GetData;
353	-- synthesis translate_off
354	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now));
355	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now))));
356	report l.all;
357	writeline (f, l) ;
358	-- synthesis translate_on
359	end if;
360
361
362	when getdata => --positionnement du mot de longueur des données
363	--dlen:=251; ---
364	if ct=0 then
365	-- synthesis translate_off
366	write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
367	report l.all;
368	writeline (f, l) ;
369	-- synthesis translate_on
370	end if;
371
372	SrcAdr:=X"006D";
373	DestAdr:=X"1400";
374	if unsigned(MyRank) = 0 then
375	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
376	else
377
378	--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win);
379	end if;
380	adresse:=to_integer(unsigned(sram.O.addr_wr));
381	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
382
383	dcount:=ct;
384
385	if ct=0 then
386	if unsigned(MyRank)/=0 then
387	RunState<=wincompleted;
388	else
389	nb_rma:=nb_rma+1;
390	if nb_rma=2 then
391	RunState<=wincompleted;
392	nb_rma:=0;
393	end if;
394	end if;
395	-- synthesis translate_off
396	assert ct/=0 report "GET_END " & integer'image(destrank)
397	severity Warning ;
398	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
399	report l.all;
400
401	writeline (f, l) ;
402	-- synthesis translate_on
403	end if;
404
405	when WinCompleted =>
406	if ct=0 then
407	-- synthesis translate_off
408	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
409	report l.all;
410	writeline (f, l) ;
411	-- synthesis translate_on
412	end if;
413	pMPI_Win_Complete(ct,Libr,sram,MyWin );
414	adresse:=to_integer(unsigned(sram.O.addr_wr));
415	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
416
417	if ct=0 then
418	RunState<=WinWait;
419	-- synthesis translate_off
420	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
421	report l.all;
422	writeline (f, l) ;
423	-- synthesis translate_on
424
425	end if;
426	when WinWait =>
427	if ct=0 then
428	-- synthesis translate_off
429	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
430	report l.all;
431	writeline (f, l) ;
432	-- synthesis translate_on
433	end if;
434	pMPI_Win_wait(ct,Libr,sram,MyWin );
435	adresse:=to_integer(unsigned(sram.O.addr_wr));
436	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
437
438	if ct=0 then
439	if unsigned(Myrank)>3 then
440	RunState<=Finalize;
441	else
442	RunState<=MpiSpawn;
443	end if;
444	-- synthesis translate_off
445	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
446	report l.all;
447	writeline (f, l) ;
448	-- synthesis translate_on
449
450	end if;
451
452	when MpiSpawn =>
453	if ct=0 then
454	-- synthesis translate_off
455	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
456	report l.all;
457	writeline (f, l) ;
458	-- synthesis translate_on
459	end if;
460	--(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
461
462	maxprocs:=2;
463	pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes);
464	adresse:=to_integer(unsigned(sram.O.addr_wr));
465	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
466
467	if ct=0 then
468	RunState<=Finalize;
469	-- synthesis translate_off
470	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
471	report l.all;
472	writeline (f, l) ;
473	-- synthesis translate_on
474
475	end if;
476	when finalize =>
477	if ct=0 then
478	-- synthesis translate_off
479	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
480	report l.all;
481	writeline (f, l) ;
482	-- synthesis translate_on
483	end if;
484	sram.O.we<='0';
485	sram.O.ena<='0';
486	sram.O.enb<='0';
487	if ct=0 then
488	RunState<=start;
489	-- synthesis translate_off
490	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
491	report l.all;
492	writeline (f, l) ;
493	file_close(f);
494	-- synthesis translate_on
495	end if;
496
497	when st_timeout =>
498
499	sram.O.we<='0';
500	sram.O.ena<='0';
501	sram.O.enb<='0';
502
503	RunState<=start;
504	end case;
505	ct_state<=ct; --pour débogage
506	end if;
507	end if;
508
509	end process pPutGet;
510
511	end Behavioral;
512

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