source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise @ 74

Last change on this file since 74 was 74, checked in by rolagamo, 10 years ago
File size: 43.5 KB
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1<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4  <!--                                                          -->
5
6  <!--             For tool use only. Do not edit.              -->
7
8  <!--                                                          -->
9
10  <!-- ProjectNavigator created generated project file.         -->
11
12  <!-- For use in tracking generated file and other information -->
13
14  <!-- allowing preservation of process status.                 -->
15
16  <!--                                                          -->
17
18  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
19
20  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
21
22  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="MPI_CORE_COMPONENTS.xise"/>
23
24  <files xmlns="http://www.xilinx.com/XMLSchema">
25    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="CORE_MPI.bld"/>
26    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="CORE_MPI.cmd_log"/>
27    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="CORE_MPI.lso"/>
28    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="CORE_MPI.ngc"/>
29    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="CORE_MPI.ngd"/>
30    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="CORE_MPI.ngr"/>
31    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="CORE_MPI.prj"/>
32    <file xil_pn:fileType="FILE_SPL" xil_pn:name="CORE_MPI.spl"/>
33    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="CORE_MPI.stx"/>
34    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="CORE_MPI.sym" xil_pn:origination="imported"/>
35    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="CORE_MPI.syr"/>
36    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="CORE_MPI.xst"/>
37    <file xil_pn:fileType="FILE_HTML" xil_pn:name="CORE_MPI_envsettings.html"/>
38    <file xil_pn:fileType="FILE_NCD" xil_pn:name="CORE_MPI_guide.ncd" xil_pn:origination="imported"/>
39    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="CORE_MPI_map.map" xil_pn:subbranch="Map"/>
40    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="CORE_MPI_map.mrp" xil_pn:subbranch="Map"/>
41    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="CORE_MPI_map.ngm" xil_pn:subbranch="Map"/>
42    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_map.xrpt"/>
43    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_ngdbuild.xrpt"/>
44    <file xil_pn:fileType="FILE_HTML" xil_pn:name="CORE_MPI_summary.html"/>
45    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="CORE_MPI_xst.xrpt"/>
46    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Crossbar.bld"/>
47    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Crossbar.cmd_log"/>
48    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Crossbar.lso"/>
49    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Crossbar.ncd" xil_pn:subbranch="Par"/>
50    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Crossbar.ngc"/>
51    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="Crossbar.ngd"/>
52    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Crossbar.ngr"/>
53    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="Crossbar.par" xil_pn:subbranch="Par"/>
54    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="Crossbar.pcf" xil_pn:subbranch="Map"/>
55    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Crossbar.prj"/>
56    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Crossbar.stx"/>
57    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Crossbar.syr"/>
58    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="Crossbar.twr" xil_pn:subbranch="Par"/>
59    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="Crossbar.twx" xil_pn:subbranch="Par"/>
60    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="Crossbar.unroutes" xil_pn:subbranch="Par"/>
61    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Crossbar.xst"/>
62    <file xil_pn:fileType="FILE_NCD" xil_pn:name="Crossbar_guide.ncd" xil_pn:origination="imported"/>
63    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Crossbar_map.map" xil_pn:subbranch="Map"/>
64    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Crossbar_map.mrp" xil_pn:subbranch="Map"/>
65    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Crossbar_map.ncd" xil_pn:subbranch="Map"/>
66    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="Crossbar_map.ngm" xil_pn:subbranch="Map"/>
67    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="Crossbar_pad.csv" xil_pn:subbranch="Par"/>
68    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="Crossbar_pad.txt" xil_pn:subbranch="Par"/>
69    <file xil_pn:fileType="FILE_HTML" xil_pn:name="Crossbar_summary.html"/>
70    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="Crossbar_xst.xrpt"/>
71    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="DMA_ARBITER.bld"/>
72    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="DMA_ARBITER.cmd_log"/>
73    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="DMA_ARBITER.lso"/>
74    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="DMA_ARBITER.ncd" xil_pn:subbranch="Par"/>
75    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="DMA_ARBITER.ngc"/>
76    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="DMA_ARBITER.ngd"/>
77    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="DMA_ARBITER.ngr"/>
78    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="DMA_ARBITER.pad"/>
79    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="DMA_ARBITER.par" xil_pn:subbranch="Par"/>
80    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="DMA_ARBITER.pcf" xil_pn:subbranch="Map"/>
81    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DMA_ARBITER.prj"/>
82    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="DMA_ARBITER.ptwx"/>
83    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="DMA_ARBITER.stx"/>
84    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="DMA_ARBITER.syr"/>
85    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="DMA_ARBITER.twr" xil_pn:subbranch="Par"/>
86    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="DMA_ARBITER.twx" xil_pn:subbranch="Par"/>
87    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="DMA_ARBITER.unroutes" xil_pn:subbranch="Par"/>
88    <file xil_pn:fileType="FILE_XPI" xil_pn:name="DMA_ARBITER.xpi"/>
89    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="DMA_ARBITER.xst"/>
90    <file xil_pn:fileType="FILE_HTML" xil_pn:name="DMA_ARBITER_envsettings.html"/>
91    <file xil_pn:fileType="FILE_NCD" xil_pn:name="DMA_ARBITER_guide.ncd" xil_pn:origination="imported"/>
92    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="DMA_ARBITER_map.map" xil_pn:subbranch="Map"/>
93    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="DMA_ARBITER_map.mrp" xil_pn:subbranch="Map"/>
94    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="DMA_ARBITER_map.ncd" xil_pn:subbranch="Map"/>
95    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="DMA_ARBITER_map.ngm" xil_pn:subbranch="Map"/>
96    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="DMA_ARBITER_map.xrpt"/>
97    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="DMA_ARBITER_pad.csv" xil_pn:subbranch="Par"/>
98    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="DMA_ARBITER_pad.txt" xil_pn:subbranch="Par"/>
99    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="DMA_ARBITER_par.xrpt"/>
100    <file xil_pn:fileType="FILE_HTML" xil_pn:name="DMA_ARBITER_summary.html"/>
101    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="DMA_ARBITER_summary.xml"/>
102    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="DMA_ARBITER_usage.xml"/>
103    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="DMA_ARBITER_xst.xrpt"/>
104    <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/>
105    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="FIFO_256_FWFT_isim_beh.exe"/>
106    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Hold_FSM_isim_beh.exe"/>
107    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPICORETEST_guide.ncd" xil_pn:origination="imported"/>
108    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MPI_CORE_SCHEDULER.bld"/>
109    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MPI_CORE_SCHEDULER.cmd_log"/>
110    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MPI_CORE_SCHEDULER.lso"/>
111    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_CORE_SCHEDULER.ncd" xil_pn:subbranch="Par"/>
112    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MPI_CORE_SCHEDULER.ngc"/>
113    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MPI_CORE_SCHEDULER.ngd"/>
114    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MPI_CORE_SCHEDULER.ngr"/>
115    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MPI_CORE_SCHEDULER.par" xil_pn:subbranch="Par"/>
116    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MPI_CORE_SCHEDULER.pcf" xil_pn:subbranch="Map"/>
117    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MPI_CORE_SCHEDULER.prj"/>
118    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MPI_CORE_SCHEDULER.stx"/>
119    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MPI_CORE_SCHEDULER.syr"/>
120    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MPI_CORE_SCHEDULER.twr" xil_pn:subbranch="Par"/>
121    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MPI_CORE_SCHEDULER.twx" xil_pn:subbranch="Par"/>
122    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MPI_CORE_SCHEDULER.unroutes" xil_pn:subbranch="Par"/>
123    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MPI_CORE_SCHEDULER.xst"/>
124    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPI_CORE_SCHEDULER_envsettings.html"/>
125    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_CORE_SCHEDULER_guide.ncd" xil_pn:origination="imported"/>
126    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MPI_CORE_SCHEDULER_map.map" xil_pn:subbranch="Map"/>
127    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MPI_CORE_SCHEDULER_map.mrp" xil_pn:subbranch="Map"/>
128    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_CORE_SCHEDULER_map.ncd" xil_pn:subbranch="Map"/>
129    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MPI_CORE_SCHEDULER_map.ngm" xil_pn:subbranch="Map"/>
130    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MPI_CORE_SCHEDULER_pad.csv" xil_pn:subbranch="Par"/>
131    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MPI_CORE_SCHEDULER_pad.txt" xil_pn:subbranch="Par"/>
132    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPI_CORE_SCHEDULER_summary.html"/>
133    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MPI_CORE_SCHEDULER_xst.xrpt"/>
134    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MPI_NOC.fdo"/>
135    <file xil_pn:fileType="FILE_SPL" xil_pn:name="MPI_NOC.spl"/>
136    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="MPI_NOC.sym" xil_pn:origination="imported"/>
137    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPI_NOC_guide.ncd" xil_pn:origination="imported"/>
138    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MultiMPITest.bld"/>
139    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MultiMPITest.cmd_log"/>
140    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MultiMPITest.fdo"/>
141    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MultiMPITest.lso"/>
142    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest.ncd" xil_pn:subbranch="Par"/>
143    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MultiMPITest.ngc"/>
144    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MultiMPITest.ngd"/>
145    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MultiMPITest.ngr"/>
146    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="MultiMPITest.pad"/>
147    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MultiMPITest.par" xil_pn:subbranch="Par"/>
148    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MultiMPITest.pcf" xil_pn:subbranch="Map"/>
149    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest.prj"/>
150    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="MultiMPITest.ptwx"/>
151    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MultiMPITest.stx"/>
152    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MultiMPITest.syr"/>
153    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest.twr" xil_pn:subbranch="Par"/>
154    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest.twx" xil_pn:subbranch="Par"/>
155    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MultiMPITest.unroutes" xil_pn:subbranch="Par"/>
156    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="MultiMPITest.ut" xil_pn:subbranch="FPGAConfiguration"/>
157    <file xil_pn:fileType="FILE_XPI" xil_pn:name="MultiMPITest.xpi"/>
158    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MultiMPITest.xst"/>
159    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_envsettings.html"/>
160    <file xil_pn:fileType="FILE_LOG" xil_pn:name="MultiMPITest_fpga_editor.log"/>
161    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_guide.ncd" xil_pn:origination="imported"/>
162    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="MultiMPITest_isim_beh.exe"/>
163    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.map" xil_pn:subbranch="Map"/>
164    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.mrp" xil_pn:subbranch="Map"/>
165    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_map.ncd" xil_pn:subbranch="Map"/>
166    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MultiMPITest_map.ngm" xil_pn:subbranch="Map"/>
167    <file xil_pn:fileType="FILE_LOG" xil_pn:name="MultiMPITest_map_fpga_editor.log"/>
168    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MultiMPITest_pad.csv" xil_pn:subbranch="Par"/>
169    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MultiMPITest_pad.txt" xil_pn:subbranch="Par"/>
170    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_par.xrpt"/>
171    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest_preroute.twr" xil_pn:subbranch="Map"/>
172    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest_preroute.twx" xil_pn:subbranch="Map"/>
173    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest_stx_beh.prj"/>
174    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_summary.html"/>
175    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest_vhdl.prj"/>
176    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_xst.xrpt"/>
177    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="PE.bld"/>
178    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="PE.cmd_log"/>
179    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="PE.fdo"/>
180    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="PE.lso"/>
181    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE.ncd" xil_pn:subbranch="Par"/>
182    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="PE.ngc"/>
183    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="PE.ngd"/>
184    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="PE.ngr"/>
185    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="PE.par" xil_pn:subbranch="Par"/>
186    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="PE.pcf" xil_pn:subbranch="Map"/>
187    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="PE.prj"/>
188    <file xil_pn:fileType="FILE_SPL" xil_pn:name="PE.spl"/>
189    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="PE.stx"/>
190    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="PE.sym" xil_pn:origination="imported"/>
191    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="PE.syr"/>
192    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="PE.twr" xil_pn:subbranch="Par"/>
193    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="PE.twx" xil_pn:subbranch="Par"/>
194    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="PE.unroutes" xil_pn:subbranch="Par"/>
195    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="PE.xst"/>
196    <file xil_pn:fileType="FILE_HTML" xil_pn:name="PE_envsettings.html"/>
197    <file xil_pn:fileType="FILE_NCD" xil_pn:name="PE_guide.ncd" xil_pn:origination="imported"/>
198    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="PE_isim_beh.exe"/>
199    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="PE_map.map" xil_pn:subbranch="Map"/>
200    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="PE_map.mrp" xil_pn:subbranch="Map"/>
201    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE_map.ncd" xil_pn:subbranch="Map"/>
202    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="PE_map.ngm" xil_pn:subbranch="Map"/>
203    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="PE_pad.csv" xil_pn:subbranch="Par"/>
204    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="PE_pad.txt" xil_pn:subbranch="Par"/>
205    <file xil_pn:fileType="FILE_HTML" xil_pn:name="PE_summary.html"/>
206    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="PE_xst.xrpt"/>
207    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="SWITCH_GEN.bld"/>
208    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SWITCH_GEN.cmd_log"/>
209    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SWITCH_GEN.lso"/>
210    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN.ncd" xil_pn:subbranch="Par"/>
211    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SWITCH_GEN.ngc"/>
212    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="SWITCH_GEN.ngd"/>
213    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SWITCH_GEN.ngr"/>
214    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="SWITCH_GEN.pad"/>
215    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="SWITCH_GEN.par" xil_pn:subbranch="Par"/>
216    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="SWITCH_GEN.pcf" xil_pn:subbranch="Map"/>
217    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SWITCH_GEN.prj"/>
218    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="SWITCH_GEN.ptwx"/>
219    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SWITCH_GEN.stx"/>
220    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SWITCH_GEN.syr"/>
221    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="SWITCH_GEN.twr" xil_pn:subbranch="Par"/>
222    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="SWITCH_GEN.twx" xil_pn:subbranch="Par"/>
223    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="SWITCH_GEN.unroutes" xil_pn:subbranch="Par"/>
224    <file xil_pn:fileType="FILE_XPI" xil_pn:name="SWITCH_GEN.xpi"/>
225    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SWITCH_GEN.xst"/>
226    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SWITCH_GENERIQUE.cmd_log"/>
227    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SWITCH_GENERIQUE.lso"/>
228    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SWITCH_GENERIQUE.prj"/>
229    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SWITCH_GENERIQUE.syr"/>
230    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SWITCH_GENERIQUE.xst"/>
231    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GENERIQUE_envsettings.html"/>
232    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GENERIQUE_summary.html"/>
233    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GENERIQUE_xst.xrpt"/>
234    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_envsettings.html"/>
235    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_guide.ncd" xil_pn:origination="imported"/>
236    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SWITCH_GEN_map.map" xil_pn:subbranch="Map"/>
237    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SWITCH_GEN_map.mrp" xil_pn:subbranch="Map"/>
238    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_map.ncd" xil_pn:subbranch="Map"/>
239    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SWITCH_GEN_map.ngm" xil_pn:subbranch="Map"/>
240    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SWITCH_GEN_pad.csv" xil_pn:subbranch="Par"/>
241    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SWITCH_GEN_pad.txt" xil_pn:subbranch="Par"/>
242    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_par.xrpt"/>
243    <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_summary.html"/>
244    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_xst.xrpt"/>
245    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SetBit.vhi"/>
246    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
247    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
248    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
249    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
250    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
251    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
252    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
253    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
254    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
255    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
256    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
257    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="load_instr.bld"/>
258    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="load_instr.cmd_log"/>
259    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="load_instr.lso"/>
260    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr.ncd" xil_pn:subbranch="Par"/>
261    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="load_instr.ngc"/>
262    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="load_instr.ngd"/>
263    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="load_instr.ngr"/>
264    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="load_instr.par" xil_pn:subbranch="Par"/>
265    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="load_instr.pcf" xil_pn:subbranch="Map"/>
266    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="load_instr.prj"/>
267    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="load_instr.stx"/>
268    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="load_instr.syr"/>
269    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="load_instr.twr" xil_pn:subbranch="Par"/>
270    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="load_instr.twx" xil_pn:subbranch="Par"/>
271    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="load_instr.unroutes" xil_pn:subbranch="Par"/>
272    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="load_instr.xst"/>
273    <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_envsettings.html"/>
274    <file xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr_guide.ncd" xil_pn:origination="imported"/>
275    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="load_instr_map.map" xil_pn:subbranch="Map"/>
276    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="load_instr_map.mrp" xil_pn:subbranch="Map"/>
277    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="load_instr_map.ncd" xil_pn:subbranch="Map"/>
278    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="load_instr_map.ngm" xil_pn:subbranch="Map"/>
279    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="load_instr_pad.csv" xil_pn:subbranch="Par"/>
280    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="load_instr_pad.txt" xil_pn:subbranch="Par"/>
281    <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_summary.html"/>
282    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="load_instr_xst.xrpt"/>
283    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="mpi_test.fdo"/>
284    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_beh.prj"/>
285    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mpi_test_isim_beh.exe"/>
286    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="mpi_test_isim_beh.wdb"/>
287    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_stx_beh.prj"/>
288    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="multimpitest.bgn" xil_pn:subbranch="FPGAConfiguration"/>
289    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="multimpitest.bit" xil_pn:subbranch="FPGAConfiguration"/>
290    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="multimpitest.drc" xil_pn:subbranch="FPGAConfiguration"/>
291    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="pepExtractor.prj"/>
292    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
293    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_DMA_isim_beh.exe"/>
294    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="test_xbar_8x8.fdo"/>
295    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_xbar_8x8_isim_beh.exe"/>
296    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
297    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
298    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
299    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
300    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
301    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
302    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
303    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
304    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
305  </files>
306
307  <transforms xmlns="http://www.xilinx.com/XMLSchema">
308    <transform xil_pn:end_ts="1389570072" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1389570072">
309      <status xil_pn:value="SuccessfullyRun"/>
310      <status xil_pn:value="ReadyToRun"/>
311    </transform>
312    <transform xil_pn:end_ts="1389743130" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1389743129">
313      <status xil_pn:value="SuccessfullyRun"/>
314      <status xil_pn:value="ReadyToRun"/>
315      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
316      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
317      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
318      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
319      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
320      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
321      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
322      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
323      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
324      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD"/>
325      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD"/>
326      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
327      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
328      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
329      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
330      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
331      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
332      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
333      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
334      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
335      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
336      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
337      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
338      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD"/>
339      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
340      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
341      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd"/>
342      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
343      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
344      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
345      <outfile xil_pn:name="CORE_MPI.vhd"/>
346      <outfile xil_pn:name="DEMUX1.vhd"/>
347      <outfile xil_pn:name="DMA_ARBITER.vhd"/>
348      <outfile xil_pn:name="EX1_FSM.vhd"/>
349      <outfile xil_pn:name="EX2_FSM.vhd"/>
350      <outfile xil_pn:name="EX3_FSM.vhd"/>
351      <outfile xil_pn:name="EX4_FSM.vhd"/>
352      <outfile xil_pn:name="Ex0_Fsm.vhd"/>
353      <outfile xil_pn:name="Ex5_FSM.vhd"/>
354      <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
355      <outfile xil_pn:name="FIfo_mem.vhd"/>
356      <outfile xil_pn:name="FIfo_proc.vhd"/>
357      <outfile xil_pn:name="HT_process.vhd"/>
358      <outfile xil_pn:name="Hold_FSM.vhd"/>
359      <outfile xil_pn:name="MPICORETEST.vhd"/>
360      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
361      <outfile xil_pn:name="MPI_NOC.vhd"/>
362      <outfile xil_pn:name="MPI_RMA.vhd"/>
363      <outfile xil_pn:name="MUX1.vhd"/>
364      <outfile xil_pn:name="MUX8.vhd"/>
365      <outfile xil_pn:name="MultiMPITest.vhd"/>
366      <outfile xil_pn:name="PE.vhd"/>
367      <outfile xil_pn:name="Packet_type.vhd"/>
368      <outfile xil_pn:name="RAM_32_32.vhd"/>
369      <outfile xil_pn:name="RAM_64.vhd"/>
370      <outfile xil_pn:name="SetBit.vhd"/>
371      <outfile xil_pn:name="image_pkg.vhd"/>
372      <outfile xil_pn:name="load_instr.vhd"/>
373      <outfile xil_pn:name="mpi_test.vhd"/>
374      <outfile xil_pn:name="round_robbin_machine.vhd"/>
375      <outfile xil_pn:name="sim_fifo.vhd"/>
376      <outfile xil_pn:name="test_DMA.vhd"/>
377    </transform>
378    <transform xil_pn:end_ts="1389570072" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1389570072">
379      <status xil_pn:value="SuccessfullyRun"/>
380      <status xil_pn:value="ReadyToRun"/>
381    </transform>
382    <transform xil_pn:end_ts="1389570074" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1389570072">
383      <status xil_pn:value="SuccessfullyRun"/>
384      <status xil_pn:value="ReadyToRun"/>
385    </transform>
386    <transform xil_pn:end_ts="1389726825" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="7827306417472095804" xil_pn:start_ts="1389726825">
387      <status xil_pn:value="SuccessfullyRun"/>
388      <status xil_pn:value="ReadyToRun"/>
389    </transform>
390    <transform xil_pn:end_ts="1389743130" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1389743130">
391      <status xil_pn:value="SuccessfullyRun"/>
392      <status xil_pn:value="ReadyToRun"/>
393      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
394      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
395      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd"/>
396      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd"/>
397      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd"/>
398      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd"/>
399      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd"/>
400      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd"/>
401      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd"/>
402      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD"/>
403      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD"/>
404      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD"/>
405      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD"/>
406      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD"/>
407      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD"/>
408      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD"/>
409      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD"/>
410      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD"/>
411      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD"/>
412      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD"/>
413      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD"/>
414      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD"/>
415      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD"/>
416      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD"/>
417      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd"/>
418      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd"/>
419      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd"/>
420      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd"/>
421      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd"/>
422      <outfile xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd"/>
423      <outfile xil_pn:name="CORE_MPI.vhd"/>
424      <outfile xil_pn:name="DEMUX1.vhd"/>
425      <outfile xil_pn:name="DMA_ARBITER.vhd"/>
426      <outfile xil_pn:name="EX1_FSM.vhd"/>
427      <outfile xil_pn:name="EX2_FSM.vhd"/>
428      <outfile xil_pn:name="EX3_FSM.vhd"/>
429      <outfile xil_pn:name="EX4_FSM.vhd"/>
430      <outfile xil_pn:name="Ex0_Fsm.vhd"/>
431      <outfile xil_pn:name="Ex5_FSM.vhd"/>
432      <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
433      <outfile xil_pn:name="FIfo_mem.vhd"/>
434      <outfile xil_pn:name="FIfo_proc.vhd"/>
435      <outfile xil_pn:name="HT_process.vhd"/>
436      <outfile xil_pn:name="Hold_FSM.vhd"/>
437      <outfile xil_pn:name="MPICORETEST.vhd"/>
438      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
439      <outfile xil_pn:name="MPI_NOC.vhd"/>
440      <outfile xil_pn:name="MPI_RMA.vhd"/>
441      <outfile xil_pn:name="MUX1.vhd"/>
442      <outfile xil_pn:name="MUX8.vhd"/>
443      <outfile xil_pn:name="MultiMPITest.vhd"/>
444      <outfile xil_pn:name="PE.vhd"/>
445      <outfile xil_pn:name="Packet_type.vhd"/>
446      <outfile xil_pn:name="RAM_32_32.vhd"/>
447      <outfile xil_pn:name="RAM_64.vhd"/>
448      <outfile xil_pn:name="SetBit.vhd"/>
449      <outfile xil_pn:name="image_pkg.vhd"/>
450      <outfile xil_pn:name="load_instr.vhd"/>
451      <outfile xil_pn:name="mpi_test.vhd"/>
452      <outfile xil_pn:name="round_robbin_machine.vhd"/>
453      <outfile xil_pn:name="sim_fifo.vhd"/>
454      <outfile xil_pn:name="test_DMA.vhd"/>
455    </transform>
456    <transform xil_pn:end_ts="1389743164" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-6667380628693525942" xil_pn:start_ts="1389743130">
457      <status xil_pn:value="SuccessfullyRun"/>
458      <status xil_pn:value="ReadyToRun"/>
459      <outfile xil_pn:name="mpi_test.fdo"/>
460      <outfile xil_pn:name="vsim.wlf"/>
461      <outfile xil_pn:name="work"/>
462    </transform>
463    <transform xil_pn:end_ts="1389558632" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1389558632">
464      <status xil_pn:value="SuccessfullyRun"/>
465      <status xil_pn:value="ReadyToRun"/>
466    </transform>
467    <transform xil_pn:end_ts="1389723757" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4817802592528555221" xil_pn:start_ts="1389723754">
468      <status xil_pn:value="SuccessfullyRun"/>
469      <status xil_pn:value="ReadyToRun"/>
470    </transform>
471    <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7827306417472095804" xil_pn:start_ts="1389723757">
472      <status xil_pn:value="SuccessfullyRun"/>
473      <status xil_pn:value="ReadyToRun"/>
474    </transform>
475    <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1389723757">
476      <status xil_pn:value="SuccessfullyRun"/>
477      <status xil_pn:value="ReadyToRun"/>
478    </transform>
479    <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1893960479894904659" xil_pn:start_ts="1389723757">
480      <status xil_pn:value="SuccessfullyRun"/>
481      <status xil_pn:value="ReadyToRun"/>
482    </transform>
483    <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1389723757">
484      <status xil_pn:value="SuccessfullyRun"/>
485      <status xil_pn:value="ReadyToRun"/>
486    </transform>
487    <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2122804370720789306" xil_pn:start_ts="1389723757">
488      <status xil_pn:value="SuccessfullyRun"/>
489      <status xil_pn:value="ReadyToRun"/>
490    </transform>
491    <transform xil_pn:end_ts="1389725470" xil_pn:in_ck="-8697612743778259046" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-7202030164265802586" xil_pn:start_ts="1389725338">
492      <status xil_pn:value="SuccessfullyRun"/>
493      <status xil_pn:value="WarningsGenerated"/>
494      <status xil_pn:value="ReadyToRun"/>
495      <status xil_pn:value="OutOfDateForInputs"/>
496      <status xil_pn:value="InputChanged"/>
497      <outfile xil_pn:name="CORE_MPI.lso"/>
498      <outfile xil_pn:name="CORE_MPI.ngc"/>
499      <outfile xil_pn:name="CORE_MPI.ngr"/>
500      <outfile xil_pn:name="CORE_MPI.prj"/>
501      <outfile xil_pn:name="CORE_MPI.stx"/>
502      <outfile xil_pn:name="CORE_MPI.syr"/>
503      <outfile xil_pn:name="CORE_MPI.xst"/>
504      <outfile xil_pn:name="CORE_MPI_xst.xrpt"/>
505      <outfile xil_pn:name="DMA_ARBITER.ngr"/>
506      <outfile xil_pn:name="MPI_CORE_SCHEDULER.ngr"/>
507      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
508      <outfile xil_pn:name="load_instr.ngr"/>
509      <outfile xil_pn:name="webtalk_pn.xml"/>
510      <outfile xil_pn:name="xst"/>
511    </transform>
512    <transform xil_pn:end_ts="1389723997" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3683379310506444734" xil_pn:start_ts="1389723997">
513      <status xil_pn:value="SuccessfullyRun"/>
514      <status xil_pn:value="ReadyToRun"/>
515    </transform>
516    <transform xil_pn:end_ts="1389724003" xil_pn:in_ck="-1005953262871376632" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3081276958392942983" xil_pn:start_ts="1389723997">
517      <status xil_pn:value="SuccessfullyRun"/>
518      <status xil_pn:value="ReadyToRun"/>
519      <status xil_pn:value="OutOfDateForInputs"/>
520      <status xil_pn:value="OutOfDateForPredecessor"/>
521      <status xil_pn:value="InputChanged"/>
522      <outfile xil_pn:name="CORE_MPI.bld"/>
523      <outfile xil_pn:name="CORE_MPI.ngd"/>
524      <outfile xil_pn:name="CORE_MPI_ngdbuild.xrpt"/>
525      <outfile xil_pn:name="_ngo"/>
526      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
527    </transform>
528    <transform xil_pn:end_ts="1389724025" xil_pn:in_ck="4512930838117587152" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4079613270754646221" xil_pn:start_ts="1389724003">
529      <status xil_pn:value="FailedRun"/>
530      <status xil_pn:value="ReadyToRun"/>
531      <status xil_pn:value="OutOfDateForPredecessor"/>
532      <outfile xil_pn:name="CORE_MPI_map.map"/>
533      <outfile xil_pn:name="CORE_MPI_map.mrp"/>
534      <outfile xil_pn:name="CORE_MPI_map.ngm"/>
535      <outfile xil_pn:name="CORE_MPI_map.xrpt"/>
536      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
537    </transform>
538  </transforms>
539
540</generated_project>
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