[15] | 1 | -- Package File Template |
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| 2 | -- |
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| 3 | -- Purpose: This package defines supplemental types, subtypes, |
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| 4 | -- constants, and functions |
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| 5 | |
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| 6 | |
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| 7 | library IEEE; |
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| 8 | use IEEE.STD_LOGIC_1164.all; |
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[70] | 9 | use ieee.numeric_std.all; |
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| 10 | use IEEE.STD_LOGIC_ARITH.ALL; |
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[35] | 11 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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[15] | 12 | Library NocLib; |
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| 13 | use NocLib.CoreTypes.all; |
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| 14 | use work.PACKET_TYPE.all; |
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| 15 | |
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[70] | 16 | package Mpi_Rma is |
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| 17 | procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram); |
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[15] | 18 | procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram); |
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[70] | 19 | procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; |
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| 20 | Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; |
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| 21 | Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; |
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[15] | 22 | Target_Datatype :natural; Win : natural); |
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| 23 | |
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[70] | 24 | procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; |
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| 25 | Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; |
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| 26 | Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; |
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| 27 | Target_Datatype :natural; Win : natural); |
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| 28 | procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ); |
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| 29 | |
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| 30 | procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
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| 31 | base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; |
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| 32 | info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); |
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| 33 | procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); |
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| 34 | procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); |
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[72] | 35 | procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); |
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| 36 | procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); |
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[70] | 37 | procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
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| 38 | command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; |
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| 39 | signal intercomm :out natural; signal array_of_errcodes : out natural); |
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[15] | 40 | -- declare functions and procedure |
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[70] | 41 | procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
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| 42 | AdrVect:in std_logic_vector; data: out std_logic_vector); |
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| 43 | procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
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[15] | 44 | AdrVect:in std_logic_vector; Data:in std_logic_vector); |
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[74] | 45 | |
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| 46 | procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
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| 47 | variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic); |
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| 48 | |
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[15] | 49 | end MPI_Rma; |
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| 50 | |
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| 51 | |
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| 52 | package body MPI_Rma is |
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| 53 | ----int MPI_Put( |
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| 54 | -- void *origin_addr, |
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| 55 | -- int origin_count, |
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| 56 | -- MPI_Datatype origin_datatype, |
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| 57 | -- int target_rank, |
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| 58 | -- MPI_Aint target_disp, |
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| 59 | -- int target_count, |
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| 60 | -- MPI_Datatype target_datatype, |
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| 61 | -- MPI_Win win |
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| 62 | --); |
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| 63 | -- Example 1 |
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[70] | 64 | procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; |
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| 65 | Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; |
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| 66 | Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; |
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[15] | 67 | Target_Datatype :natural; Win : natural) is |
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[72] | 68 | variable i,dcount,wr_state : natural:=0; |
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[70] | 69 | variable adresse :natural; |
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| 70 | variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; |
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[15] | 71 | variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; |
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[70] | 72 | variable put_adr : std_logic_vector (ADRLEN-1 downto 0); |
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| 73 | variable config_reg: std_logic_vector (Word-1 downto 0); |
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[15] | 74 | constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); |
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| 75 | begin |
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[72] | 76 | put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN); |
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[70] | 77 | |
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| 78 | addr1:=Orig_Addr; |
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| 79 | addr2:=Target_Disp; |
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| 80 | if NextCtx /=0 then --préserver la valeur de count entre les appels |
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| 81 | dcount:=NextCtx; |
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[15] | 82 | end if; |
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| 83 | -- |
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| 84 | |
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| 85 | if rising_edge(clkin) then |
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[72] | 86 | if dcount= 0 then |
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| 87 | dcount:=dcount+1; |
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| 88 | Interf.S.Intstate1<=0; |
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| 89 | elsif dcount>=1 and dcount <=3 then |
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[70] | 90 | if interf.I.ramsel='0' then |
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| 91 | Interf.O.membusy<='0'; |
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[74] | 92 | --SysRam.O.we<='1'; |
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| 93 | --SysRam.O.ena<='1'; |
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| 94 | SysRam.O.enb<='1'; |
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[72] | 95 | wr_state:=interf.S.Intstate1; |
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| 96 | WritePtr (put_adr,wr_state,SysRam); |
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| 97 | interf.S.Intstate1<=wr_state; |
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[74] | 98 | if wr_state =0 then |
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[70] | 99 | -- fin de l'écriture du pointeur en mémoire |
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[72] | 100 | dcount:=4; |
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[70] | 101 | end if; |
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| 102 | end if; |
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| 103 | |
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| 104 | elsif dcount=4 then |
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| 105 | if interf.I.ramsel='0' then |
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| 106 | SysRam.O.we<='1'; |
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| 107 | SysRam.O.ena<='1'; |
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| 108 | SysRam.O.enb<='0'; |
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| 109 | Interf.O.membusy<='1'; |
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[72] | 110 | if target_rank <=15 then --limitation de cete version à 16 rang |
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| 111 | Interf.S.Gstart(Target_rank)<='1'; |
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| 112 | end if; |
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[15] | 113 | adresse:=core_put_adr; |
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[72] | 114 | SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction |
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[70] | 115 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 116 | dcount:=dcount+1; |
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| 117 | end if; |
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| 118 | elsif dcount=5 then |
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| 119 | if interf.I.ramsel='0' then |
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[15] | 120 | adresse:=core_put_adr+1; |
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[70] | 121 | SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur |
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| 122 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 123 | dcount:=dcount+1; |
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| 124 | Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction |
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[39] | 125 | end if; |
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[70] | 126 | elsif dcount=6 then |
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| 127 | if interf.I.ramsel='0' then |
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[15] | 128 | adresse:=core_put_adr+2; |
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[70] | 129 | SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut |
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| 130 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 131 | dcount:=dcount+1; |
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[39] | 132 | end if; |
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[70] | 133 | elsif dcount=7 then |
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| 134 | if interf.I.ramsel='0' then |
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[15] | 135 | adresse:=core_put_adr+3; |
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[70] | 136 | SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas |
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| 137 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 138 | dcount:=dcount+1; |
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[39] | 139 | end if; |
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[70] | 140 | elsif dcount=8 then |
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| 141 | if interf.I.ramsel='0' then |
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[15] | 142 | adresse:=core_put_adr+4; |
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[70] | 143 | SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut |
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| 144 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 145 | dcount:=dcount+1; |
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[39] | 146 | end if; |
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[70] | 147 | elsif dcount=9 then |
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| 148 | if interf.I.ramsel='0' then |
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[15] | 149 | adresse:=core_put_adr+5; |
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[70] | 150 | SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas |
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| 151 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 152 | dcount:=dcount+1; |
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[39] | 153 | end if; |
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[70] | 154 | elsif dcount=10 then |
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| 155 | |
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| 156 | SysRam.O.we<='1'; |
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| 157 | SysRam.O.ena<='1'; |
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| 158 | SysRam.O.enb<='1'; |
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| 159 | if interf.I.ramsel='0' then |
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[15] | 160 | adresse:=core_base_adr+1; |
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[70] | 161 | SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); |
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| 162 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 163 | SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; |
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| 164 | Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction |
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| 165 | Interf.O.membusy<='0'; |
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| 166 | dcount:=dcount+1; |
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[39] | 167 | end if; |
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[70] | 168 | elsif dcount=11 then |
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| 169 | if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? |
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| 170 | Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction |
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| 171 | dcount:=dcount+1; |
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| 172 | config_reg:=SysRam.I.Data_out and x"f6"; |
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| 173 | SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; |
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| 174 | else |
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| 175 | Interf.O.Instr_En<='1'; |
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| 176 | end if; |
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| 177 | adresse:=core_base_adr+1; |
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| 178 | SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); |
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| 179 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 180 | --SysRam.O.Ram_busy<='0'; --?? |
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| 181 | SysRam.O.we<='0'; |
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| 182 | SysRam.O.ena<='0'; -- préparer la lecture du résultat du Put |
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| 183 | SysRam.O.enb<='1'; |
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| 184 | elsif dcount=12 then |
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| 185 | adresse:=core_base_adr+1; |
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| 186 | SysRam.O.we<='1'; |
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| 187 | SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put |
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| 188 | SysRam.O.enb<='1'; |
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| 189 | if interf.I.ramsel='0' then |
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| 190 | config_reg:=SysRam.I.Data_out and x"f6"; |
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| 191 | SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; |
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| 192 | dcount:=dcount+1; |
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| 193 | Interf.O.membusy<='1'; |
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| 194 | end if; |
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| 195 | SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); |
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| 196 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 197 | elsif dcount=13 then |
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| 198 | SysRam.O.we<='1'; |
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| 199 | SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put |
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| 200 | SysRam.O.enb<='0'; |
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| 201 | config_reg:=SysRam.I.Data_out and x"f6"; |
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| 202 | SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; |
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| 203 | dcount:=dcount+1; |
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| 204 | adresse:=core_base_adr+1; |
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| 205 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 206 | elsif dcount=14 then |
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| 207 | SysRam.O.we<='0'; |
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| 208 | SysRam.O.ena<='0'; |
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| 209 | SysRam.O.enb<='1'; |
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| 210 | Interf.O.membusy<='0'; |
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| 211 | if interf.I.ramsel='0' then |
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| 212 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); |
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| 213 | if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! |
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| 214 | dcount:=dcount+1; |
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[72] | 215 | SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); |
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[70] | 216 | Interf.S.Intstate2<=255; --timer pour la réception |
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| 217 | end if; |
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| 218 | end if; |
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| 219 | elsif dcount=15 then |
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| 220 | dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse |
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| 221 | elsif dcount=16 then |
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| 222 | if interf.I.ramsel='0' then |
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| 223 | dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse |
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| 224 | end if; |
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| 225 | elsif dcount=17 then |
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| 226 | SysRam.O.we<='0'; |
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| 227 | SysRam.O.ena<='0'; |
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| 228 | SysRam.O.enb<='1'; |
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| 229 | Interf.O.membusy<='0'; |
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| 230 | if interf.I.ramsel='0' then |
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[72] | 231 | SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); |
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[70] | 232 | if SysRam.I.Data_out(5)='1' then --Message du MPI PUT bien reçu ! |
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| 233 | dcount:=dcount+1; |
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[72] | 234 | SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); |
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[70] | 235 | elsif Interf.S.Intstate2>0 then |
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| 236 | Interf.S.Intstate2<=Interf.S.Intstate2-1; |
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| 237 | else |
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| 238 | -- dcount:=1;--recommencer l'envoi |
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| 239 | end if; |
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| 240 | end if; |
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| 241 | elsif dcount=18 then |
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| 242 | dcount:=0; --fin normale de la fonction |
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| 243 | Interf.O.membusy<='0'; |
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[15] | 244 | end if; |
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| 245 | |
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[70] | 246 | |
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| 247 | NExtCtx:=dcount; |
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[15] | 248 | end if; |
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| 249 | end procedure; |
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| 250 | |
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[70] | 251 | procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; |
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| 252 | Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; |
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| 253 | Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; |
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[15] | 254 | Target_Datatype :natural; Win : natural) is |
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[39] | 255 | variable i,wcount,dcount : natural range 0 to 255:=0; |
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[70] | 256 | variable adresse :natural; |
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[74] | 257 | variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 258 | variable bitval : std_logic:='0'; |
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[70] | 259 | variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; |
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[15] | 260 | variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; |
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[70] | 261 | variable get_adr : std_logic_vector (ADRLEN-1 downto 0); |
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| 262 | variable config_reg,win_reg: std_logic_vector (Word-1 downto 0); |
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[15] | 263 | constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); |
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| 264 | begin |
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[70] | 265 | get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN)); |
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| 266 | |
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| 267 | addr1:=Orig_Addr; |
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| 268 | addr2:=Target_Disp; |
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| 269 | if NextCtx /=0 then --préserver la valeur de count entre les appels |
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| 270 | dcount:=NextCtx; |
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[15] | 271 | end if; |
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| 272 | -- |
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| 273 | |
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| 274 | if rising_edge(clkin) then |
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[70] | 275 | |
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| 276 | if dcount =0 then |
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| 277 | dcount:=dcount+1; |
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[74] | 278 | Interf.S.IntState1<=0; |
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[70] | 279 | elsif dcount>=1 and dcount <=3 then |
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| 280 | if interf.I.ramsel='0' then |
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| 281 | SysRam.O.we<='1'; |
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| 282 | SysRam.O.ena<='1'; |
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| 283 | SysRam.O.enb<='0'; |
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| 284 | wcount:=Interf.S.IntState1; |
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| 285 | WritePtr (get_adr,wcount,SysRam); |
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| 286 | Interf.S.IntState1<=wcount; |
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| 287 | Interf.O.membusy<='1'; |
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[74] | 288 | if wcount =0 then |
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[70] | 289 | dcount:=4; |
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[72] | 290 | Interf.S.Intstate1<=1; |
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[74] | 291 | end if; |
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| 292 | else |
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| 293 | Interf.S.IntState1<=0; |
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| 294 | |
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[70] | 295 | end if; |
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| 296 | |
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| 297 | elsif dcount=4 then |
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| 298 | if interf.I.ramsel='0' then |
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| 299 | SysRam.O.we<='1'; |
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| 300 | SysRam.O.ena<='1'; |
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| 301 | SysRam.O.enb<='0'; |
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[72] | 302 | if target_rank <=15 then --limitation de cete version à 16 rang |
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| 303 | Interf.S.Gstart(Target_rank)<='1'; |
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| 304 | end if; |
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[15] | 305 | adresse:=core_get_adr; |
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[72] | 306 | SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction |
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[70] | 307 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 308 | Interf.O.membusy<='1'; |
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| 309 | dcount:=dcount+1; |
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| 310 | end if; |
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| 311 | elsif dcount=5 then |
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| 312 | if interf.I.ramsel='0' then |
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| 313 | SysRam.O.we<='1'; |
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| 314 | SysRam.O.ena<='1'; |
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[35] | 315 | adresse:=core_get_adr+1; |
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[70] | 316 | SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur |
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| 317 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 318 | interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction |
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| 319 | dcount:=dcount+1; |
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[35] | 320 | end if; |
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[70] | 321 | elsif dcount=6 then |
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| 322 | if interf.I.ramsel='0' then |
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| 323 | SysRam.O.we<='1'; |
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| 324 | SysRam.O.ena<='1'; |
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[35] | 325 | adresse:=core_get_adr+2; |
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[70] | 326 | SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut |
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| 327 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 328 | |
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| 329 | dcount:=dcount+1; |
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[74] | 330 | |
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[35] | 331 | end if; |
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[70] | 332 | elsif dcount=7 then |
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| 333 | if interf.I.ramsel='0' then |
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| 334 | SysRam.O.we<='1'; |
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| 335 | SysRam.O.ena<='1'; |
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[35] | 336 | adresse:=core_get_adr+3; |
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[70] | 337 | SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas |
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| 338 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
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| 339 | |
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| 340 | dcount:=dcount+1; |
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[35] | 341 | end if; |
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[70] | 342 | elsif dcount=8 then |
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| 343 | if interf.I.ramsel='0' then |
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| 344 | SysRam.O.we<='1'; |
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| 345 | SysRam.O.ena<='1'; |
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[35] | 346 | adresse:=core_get_adr+4; |
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[70] | 347 | SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut |
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| 348 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 349 | Interf.O.membusy<='1'; |
---|
| 350 | dcount:=dcount+1; |
---|
[35] | 351 | end if; |
---|
[70] | 352 | elsif dcount=9 then |
---|
| 353 | if interf.I.ramsel='0' then |
---|
| 354 | SysRam.O.we<='1'; |
---|
| 355 | SysRam.O.ena<='1'; |
---|
[35] | 356 | adresse:=core_get_adr+5; |
---|
[70] | 357 | SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas |
---|
| 358 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 359 | Interf.O.membusy<='1'; |
---|
[70] | 360 | dcount:=dcount+1; |
---|
[35] | 361 | end if; |
---|
[74] | 362 | elsif dcount=10 then |
---|
| 363 | if interf.I.ramsel='0' then |
---|
[70] | 364 | SysRam.O.we<='1'; |
---|
| 365 | SysRam.O.ena<='1'; |
---|
[74] | 366 | adresse:=core_get_adr+7; |
---|
| 367 | SysRam.O.Data_in<=x"00"; -- résultat du GET |
---|
[70] | 368 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 369 | Interf.O.membusy<='1'; |
---|
| 370 | Interf.S.IntState2<=0; |
---|
[70] | 371 | dcount:=dcount+1; |
---|
[35] | 372 | end if; |
---|
[70] | 373 | elsif dcount=11 then |
---|
[74] | 374 | |
---|
| 375 | SysRam.O.we<='1'; |
---|
| 376 | SysRam.O.ena<='1'; |
---|
| 377 | SysRam.O.enb<='1'; |
---|
| 378 | addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); |
---|
| 379 | wcount:=Interf.S.IntState2; |
---|
| 380 | wdata:=x"01";bitval:='1'; |
---|
| 381 | setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval); |
---|
| 382 | Interf.S.IntState2<=wcount; |
---|
| 383 | if wcount=0 then |
---|
| 384 | dcount:=dcount+1; |
---|
| 385 | Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction |
---|
| 386 | end if; |
---|
| 387 | |
---|
| 388 | elsif dcount=12 then |
---|
[70] | 389 | if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? |
---|
| 390 | Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction |
---|
| 391 | dcount:=dcount+1; |
---|
| 392 | config_reg:=SysRam.I.Data_out and x"f6"; |
---|
[74] | 393 | --SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; |
---|
[70] | 394 | end if; |
---|
| 395 | adresse:=core_base_adr+1; |
---|
[74] | 396 | SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[70] | 397 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 398 | --SysRam.O.Ram_busy<='0'; --?? |
---|
| 399 | SysRam.O.we<='0'; |
---|
| 400 | SysRam.O.ena<='0'; -- préparer la lecture du résultat du get |
---|
| 401 | SysRam.O.enb<='1'; |
---|
| 402 | Interf.O.membusy<='0'; |
---|
[74] | 403 | elsif dcount=13 then |
---|
[70] | 404 | |
---|
| 405 | adresse:=core_base_adr+1; |
---|
| 406 | SysRam.O.we<='1'; |
---|
| 407 | SysRam.O.ena<='1'; -- préparer l'écriture du résultat du get |
---|
| 408 | SysRam.O.enb<='1'; |
---|
[74] | 409 | SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 410 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 411 | |
---|
[70] | 412 | if interf.I.ramsel='0' then |
---|
| 413 | config_reg:=SysRam.I.Data_out and x"f6"; |
---|
| 414 | SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; |
---|
| 415 | dcount:=dcount+1; |
---|
| 416 | Interf.O.membusy<='1'; |
---|
| 417 | end if; |
---|
[74] | 418 | |
---|
| 419 | elsif dcount=14 then |
---|
[70] | 420 | |
---|
| 421 | SysRam.O.we<='1'; |
---|
| 422 | SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET |
---|
| 423 | SysRam.O.enb<='0'; |
---|
| 424 | adresse:=core_base_adr+1; |
---|
| 425 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 426 | if interf.I.ramsel='0' then |
---|
| 427 | config_reg:=SysRam.I.Data_out and x"f6"; |
---|
| 428 | SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; |
---|
[74] | 429 | dcount:=18;--dcount+1; |
---|
| 430 | Interf.O.membusy<='1'; |
---|
| 431 | |
---|
| 432 | end if; |
---|
| 433 | elsif dcount=15 then |
---|
| 434 | |
---|
| 435 | SysRam.O.we<='0'; |
---|
| 436 | SysRam.O.ena<='0'; -- préparer l'écriture du WBusy |
---|
| 437 | SysRam.O.enb<='1'; |
---|
| 438 | adresse:=core_base_adr+5; |
---|
| 439 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 440 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 441 | |
---|
| 442 | if interf.I.ramsel='0' then |
---|
| 443 | config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy |
---|
| 444 | SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy |
---|
[70] | 445 | dcount:=dcount+1; |
---|
[74] | 446 | Interf.O.membusy<='1'; |
---|
[70] | 447 | end if; |
---|
[74] | 448 | elsif dcount=16 then |
---|
| 449 | |
---|
| 450 | SysRam.O.we<='0'; |
---|
| 451 | SysRam.O.ena<='0'; -- préparer l'écriture du WBusy |
---|
| 452 | SysRam.O.enb<='1'; |
---|
| 453 | adresse:=core_base_adr+5; |
---|
| 454 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 455 | if interf.I.ramsel='0' then |
---|
| 456 | config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy |
---|
| 457 | SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy |
---|
| 458 | dcount:=dcount+1; |
---|
| 459 | Interf.O.membusy<='1'; |
---|
| 460 | |
---|
| 461 | end if; |
---|
| 462 | elsif dcount=17 then |
---|
| 463 | |
---|
| 464 | SysRam.O.we<='1'; |
---|
| 465 | SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET |
---|
| 466 | SysRam.O.enb<='1'; |
---|
| 467 | adresse:=core_base_adr+5; |
---|
| 468 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 469 | if interf.I.ramsel='0' then |
---|
| 470 | config_reg:=SysRam.I.Data_out or x"40"; |
---|
| 471 | SysRam.O.Data_in<=config_reg ; --; |
---|
| 472 | dcount:=dcount+1; |
---|
| 473 | Interf.O.membusy<='1'; |
---|
| 474 | end if; |
---|
| 475 | elsif dcount>=18 and dcount <=21 then |
---|
[70] | 476 | SysRam.O.we<='0'; |
---|
| 477 | SysRam.O.ena<='0'; |
---|
| 478 | SysRam.O.enb<='1'; |
---|
| 479 | Interf.O.membusy<='0'; |
---|
| 480 | if interf.I.ramsel='0' then |
---|
| 481 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); |
---|
| 482 | if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! |
---|
| 483 | dcount:=dcount+1; |
---|
| 484 | end if; |
---|
| 485 | end if; |
---|
[74] | 486 | elsif dcount>=22 and dcount <=24 then |
---|
| 487 | SysRam.O.we<='0'; |
---|
| 488 | SysRam.O.ena<='0'; |
---|
| 489 | SysRam.O.enb<='1'; |
---|
| 490 | Interf.O.membusy<='0'; |
---|
| 491 | SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); |
---|
| 492 | if interf.I.ramsel='0' then |
---|
| 493 | SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); |
---|
| 494 | if SysRam.I.Data_out(5)='1' then --Message du MPI Get bien reçu ! |
---|
| 495 | dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème ! |
---|
| 496 | SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); |
---|
| 497 | elsif Interf.S.Intstate2>0 then |
---|
| 498 | Interf.S.Intstate2<=Interf.S.Intstate2-1; |
---|
| 499 | else |
---|
| 500 | -- dcount:=1;--recommencer l'envoi |
---|
| 501 | end if; |
---|
| 502 | end if; |
---|
[70] | 503 | |
---|
[74] | 504 | elsif dcount=25 then |
---|
[70] | 505 | dcount:=0; --fin normale de la fonction |
---|
| 506 | Interf.O.membusy<='0'; |
---|
[74] | 507 | SysRam.O.we<='0'; |
---|
| 508 | SysRam.O.ena<='0'; |
---|
| 509 | SysRam.O.enb<='0'; |
---|
[15] | 510 | end if; |
---|
[74] | 511 | |
---|
[70] | 512 | NExtCtx:=dcount; |
---|
[39] | 513 | end if; |
---|
[15] | 514 | end procedure; |
---|
[70] | 515 | Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is |
---|
| 516 | Begin |
---|
| 517 | --cette procédure permet de récupérer le groupe qui est associé à un communicateur |
---|
| 518 | --dans notre cas c'est la récupération du groupe associé à COMM_WORLD |
---|
| 519 | end procedure; |
---|
[15] | 520 | --int MPI_Group_incl(MPI_Group group, int n, int *ranks, |
---|
[70] | 521 | -- MPI_Group *newgroup) |
---|
| 522 | Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; |
---|
| 523 | GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is |
---|
| 524 | Begin |
---|
| 525 | -- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks |
---|
| 526 | -- et d'activer l'un des bits de position de newgroup. |
---|
| 527 | -- |
---|
| 528 | -- |
---|
| 529 | end procedure; |
---|
| 530 | |
---|
| 531 | procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is |
---|
| 532 | variable adresse_rd : natural range 0 to 2**ADRLEN-1; |
---|
| 533 | |
---|
| 534 | begin |
---|
| 535 | |
---|
| 536 | if NextCtx =0 then |
---|
| 537 | SysRam.O.we<='0'; |
---|
| 538 | SysRam.O.ena<='0'; |
---|
| 539 | SysRam.O.enb<='1'; |
---|
| 540 | adresse_rd:=CORE_INIT_ADR+1; |
---|
| 541 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); |
---|
| 542 | |
---|
| 543 | NextCtx:=1; |
---|
| 544 | |
---|
| 545 | elsif NextCtx=1 then |
---|
| 546 | SysRam.O.we<='0'; |
---|
| 547 | SysRam.O.ena<='0'; |
---|
| 548 | SysRam.O.enb<='1'; |
---|
| 549 | adresse_rd:=CORE_INIT_ADR+1; |
---|
| 550 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); |
---|
| 551 | if interf.I.ramsel='0' then |
---|
| 552 | Rank<=SysRam.I.Data_out(3 downto 0); |
---|
| 553 | NextCtx:=2; |
---|
| 554 | Interf.O.membusy<='1'; |
---|
| 555 | end if; |
---|
| 556 | elsif NextCtx=2 then |
---|
| 557 | SysRam.O.we<='0'; |
---|
| 558 | SysRam.O.ena<='0'; |
---|
| 559 | SysRam.O.enb<='1'; |
---|
| 560 | adresse_rd:=CORE_INIT_ADR+1; |
---|
| 561 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); |
---|
| 562 | if interf.I.ramsel='0' then |
---|
| 563 | Rank<=SysRam.I.Data_out(3 downto 0); |
---|
[72] | 564 | Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); |
---|
[70] | 565 | NextCtx:=3; |
---|
| 566 | Interf.O.membusy<='1'; |
---|
| 567 | end if; |
---|
| 568 | elsif NextCtx=3 then |
---|
| 569 | SysRam.O.we<='0'; |
---|
| 570 | SysRam.O.ena<='0'; |
---|
| 571 | SysRam.O.enb<='1'; |
---|
| 572 | adresse_rd:=CORE_INIT_ADR+1; |
---|
| 573 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); |
---|
| 574 | if interf.I.ramsel='0' then |
---|
| 575 | Rank<=SysRam.I.Data_out(3 downto 0); |
---|
[74] | 576 | Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); |
---|
[70] | 577 | NextCtx:=4; |
---|
| 578 | Interf.O.membusy<='1'; |
---|
| 579 | end if; |
---|
| 580 | elsif NextCtx=4 then |
---|
| 581 | SysRam.O.we<='0'; |
---|
| 582 | SysRam.O.ena<='0'; |
---|
| 583 | SysRam.O.enb<='1'; |
---|
| 584 | adresse_rd:=CORE_INIT_ADR+1; |
---|
| 585 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); |
---|
| 586 | if interf.I.ramsel='0' then |
---|
| 587 | Rank<=SysRam.I.Data_out(3 downto 0); |
---|
[74] | 588 | Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); |
---|
[70] | 589 | NextCtx:=0; |
---|
| 590 | Interf.O.membusy<='0'; |
---|
| 591 | end if; |
---|
| 592 | end if; |
---|
| 593 | end procedure; |
---|
| 594 | |
---|
[15] | 595 | --int MPI_Win_create( |
---|
| 596 | -- void *base, |
---|
| 597 | -- MPI_Aint size, |
---|
| 598 | -- int disp_unit, |
---|
| 599 | -- MPI_Info info, |
---|
| 600 | -- MPI_Comm comm, |
---|
| 601 | -- MPI_Win *win |
---|
[70] | 602 | --); |
---|
| 603 | procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
---|
| 604 | base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; |
---|
| 605 | info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is |
---|
| 606 | -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre |
---|
| 607 | -- si fenêtre libre trouvée, et |
---|
| 608 | -- mise à 1 du Bit WCreate du registre status |
---|
| 609 | type wtype is array (1 to 4 ) of natural range 0 to 255; |
---|
| 610 | variable AdrWin: std_logic_vector(ADRLEN-1 downto 0); |
---|
| 611 | variable adresse : std_logic_vector(ADRLEN-1 downto 0); |
---|
| 612 | variable clkin : std_logic:='1'; |
---|
| 613 | variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN)); |
---|
| 614 | variable w0 : std_logic_vector(Word-1 downto 0); |
---|
| 615 | variable adrnat : natural; |
---|
| 616 | variable sizewin : std_logic_vector(Word-1 downto 0); |
---|
| 617 | variable count : natural range 0 to 255; |
---|
| 618 | variable wdisp :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre |
---|
| 619 | begin |
---|
| 620 | -- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner |
---|
| 621 | -- le pointeur qui permet de le décrire |
---|
| 622 | |
---|
| 623 | |
---|
| 624 | If NextCtx=0 then |
---|
| 625 | NExtCtx:=NextCtx+1; |
---|
| 626 | count:=0; |
---|
| 627 | Interf.O.membusy<='0'; |
---|
| 628 | Interf.S.IntState1<=count; |
---|
| 629 | elsif NextCtx>=1 and NextCtx <= 4 then |
---|
| 630 | count:=Interf.S.IntState1; |
---|
| 631 | AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16)); |
---|
| 632 | readmem(count,interf,sysRam,AdrWin,w0); |
---|
| 633 | if count=0 then |
---|
| 634 | if w0(0)/='1' then -- cette fenêtre est libre |
---|
| 635 | NextCtx:=6; --étape de la création de la fenêtre |
---|
| 636 | Win.addr:=base; --l'adresse de la fenêtre |
---|
| 637 | Win.id:=NextCtx; -- la référence provisoire de la fenêtre |
---|
| 638 | Win.size:=Size; -- la taille de la fenêtre |
---|
| 639 | |
---|
| 640 | else |
---|
| 641 | NextCtx:=NextCtx+1; |
---|
| 642 | end if; |
---|
| 643 | end if; |
---|
| 644 | Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure |
---|
| 645 | |
---|
| 646 | elsif NextCtx=5 then |
---|
| 647 | -- Plus de fenêtre disponible erreur |
---|
| 648 | NextCtx:=1; -- boucle sans fin :) |
---|
| 649 | Win.id:=0; |
---|
| 650 | Win.addr:=x"0000"; |
---|
| 651 | elsif NextCtx=6 then |
---|
| 652 | --Affectation de l'objet Windows car une place est disponible |
---|
| 653 | count:=Interf.S.IntState1; |
---|
| 654 | AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); |
---|
| 655 | Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created |
---|
| 656 | Interf.S.IntState1<=count; |
---|
| 657 | if count=0 then |
---|
| 658 | NextCtx:=NextCtx+1; |
---|
| 659 | end if; |
---|
| 660 | |
---|
| 661 | elsif NextCtx=8 then |
---|
| 662 | AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); |
---|
| 663 | interf.S.winid<=interf.S.winid+1; |
---|
| 664 | count:=Interf.S.IntState1; |
---|
| 665 | Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre |
---|
| 666 | Interf.S.IntState1<=count; |
---|
| 667 | if count=0 then |
---|
| 668 | NextCtx:=NextCtx+1; |
---|
| 669 | end if; |
---|
| 670 | elsif NextCtx=9 then |
---|
| 671 | |
---|
| 672 | adrnat:=Core_base_adr+Wdisp(Win.id); |
---|
| 673 | |
---|
| 674 | AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); |
---|
| 675 | count:=Interf.S.IntState1; |
---|
| 676 | |
---|
| 677 | |
---|
| 678 | Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse |
---|
| 679 | Interf.S.IntState1<=count; |
---|
| 680 | if count=0 then |
---|
| 681 | NextCtx:=NextCtx+1; |
---|
| 682 | end if; |
---|
| 683 | elsif NextCtx=10 then |
---|
| 684 | AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); |
---|
| 685 | count:=Interf.S.IntState1; |
---|
| 686 | Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute |
---|
| 687 | Interf.S.IntState1<=count; |
---|
| 688 | if count=0 then |
---|
| 689 | NextCtx:=NextCtx+1; |
---|
| 690 | end if; |
---|
| 691 | elsif NextCtx=11 then |
---|
| 692 | AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); |
---|
| 693 | sizewin:=std_logic_vector(to_unsigned(size,8)); |
---|
| 694 | count:=Interf.S.IntState1; |
---|
| 695 | Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre |
---|
| 696 | Interf.S.IntState1<=count; |
---|
| 697 | if count=0 then |
---|
| 698 | NextCtx:=NextCtx+1; |
---|
| 699 | end if; |
---|
| 700 | elsif NextCtx=12 then |
---|
| 701 | --cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer |
---|
| 702 | -- les informations donnant le numéro de la fenêtre |
---|
[72] | 703 | W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction |
---|
[70] | 704 | count:=Interf.S.IntState1; |
---|
| 705 | Writemem(count,interf,SysRam,wcreate_adr,w0); |
---|
| 706 | Interf.S.IntState1<=count; |
---|
| 707 | if count=0 then |
---|
| 708 | NextCtx:=NextCtx+1; |
---|
| 709 | end if; |
---|
| 710 | |
---|
| 711 | elsif NextCtx=13 then |
---|
[35] | 712 | w0:=std_logic_vector(to_unsigned(Win.Id,8)); -- id proposé pour la fenêtre en création |
---|
[70] | 713 | count:=Interf.S.IntState1; |
---|
| 714 | Writemem(count,interf,SysRam,wcreate_adr+1,w0); |
---|
| 715 | Interf.S.IntState1<=count; |
---|
| 716 | if count=0 then |
---|
| 717 | NextCtx:=NextCtx+1; |
---|
[15] | 718 | end if; |
---|
[70] | 719 | elsif NextCtx=14 then |
---|
| 720 | SysRam.O.we<='1'; |
---|
| 721 | SysRam.O.ena<='1'; |
---|
| 722 | SysRam.O.enb<='0'; |
---|
| 723 | count:=Interf.S.IntState1; |
---|
| 724 | if interf.I.ramsel='0' then |
---|
| 725 | WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction |
---|
| 726 | Interf.S.IntState1<=count; |
---|
| 727 | if count=0 then |
---|
| 728 | NextCtx:=NextCtx+1; |
---|
| 729 | end if; |
---|
[15] | 730 | end if; |
---|
| 731 | elsif NextCtx=15 then |
---|
[70] | 732 | -- il faut mettre instruction_en à 1 |
---|
| 733 | SysRam.O.we<='0'; |
---|
| 734 | SysRam.O.ena<='0'; |
---|
| 735 | SysRam.O.enb<='1'; |
---|
| 736 | SysRam.O.we<='1'; |
---|
| 737 | SysRam.O.ena<='1'; |
---|
| 738 | SysRam.O.enb<='1'; |
---|
[15] | 739 | adresse:=stdlv(core_base_adr+1); |
---|
[70] | 740 | SysRam.O.addr_rd<=adresse; |
---|
| 741 | SysRam.O.Addr_wr<=adresse; |
---|
| 742 | SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; |
---|
| 743 | Writemem(count,interf,SysRam,adresse,x"01"); |
---|
| 744 | Interf.S.IntState1<=count; |
---|
| 745 | if count=0 then |
---|
| 746 | NextCtx:=NextCtx+1; |
---|
| 747 | end if; |
---|
| 748 | Interf.O.Instr_En<='1'; |
---|
| 749 | adresse:=stdlv(core_base_adr); |
---|
| 750 | SysRam.O.Addr_rd<=adresse; |
---|
| 751 | NextCtx:=NextCtx+1; |
---|
| 752 | elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib |
---|
| 753 | if Interf.I.Instr_ack='1' then |
---|
| 754 | Interf.O.Instr_En<='0'; |
---|
| 755 | NextCtx:=NextCtx+1; |
---|
| 756 | end if; |
---|
| 757 | SysRam.O.we<='0'; |
---|
| 758 | SysRam.O.ena<='0'; |
---|
| 759 | SysRam.O.enb<='1'; |
---|
| 760 | elsif NextCtx=17 then |
---|
| 761 | -- lecture du résultat de l'instruction |
---|
| 762 | |
---|
| 763 | |
---|
| 764 | else |
---|
| 765 | |
---|
| 766 | end if; |
---|
| 767 | end procedure; |
---|
[15] | 768 | --int MPI_Win_start( |
---|
| 769 | -- MPI_Group group, |
---|
| 770 | -- int assert, |
---|
| 771 | -- MPI_Win win |
---|
| 772 | --); |
---|
[70] | 773 | procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is |
---|
| 774 | --cette fonction active les bits WStart pour chaque processus avec lequel |
---|
| 775 | -- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à |
---|
| 776 | --chacune de ces cibles |
---|
| 777 | variable dcount : natural range 0 to 255:=0; |
---|
| 778 | variable cstatus : std_logic_vector(Word-1 downto 0); |
---|
| 779 | begin |
---|
| 780 | |
---|
| 781 | -- retour de l'adresse de de la fenêtre dans la structure Win |
---|
| 782 | -- initialisation des bits concernant |
---|
| 783 | |
---|
| 784 | if NextCtx =0 then |
---|
| 785 | NextCtx:=NextCtx+1; |
---|
| 786 | elsif NextCtx=1 then |
---|
| 787 | if interf.I.ramsel='0' then |
---|
| 788 | SysRam.O.we<='1'; |
---|
| 789 | SysRam.O.ena<='1'; |
---|
| 790 | SysRam.O.enb<='0'; |
---|
[72] | 791 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); |
---|
[70] | 792 | SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits |
---|
| 793 | |
---|
| 794 | NextCtx:=NextCtx+1; |
---|
| 795 | Interf.O.membusy<='1'; |
---|
[72] | 796 | Interf.S.GStart<=(others=>'0'); |
---|
[70] | 797 | end if; |
---|
| 798 | elsif NextCtx=2 then |
---|
| 799 | if interf.I.ramsel='0' then |
---|
| 800 | SysRam.O.we<='1'; |
---|
| 801 | SysRam.O.ena<='1'; |
---|
| 802 | SysRam.O.enb<='0'; |
---|
[72] | 803 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); |
---|
[70] | 804 | SysRam.O.Data_in<=x"01"; |
---|
| 805 | NextCtx:=NextCtx+1; |
---|
[74] | 806 | Interf.O.membusy<='1'; |
---|
[70] | 807 | end if; |
---|
[74] | 808 | elsif NextCtx=3 then |
---|
| 809 | if interf.I.ramsel='0' then |
---|
| 810 | SysRam.O.we<='1'; |
---|
| 811 | SysRam.O.ena<='1'; |
---|
| 812 | SysRam.O.enb<='0'; |
---|
| 813 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); |
---|
| 814 | SysRam.O.Data_in<=x"01"; |
---|
| 815 | NextCtx:=NextCtx+1; |
---|
| 816 | Interf.O.membusy<='1'; |
---|
| 817 | end if; |
---|
| 818 | elsif NextCtx=4 then |
---|
[70] | 819 | NextCtx:=0; |
---|
| 820 | Interf.O.membusy<='0'; |
---|
[74] | 821 | SysRam.O.we<='0'; |
---|
| 822 | SysRam.O.ena<='0'; |
---|
[70] | 823 | end if; |
---|
| 824 | |
---|
| 825 | |
---|
| 826 | end procedure; |
---|
| 827 | procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is |
---|
[72] | 828 | variable adresse :natural; |
---|
| 829 | variable wcount: natural range 0 to 255:=0; |
---|
| 830 | variable LRam : typ_dpRam; |
---|
[74] | 831 | variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation |
---|
[72] | 832 | variable W0 :std_logic_vector(Word-1 downto 0); |
---|
| 833 | variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); |
---|
| 834 | |
---|
[70] | 835 | begin |
---|
[72] | 836 | -- |
---|
| 837 | wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); |
---|
| 838 | LRam:=SysRam; -- nécessaire pour le débogage |
---|
| 839 | if NextCtx =0 then |
---|
| 840 | |
---|
[74] | 841 | SysRam.O.we<='0'; |
---|
| 842 | SysRam.O.ena<='0'; |
---|
[72] | 843 | SysRam.O.enb<='0'; |
---|
[74] | 844 | Interf.O.MemBusy<='1'; --occuper la mémoire |
---|
[72] | 845 | Interf.S.IntState1<=0; |
---|
| 846 | NextCtx:=1; |
---|
| 847 | adresse:=core_wcompl_adr; |
---|
| 848 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 849 | Interf.O.Instr_En<='0'; |
---|
| 850 | |
---|
| 851 | elsif NextCtx=1 then --écriture du ptr d'intruction |
---|
| 852 | SysRam.O.we<='1'; |
---|
| 853 | SysRam.O.ena<='1'; |
---|
| 854 | SysRam.O.enb<='0'; |
---|
| 855 | if interf.I.ramsel='0' then |
---|
| 856 | |
---|
| 857 | adresse:=core_wcompl_adr; |
---|
| 858 | |
---|
| 859 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 860 | Interf.O.Instr_En<='0'; |
---|
| 861 | Interf.O.membusy<='1'; |
---|
[74] | 862 | SysRam.O.we<='1'; |
---|
| 863 | SysRam.O.ena<='1'; |
---|
[72] | 864 | wcount:=Interf.S.IntState1; |
---|
[74] | 865 | WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir |
---|
[72] | 866 | Interf.S.IntState1<=wcount; |
---|
| 867 | |
---|
[74] | 868 | if wcount =0 then |
---|
[72] | 869 | NextCtx:=2; |
---|
| 870 | Interf.S.IntState1<=0; |
---|
| 871 | Interf.S.IntState2<=0; |
---|
| 872 | Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées |
---|
| 873 | Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées |
---|
| 874 | adresse:=core_wcompl_adr; |
---|
| 875 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 876 | end if; |
---|
| 877 | else |
---|
| 878 | Interf.S.IntState1<=0; --recommencer l'écriture du pointeur |
---|
[72] | 879 | end if; |
---|
| 880 | elsif NextCtx=2 then |
---|
[74] | 881 | if Interf.I.Ramsel='0' then |
---|
[72] | 882 | SysRam.O.we<='1'; |
---|
| 883 | SysRam.O.ena<='1'; |
---|
| 884 | SysRam.O.enb<='0'; |
---|
[74] | 885 | Interf.O.membusy<='1'; |
---|
[72] | 886 | adresse:=core_wcompl_adr; |
---|
[74] | 887 | NextCtx:=10; --aller à la fin de la fonction |
---|
| 888 | i:=0; |
---|
| 889 | l1:for i in 0 to 7 loop |
---|
| 890 | -- i:=i+1; |
---|
| 891 | if i>=interf.s.intState2 then |
---|
[72] | 892 | if interf.s.gstart(i)='1' then |
---|
| 893 | SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); |
---|
[74] | 894 | Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); |
---|
| 895 | |
---|
[72] | 896 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 897 | Interf.S.tmem(0)(i)<='0'; --ce dest a été traité ! |
---|
[74] | 898 | NextCtx:=4; |
---|
[72] | 899 | Interf.S.IntState2<=i+1; |
---|
[74] | 900 | exit l1; |
---|
[72] | 901 | end if; |
---|
[74] | 902 | end if; |
---|
| 903 | exit l1 when i=7; |
---|
| 904 | end loop l1; |
---|
| 905 | end if; |
---|
[72] | 906 | elsif NextCtx=3 then |
---|
[74] | 907 | if interf.I.ramsel='0' then |
---|
[72] | 908 | SysRam.O.we<='1'; |
---|
| 909 | SysRam.O.ena<='1'; |
---|
| 910 | SysRam.O.enb<='0'; |
---|
[74] | 911 | Interf.O.membusy<='1'; |
---|
| 912 | adresse:=core_wcompl_adr; |
---|
| 913 | wcount:=Interf.S.IntState1; |
---|
| 914 | WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir |
---|
| 915 | Interf.S.IntState1<=wcount; |
---|
| 916 | SysRam.O.Data_in<= Interf.S.tmem(2); |
---|
| 917 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 918 | if wcount=0 then |
---|
| 919 | NextCtx:=NextCtx+1; |
---|
| 920 | end if; |
---|
| 921 | end if; |
---|
| 922 | elsif NextCtx=4 then |
---|
| 923 | SysRam.O.we<='1'; |
---|
| 924 | SysRam.O.ena<='1'; |
---|
| 925 | SysRam.O.enb<='0'; |
---|
| 926 | Interf.O.membusy<='1'; |
---|
[72] | 927 | adresse:=core_wcompl_adr+1; |
---|
| 928 | SysRam.O.Data_in<= x"04" ; |
---|
| 929 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 930 | NextCtx:=NextCtx+1; |
---|
[74] | 931 | elsif NextCtx=5 then |
---|
[72] | 932 | SysRam.O.we<='1'; |
---|
| 933 | SysRam.O.ena<='1'; |
---|
| 934 | SysRam.O.enb<='0'; |
---|
[74] | 935 | Interf.O.membusy<='1'; |
---|
[72] | 936 | adresse:=core_wcompl_adr+2; |
---|
| 937 | Interf.O.Instruction<=x"04";--longueur de l'instruction |
---|
| 938 | SysRam.O.Data_in<=x"00" ;-- |
---|
| 939 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 940 | NextCtx:=6; |
---|
| 941 | elsif NextCtx=6 then |
---|
[72] | 942 | SysRam.O.we<='1'; |
---|
| 943 | SysRam.O.ena<='1'; |
---|
| 944 | SysRam.O.enb<='0'; |
---|
[74] | 945 | Interf.O.membusy<='1'; |
---|
[72] | 946 | adresse:=core_wcompl_adr+3; |
---|
| 947 | SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); |
---|
| 948 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 949 | NextCtx:=7; |
---|
| 950 | elsif NextCtx=7 then |
---|
[72] | 951 | SysRam.O.we<='1'; |
---|
| 952 | SysRam.O.ena<='1'; |
---|
| 953 | SysRam.O.enb<='0'; |
---|
| 954 | adresse:=core_wcompl_adr+3; |
---|
| 955 | SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); |
---|
| 956 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 957 | NextCtx:=NextCtx+1; |
---|
[70] | 958 | |
---|
[74] | 959 | elsif NextCtx=8 then --fin de la fonction |
---|
[72] | 960 | SysRam.O.we<='0'; |
---|
| 961 | SysRam.O.ena<='0'; |
---|
| 962 | SysRam.O.enb<='1'; |
---|
| 963 | --dcount:=0; |
---|
| 964 | Interf.O.membusy<='0'; |
---|
| 965 | Interf.O.Instr_En<='1'; |
---|
| 966 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen)); |
---|
[74] | 967 | NextCtx:=NextCtx+1; |
---|
| 968 | elsif NextCtx=9 then --acquittement de la copie des données dans le tampon |
---|
[72] | 969 | if Interf.I.Instr_ack='1' then |
---|
| 970 | Interf.O.Instr_En<='0'; |
---|
[74] | 971 | NextCtx:=10; |
---|
[72] | 972 | end if; |
---|
| 973 | SysRam.O.we<='0'; |
---|
| 974 | SysRam.O.ena<='0'; |
---|
| 975 | SysRam.O.enb<='1'; |
---|
| 976 | |
---|
[74] | 977 | elsif NextCtx=10 then --lecture de la fin de WComplete |
---|
[72] | 978 | SysRam.O.we<='0'; |
---|
| 979 | SysRam.O.ena<='0'; |
---|
| 980 | SysRam.O.enb<='1'; |
---|
| 981 | |
---|
| 982 | if interf.S.IntState2=0 then --aucune instruction MPI exécutée ? |
---|
| 983 | |
---|
| 984 | elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer |
---|
| 985 | NextCtx:=2; |
---|
| 986 | elsif Interf.S.tmem(0)=0 then |
---|
| 987 | if interf.I.ramsel='0' then |
---|
[74] | 988 | NextCtx:=NextCtx+1; |
---|
[72] | 989 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); |
---|
| 990 | end if; |
---|
| 991 | end if; |
---|
[74] | 992 | elsif NextCtx=11 then --test de la fin des transferts |
---|
[72] | 993 | if interf.I.ramsel='0' then |
---|
| 994 | SysRam.O.we<='0'; |
---|
| 995 | SysRam.O.ena<='0'; |
---|
| 996 | SysRam.O.enb<='1'; |
---|
| 997 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); |
---|
| 998 | if SysRam.I.Data_out(0)='1' and SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0 |
---|
| 999 | --il faut un DSent=1 pour Put ou un DSending pour Get |
---|
| 1000 | if SysRam.I.Data_out(5)='1' or (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1') then |
---|
| 1001 | NextCtx:=NextCtx+1; |
---|
| 1002 | end if; |
---|
| 1003 | end if; |
---|
| 1004 | |
---|
| 1005 | end if; |
---|
[74] | 1006 | elsif NextCtx=12 then |
---|
[72] | 1007 | Interf.S.IntState1<=0; -- initialisation du compteur d'état |
---|
| 1008 | Interf.S.IntState2<=0; |
---|
[74] | 1009 | SysRam.O.enb<='0'; |
---|
[72] | 1010 | NextCtx:=0; --fin de la fonction |
---|
| 1011 | end if; |
---|
| 1012 | |
---|
[70] | 1013 | end procedure; |
---|
| 1014 | procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is |
---|
| 1015 | --cette fonction active les bits WStart pour chaque processus avec lequel |
---|
| 1016 | -- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à |
---|
| 1017 | --chacune de ces cibles |
---|
[72] | 1018 | variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire |
---|
| 1019 | variable dcount : natural range 0 to 255:=0; |
---|
| 1020 | variable cstatus : std_logic_vector(Word-1 downto 0); |
---|
[70] | 1021 | begin |
---|
[72] | 1022 | |
---|
| 1023 | -- retour de l'adresse de de la fenêtre dans la structure Win |
---|
| 1024 | -- initialisation des bits concernant |
---|
| 1025 | if Win.id =0 then |
---|
| 1026 | W_ptr:=Core_Base_Adr+4; |
---|
| 1027 | end if; |
---|
| 1028 | if NextCtx =0 then |
---|
[74] | 1029 | |
---|
[72] | 1030 | if pgroup.grp=0 then --rien à faire |
---|
| 1031 | nextCtx:=5; |
---|
| 1032 | Interf.S.GPost<=(others=>'0'); |
---|
[74] | 1033 | else |
---|
| 1034 | NextCtx:=NextCtx+1; |
---|
[72] | 1035 | end if; |
---|
| 1036 | elsif NextCtx=1 then |
---|
| 1037 | if interf.I.ramsel='0' then |
---|
| 1038 | SysRam.O.we<='1'; |
---|
| 1039 | SysRam.O.ena<='1'; |
---|
| 1040 | SysRam.O.enb<='0'; |
---|
| 1041 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); |
---|
| 1042 | SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits |
---|
| 1043 | |
---|
| 1044 | NextCtx:=NextCtx+1; |
---|
| 1045 | Interf.O.membusy<='1'; |
---|
| 1046 | |
---|
| 1047 | end if; |
---|
| 1048 | --limitation de cete version à 16 rang |
---|
| 1049 | Interf.S.GPost<=pgroup.grp; |
---|
| 1050 | elsif NextCtx=2 then |
---|
| 1051 | if interf.I.ramsel='0' then |
---|
| 1052 | SysRam.O.we<='1'; |
---|
| 1053 | SysRam.O.ena<='1'; |
---|
| 1054 | SysRam.O.enb<='0'; |
---|
| 1055 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); |
---|
| 1056 | SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits |
---|
| 1057 | |
---|
| 1058 | NextCtx:=NextCtx+1; |
---|
| 1059 | Interf.O.membusy<='1'; |
---|
| 1060 | |
---|
| 1061 | end if; |
---|
| 1062 | elsif NextCtx=3 then |
---|
| 1063 | if interf.I.ramsel='0' then |
---|
| 1064 | SysRam.O.we<='1'; |
---|
| 1065 | SysRam.O.ena<='1'; |
---|
| 1066 | SysRam.O.enb<='0'; |
---|
| 1067 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen)); |
---|
| 1068 | SysRam.O.Data_in<=pgroup.grp(7 downto 0); |
---|
| 1069 | NextCtx:=NextCtx+1; |
---|
| 1070 | Interf.O.membusy<='1'; |
---|
| 1071 | end if; |
---|
| 1072 | elsif NextCtx=4 then |
---|
| 1073 | if interf.I.ramsel='0' then |
---|
| 1074 | SysRam.O.we<='1'; |
---|
| 1075 | SysRam.O.ena<='1'; |
---|
| 1076 | SysRam.O.enb<='0'; |
---|
| 1077 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); |
---|
| 1078 | SysRam.O.Data_in<=pgroup.grp(15 downto 8); |
---|
| 1079 | NextCtx:=NextCtx+1; |
---|
| 1080 | Interf.O.membusy<='1'; |
---|
| 1081 | end if; |
---|
| 1082 | elsif NextCtx=6 then |
---|
| 1083 | if interf.I.ramsel='0' then |
---|
| 1084 | SysRam.O.we<='1'; |
---|
| 1085 | SysRam.O.ena<='1'; |
---|
| 1086 | SysRam.O.enb<='0'; |
---|
| 1087 | SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); |
---|
| 1088 | SysRam.O.Data_in<=pgroup.grp(15 downto 8); |
---|
| 1089 | NextCtx:=NextCtx+1; |
---|
| 1090 | Interf.O.membusy<='1'; |
---|
| 1091 | end if; |
---|
| 1092 | elsif NextCtx=5 then |
---|
| 1093 | SysRam.O.we<='0'; |
---|
| 1094 | SysRam.O.ena<='0'; |
---|
| 1095 | SysRam.O.enb<='0'; |
---|
| 1096 | NextCtx:=0; |
---|
| 1097 | Interf.O.membusy<='0'; |
---|
| 1098 | end if; |
---|
| 1099 | |
---|
[70] | 1100 | |
---|
| 1101 | end procedure; |
---|
| 1102 | |
---|
| 1103 | procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is |
---|
| 1104 | --permet de synchroniser la fin des opérations sur une fenêtre |
---|
| 1105 | variable dcount : natural range 0 to 255:=0; |
---|
| 1106 | variable cstatus : std_logic_vector(Word-1 downto 0); |
---|
[72] | 1107 | variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire |
---|
[70] | 1108 | begin |
---|
[72] | 1109 | W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre |
---|
[70] | 1110 | if NextCtx =0 then |
---|
| 1111 | NextCtx:=NextCtx+1; |
---|
| 1112 | elsif NextCtx=1 then |
---|
| 1113 | if interf.I.ramsel='0' then |
---|
| 1114 | SysRam.O.we<='0'; |
---|
| 1115 | SysRam.O.ena<='0'; |
---|
| 1116 | SysRam.O.enb<='1'; |
---|
[72] | 1117 | NextCtx:=NextCtx+1; |
---|
[70] | 1118 | end if; |
---|
[72] | 1119 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); |
---|
| 1120 | If Interf.S.Gpost=0 then |
---|
[74] | 1121 | NextCtx:=5; --rien à synchroniser |
---|
[72] | 1122 | end if; |
---|
[74] | 1123 | elsif (NextCtx>=2) and (NextCtx <=3) then |
---|
[72] | 1124 | if interf.I.ramsel='0' then |
---|
| 1125 | SysRam.O.we<='0'; |
---|
| 1126 | SysRam.O.ena<='0'; |
---|
| 1127 | SysRam.O.enb<='1'; |
---|
| 1128 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); |
---|
| 1129 | NextCtx:=NextCtx+1; |
---|
| 1130 | else |
---|
| 1131 | NextCtx:=1; |
---|
| 1132 | end if; |
---|
[74] | 1133 | elsif NextCtx=4 then |
---|
[72] | 1134 | if interf.I.ramsel='0' then |
---|
| 1135 | SysRam.O.we<='0'; |
---|
| 1136 | SysRam.O.ena<='0'; |
---|
| 1137 | SysRam.O.enb<='1'; |
---|
| 1138 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); |
---|
[74] | 1139 | |
---|
[72] | 1140 | if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0 |
---|
| 1141 | --il faut un DSent=1 pour Put ou un DSending pour Get |
---|
| 1142 | if SysRam.I.Data_out(4)='1' or (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1') then |
---|
| 1143 | NextCtx:=NextCtx+1; |
---|
| 1144 | Interf.S.GPost<=(others=>'0'); |
---|
| 1145 | end if; |
---|
| 1146 | elsif SysRam.I.Data_out(3)='0' then |
---|
| 1147 | NextCtx:=NextCtx; --pas d'opérations en attente |
---|
| 1148 | else |
---|
| 1149 | NextCtx:=NextCtx; --on attend |
---|
[74] | 1150 | end if; |
---|
| 1151 | else |
---|
| 1152 | NextCtx:=2; --retour à l'atente du Bit ! |
---|
[72] | 1153 | end if; |
---|
[70] | 1154 | |
---|
[74] | 1155 | elsif NextCtx=5 then |
---|
[72] | 1156 | SysRam.O.we<='0'; |
---|
| 1157 | SysRam.O.ena<='0'; |
---|
| 1158 | SysRam.O.enb<='0'; |
---|
| 1159 | Interf.O.membusy<='0'; |
---|
| 1160 | NextCtx:=0; |
---|
[70] | 1161 | end if; |
---|
| 1162 | |
---|
| 1163 | |
---|
| 1164 | end procedure; |
---|
| 1165 | |
---|
| 1166 | |
---|
| 1167 | Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is |
---|
| 1168 | begin |
---|
| 1169 | |
---|
| 1170 | end procedure; |
---|
| 1171 | |
---|
| 1172 | procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
---|
| 1173 | command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; |
---|
| 1174 | signal intercomm :out natural; signal array_of_errcodes : out natural) is |
---|
| 1175 | |
---|
[15] | 1176 | variable i,dcount : natural:=0; |
---|
[70] | 1177 | variable adresse :natural; |
---|
| 1178 | variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); |
---|
| 1179 | begin |
---|
| 1180 | spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); |
---|
| 1181 | if NextCtx =0 then |
---|
| 1182 | |
---|
| 1183 | SysRam.O.we<='1'; |
---|
| 1184 | SysRam.O.ena<='1'; |
---|
| 1185 | SysRam.O.enb<='0'; |
---|
| 1186 | NextCtx:=1; |
---|
| 1187 | elsif NextCtx=1 then |
---|
| 1188 | if interf.I.ramsel='0' then |
---|
| 1189 | NextCtx:=2; |
---|
| 1190 | adresse:=core_spawn_adr; |
---|
| 1191 | SysRam.O.Data_in<=MPI_SPAWN & x"0" ; |
---|
| 1192 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1193 | Interf.O.membusy<='1'; |
---|
| 1194 | Interf.O.Instr_En<='0'; |
---|
| 1195 | Interf.S.IntState2<=1; -- préparation de la destination du spawn |
---|
| 1196 | end if; |
---|
| 1197 | elsif NextCtx=2 then |
---|
| 1198 | SysRam.O.we<='1'; |
---|
| 1199 | SysRam.O.ena<='1'; |
---|
| 1200 | SysRam.O.enb<='0'; |
---|
| 1201 | if interf.I.ramsel='0' then |
---|
| 1202 | NextCtx:=NextCtx+1; |
---|
| 1203 | Interf.O.membusy<='1'; |
---|
| 1204 | adresse:=core_spawn_adr; |
---|
| 1205 | if interf.I.ismain='1' then ---déclanche l'éxécution de la commande |
---|
| 1206 | SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ; |
---|
| 1207 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1208 | |
---|
| 1209 | else -- envoie d'une commande spawn à la main lib |
---|
| 1210 | SysRam.O.Data_in<=MPI_spawn & x"0" ; |
---|
| 1211 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1212 | Interf.O.Instr_En<='0'; |
---|
| 1213 | Interf.O.membusy<='1'; |
---|
| 1214 | |
---|
| 1215 | end if; |
---|
| 1216 | end if; |
---|
| 1217 | |
---|
| 1218 | elsif NextCtx=3 then |
---|
| 1219 | SysRam.O.we<='1'; |
---|
| 1220 | SysRam.O.ena<='1'; |
---|
| 1221 | SysRam.O.enb<='0'; |
---|
| 1222 | adresse:=core_spawn_adr; |
---|
| 1223 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1224 | NextCtx:=NextCtx+1; |
---|
| 1225 | elsif NextCtx=4 then |
---|
| 1226 | if interf.I.ramsel='0' then |
---|
| 1227 | adresse:=core_spawn_adr+1; |
---|
| 1228 | SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur |
---|
| 1229 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1230 | Interf.O.Instruction<=x"04"; |
---|
| 1231 | NextCtx:=NextCtx+1; |
---|
| 1232 | end if; |
---|
| 1233 | elsif NextCtx=5 then |
---|
| 1234 | if interf.I.ramsel='0' then |
---|
| 1235 | adresse:=core_spawn_adr+2; |
---|
| 1236 | SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus |
---|
| 1237 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1238 | NextCtx:=NextCtx+1; |
---|
| 1239 | end if; |
---|
| 1240 | elsif NextCtx=6 then |
---|
| 1241 | if interf.I.ramsel='0' then |
---|
| 1242 | adresse:=core_spawn_adr+3; |
---|
| 1243 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1244 | SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction |
---|
| 1245 | NextCtx:=NextCtx+1; |
---|
| 1246 | |
---|
| 1247 | end if; |
---|
| 1248 | elsif NextCtx=7 then |
---|
| 1249 | if interf.I.ramsel='0' then |
---|
| 1250 | adresse:=core_spawn_adr+3; |
---|
| 1251 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1252 | SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction |
---|
| 1253 | NextCtx:=NextCtx+1; |
---|
| 1254 | report "MPV SPAWN activé " & integer'image(interf.I.Rank); |
---|
| 1255 | end if; |
---|
| 1256 | elsif NextCtx=8 then |
---|
| 1257 | SysRam.O.we<='1'; |
---|
| 1258 | SysRam.O.ena<='1'; |
---|
| 1259 | SysRam.O.enb<='0'; |
---|
| 1260 | dcount:=Interf.S.IntState1; |
---|
| 1261 | if interf.I.ramsel='0' then |
---|
| 1262 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN)); |
---|
| 1263 | WritePtr (spawn_adr,dcount,SysRam); |
---|
| 1264 | Interf.O.Instr_En<='0'; |
---|
| 1265 | Interf.O.membusy<='1'; |
---|
| 1266 | Interf.S.IntState1<=dcount; |
---|
| 1267 | if dcount =0 then |
---|
| 1268 | NextCtx:=NextCtx+1; |
---|
| 1269 | end if; |
---|
| 1270 | end if; |
---|
| 1271 | elsif NextCtx=9 then |
---|
| 1272 | |
---|
| 1273 | --fin de la fonction |
---|
| 1274 | SysRam.O.we<='0'; |
---|
| 1275 | SysRam.O.ena<='0'; |
---|
| 1276 | SysRam.O.enb<='1'; |
---|
| 1277 | dcount:=0; |
---|
| 1278 | Interf.O.membusy<='0'; |
---|
| 1279 | Interf.O.Instr_En<='1'; |
---|
| 1280 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); |
---|
| 1281 | NextCtx:=NextCtx+1; |
---|
| 1282 | elsif NextCtx=10 then --acquittement de la copie des données dans le tampon |
---|
| 1283 | if Interf.I.Instr_ack='1' then |
---|
| 1284 | Interf.O.Instr_En<='0'; |
---|
| 1285 | NextCtx:=NextCtx+1; |
---|
| 1286 | end if; |
---|
| 1287 | SysRam.O.we<='0'; |
---|
| 1288 | SysRam.O.ena<='0'; |
---|
| 1289 | SysRam.O.enb<='1'; |
---|
| 1290 | elsif NextCtx=11 then --lecture de la fin de l'initialisation |
---|
| 1291 | SysRam.O.we<='0'; |
---|
| 1292 | SysRam.O.ena<='0'; |
---|
| 1293 | SysRam.O.enb<='1'; |
---|
[74] | 1294 | adresse:=core_spawn_adr+7; |
---|
| 1295 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); |
---|
| 1296 | if interf.I.ramsel='0' then |
---|
| 1297 | NextCtx:=NextCtx+1; |
---|
| 1298 | end if; |
---|
| 1299 | |
---|
| 1300 | elsif NextCtx=12 then --lecture de la fin de l'initialisation |
---|
| 1301 | SysRam.O.we<='0'; |
---|
| 1302 | SysRam.O.ena<='0'; |
---|
| 1303 | SysRam.O.enb<='1'; |
---|
| 1304 | adresse:=core_spawn_adr+7; |
---|
[70] | 1305 | if interf.I.ramsel='0' then |
---|
[74] | 1306 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); |
---|
| 1307 | if SysRam.I.Data_out(5)='1' then --spawned |
---|
[70] | 1308 | NextCtx:=NextCtx+1; |
---|
| 1309 | intercomm<=1; |
---|
| 1310 | end if; |
---|
| 1311 | Interf.O.membusy<='0'; |
---|
[74] | 1312 | else |
---|
| 1313 | NextCtx:=11; |
---|
| 1314 | end if; |
---|
| 1315 | elsif NextCtx=13 then --lecture de la fin de l'initialisation |
---|
| 1316 | SysRam.O.we<='0'; |
---|
| 1317 | SysRam.O.ena<='0'; |
---|
| 1318 | SysRam.O.enb<='1'; |
---|
| 1319 | adresse:=core_spawn_adr+8; |
---|
| 1320 | if interf.I.ramsel='0' then |
---|
| 1321 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); |
---|
| 1322 | Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils |
---|
| 1323 | NextCtx:=NextCtx+1; |
---|
| 1324 | |
---|
| 1325 | end if; |
---|
| 1326 | Interf.O.membusy<='0'; |
---|
| 1327 | |
---|
| 1328 | elsif NextCtx=14 then --lecture de la fin de l'initialisation |
---|
| 1329 | SysRam.O.we<='0'; |
---|
| 1330 | SysRam.O.ena<='0'; |
---|
| 1331 | SysRam.O.enb<='1'; |
---|
| 1332 | adresse:=core_spawn_adr+8; |
---|
| 1333 | if interf.I.ramsel='0' then |
---|
| 1334 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); |
---|
| 1335 | Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils |
---|
| 1336 | NextCtx:=NextCtx+1; |
---|
| 1337 | |
---|
| 1338 | end if; |
---|
| 1339 | Interf.O.membusy<='0'; |
---|
| 1340 | |
---|
| 1341 | elsif NextCtx =15 then |
---|
[70] | 1342 | Interf.O.Instr_En<='0'; |
---|
| 1343 | Interf.O.membusy<='0'; |
---|
| 1344 | SysRam.O.we<='0'; |
---|
| 1345 | SysRam.O.ena<='0'; |
---|
| 1346 | SysRam.O.enb<='0'; |
---|
| 1347 | NextCtx:=0; |
---|
| 1348 | --array_of_errcodes<=0; |
---|
| 1349 | end if; |
---|
| 1350 | array_of_errcodes<=NextCtx; |
---|
| 1351 | end procedure; |
---|
| 1352 | |
---|
| 1353 | procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is |
---|
| 1354 | variable i,dcount,wcount : natural range 0 to 255:=0; |
---|
| 1355 | variable adresse :natural; |
---|
| 1356 | variable LRam : typ_dpRam; |
---|
| 1357 | variable W0 :std_logic_vector(Word-1 downto 0); |
---|
| 1358 | variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); |
---|
| 1359 | begin |
---|
| 1360 | init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); |
---|
| 1361 | LRam:=SysRam; -- nécessaire pour le débogage |
---|
| 1362 | if NextCtx =0 then |
---|
| 1363 | |
---|
| 1364 | SysRam.O.we<='1'; |
---|
| 1365 | SysRam.O.ena<='1'; |
---|
| 1366 | SysRam.O.enb<='0'; |
---|
| 1367 | Interf.S.IntState1<=0; |
---|
| 1368 | NextCtx:=1; |
---|
| 1369 | adresse:=core_init_adr; |
---|
| 1370 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1371 | Interf.O.Instr_En<='0'; |
---|
| 1372 | |
---|
| 1373 | elsif NextCtx=1 then --écriture du ptr d'intruction |
---|
| 1374 | SysRam.O.we<='1'; |
---|
| 1375 | SysRam.O.ena<='1'; |
---|
| 1376 | SysRam.O.enb<='0'; |
---|
| 1377 | if interf.I.ramsel='0' then |
---|
| 1378 | |
---|
| 1379 | adresse:=core_init_adr; |
---|
| 1380 | |
---|
| 1381 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1382 | Interf.O.Instr_En<='0'; |
---|
| 1383 | Interf.O.membusy<='1'; |
---|
| 1384 | |
---|
| 1385 | wcount:=Interf.S.IntState1; |
---|
| 1386 | WritePtr (Init_adr,wcount,SysRam); |
---|
| 1387 | Interf.S.IntState1<=wcount; |
---|
| 1388 | |
---|
[74] | 1389 | if wcount =0 then |
---|
[70] | 1390 | NextCtx:=2; |
---|
| 1391 | Interf.S.IntState1<=0; |
---|
| 1392 | adresse:=core_init_adr; |
---|
| 1393 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1394 | end if; |
---|
| 1395 | end if; |
---|
| 1396 | elsif NextCtx=2 then |
---|
[72] | 1397 | if interf.I.ramsel='0' then |
---|
| 1398 | SysRam.O.we<='1'; |
---|
| 1399 | SysRam.O.ena<='1'; |
---|
| 1400 | SysRam.O.enb<='0'; |
---|
| 1401 | adresse:=core_init_adr; |
---|
| 1402 | SysRam.O.Data_in<=MPI_INIT & x"0" ; |
---|
| 1403 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1404 | NextCtx:=3; |
---|
| 1405 | Interf.O.membusy<='1'; |
---|
| 1406 | end if; |
---|
[70] | 1407 | elsif NextCtx=3 then |
---|
[72] | 1408 | if Interf.I.ramSel='0' then |
---|
[70] | 1409 | SysRam.O.we<='1'; |
---|
| 1410 | SysRam.O.ena<='1'; |
---|
| 1411 | SysRam.O.enb<='0'; |
---|
[72] | 1412 | Interf.O.membusy<='1'; |
---|
[70] | 1413 | adresse:=core_init_adr+1; |
---|
| 1414 | SysRam.O.Data_in<= x"04" ; |
---|
| 1415 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1416 | NextCtx:=NextCtx+1; |
---|
[72] | 1417 | end if; |
---|
[70] | 1418 | elsif NextCtx=4 then |
---|
[72] | 1419 | if Interf.I.ramSel='0' then |
---|
[70] | 1420 | SysRam.O.we<='1'; |
---|
| 1421 | SysRam.O.ena<='1'; |
---|
[72] | 1422 | Interf.O.membusy<='1'; |
---|
[70] | 1423 | SysRam.O.enb<='0'; |
---|
[72] | 1424 | adresse:=core_init_adr+1; |
---|
[70] | 1425 | Interf.O.Instruction<=x"04"; |
---|
[72] | 1426 | SysRam.O.Data_in<=x"04" ;--longueur de l'instruction |
---|
[70] | 1427 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1428 | NextCtx:=5; |
---|
[72] | 1429 | end if; |
---|
[70] | 1430 | elsif NextCtx=5 then |
---|
[72] | 1431 | if Interf.I.ramSel='0' then |
---|
[70] | 1432 | SysRam.O.we<='1'; |
---|
| 1433 | SysRam.O.ena<='1'; |
---|
[72] | 1434 | Interf.O.membusy<='1'; |
---|
[70] | 1435 | SysRam.O.enb<='0'; |
---|
[72] | 1436 | adresse:=core_init_adr+2; |
---|
[70] | 1437 | SysRam.O.Data_in<= x"00" ; |
---|
| 1438 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1439 | NextCtx:=6; |
---|
[72] | 1440 | end if; |
---|
[70] | 1441 | elsif NextCtx=6 then |
---|
[72] | 1442 | if Interf.I.ramSel='0' then |
---|
[70] | 1443 | SysRam.O.we<='1'; |
---|
| 1444 | SysRam.O.ena<='1'; |
---|
| 1445 | SysRam.O.enb<='0'; |
---|
[72] | 1446 | Interf.O.membusy<='1'; |
---|
[70] | 1447 | adresse:=core_init_adr+3; |
---|
| 1448 | SysRam.O.Data_in<=x"00" ; |
---|
| 1449 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1450 | NextCtx:=7; |
---|
[72] | 1451 | end if; |
---|
[70] | 1452 | elsif NextCtx=7 then --fin de la fonction |
---|
| 1453 | SysRam.O.we<='0'; |
---|
| 1454 | SysRam.O.ena<='0'; |
---|
| 1455 | SysRam.O.enb<='1'; |
---|
[72] | 1456 | Interf.O.membusy<='0'; |
---|
[70] | 1457 | dcount:=0; |
---|
| 1458 | Interf.O.membusy<='0'; |
---|
| 1459 | Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique |
---|
| 1460 | Interf.O.Instr_En<='1'; |
---|
| 1461 | SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); |
---|
| 1462 | NextCtx:=8; |
---|
| 1463 | elsif NextCtx=8 then --acquittement de la copie des données dans le tampon |
---|
| 1464 | if Interf.I.Instr_ack='1' then |
---|
| 1465 | Interf.O.Instr_En<='0'; |
---|
| 1466 | NextCtx:=9; |
---|
| 1467 | end if; |
---|
| 1468 | SysRam.O.we<='0'; |
---|
| 1469 | SysRam.O.ena<='0'; |
---|
| 1470 | SysRam.O.enb<='1'; |
---|
| 1471 | |
---|
| 1472 | elsif NextCtx=9 then --lecture de la fin de l'initialisation |
---|
| 1473 | SysRam.O.we<='0'; |
---|
| 1474 | SysRam.O.ena<='0'; |
---|
| 1475 | SysRam.O.enb<='1'; |
---|
| 1476 | if interf.I.ramsel='0' then |
---|
| 1477 | SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); |
---|
| 1478 | if SysRam.I.Data_out(4)='1' then |
---|
| 1479 | NextCtx:=10; |
---|
| 1480 | Interf.S.IntState1<=0; -- initialisation du compteur d'état |
---|
| 1481 | end if; |
---|
| 1482 | Interf.O.membusy<='0'; |
---|
| 1483 | end if; |
---|
| 1484 | elsif NextCtx =10 then |
---|
| 1485 | dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur |
---|
| 1486 | readmem(dcount,interf,sysRam,init_Adr,w0); |
---|
| 1487 | Interf.S.IntState1<=dcount; |
---|
| 1488 | w0:=SysRam.I.Data_out; |
---|
| 1489 | if dcount=0 then |
---|
| 1490 | Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib |
---|
| 1491 | NextCtx:=NextCtx+1; |
---|
| 1492 | end if; |
---|
| 1493 | elsif NextCtx =11 then |
---|
| 1494 | Interf.O.Instr_En<='0'; |
---|
| 1495 | Interf.O.membusy<='0'; |
---|
| 1496 | SysRam.O.we<='0'; |
---|
| 1497 | SysRam.O.ena<='0'; |
---|
| 1498 | SysRam.O.enb<='0'; |
---|
| 1499 | NextCtx:=0; |
---|
| 1500 | end if; |
---|
| 1501 | |
---|
| 1502 | |
---|
| 1503 | end procedure; |
---|
| 1504 | |
---|
| 1505 | |
---|
| 1506 | procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
---|
| 1507 | AdrVect:in std_logic_vector; Data:in std_logic_vector) is |
---|
| 1508 | --cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) |
---|
| 1509 | --en ayant vérifié que le bus est bien disponible pour l'écriture |
---|
[15] | 1510 | variable i,dcount : natural:=0; |
---|
[70] | 1511 | variable adresse :natural; |
---|
| 1512 | variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; |
---|
| 1513 | |
---|
| 1514 | begin |
---|
| 1515 | if NextCtx /=0 then --préserver la valeur de count entre les appels |
---|
| 1516 | dcount:=NextCtx; |
---|
| 1517 | else |
---|
| 1518 | |
---|
| 1519 | |
---|
| 1520 | end if; |
---|
| 1521 | |
---|
| 1522 | |
---|
| 1523 | if dcount=0 then |
---|
| 1524 | if interf.I.ramsel='0' then |
---|
| 1525 | dcount :=dcount+1; |
---|
| 1526 | Interf.O.membusy<='1'; |
---|
| 1527 | end if; |
---|
| 1528 | SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); |
---|
| 1529 | SysRam.O.Addr_wr<=adrToSet; |
---|
| 1530 | elsif dcount=1 then |
---|
| 1531 | if interf.I.ramsel='0' then |
---|
| 1532 | Interf.O.membusy<='1'; |
---|
| 1533 | dcount :=dcount+1; |
---|
| 1534 | end if; |
---|
| 1535 | SysRam.O.Data_in<=data; |
---|
| 1536 | SysRam.O.Addr_wr<=adrToSet; |
---|
| 1537 | elsif dcount=2 then |
---|
| 1538 | SysRam.O.Data_in<=data; |
---|
| 1539 | dcount :=dcount+1; |
---|
| 1540 | SysRam.O.Addr_wr<=AdrToSet; |
---|
| 1541 | elsif dcount=3 then |
---|
| 1542 | Interf.O.membusy<='1'; |
---|
| 1543 | dcount :=dcount+1; |
---|
| 1544 | SysRam.O.Addr_wr<=adrToSet; |
---|
| 1545 | SysRam.O.Data_in<=data; |
---|
| 1546 | elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM |
---|
| 1547 | dcount:=0; |
---|
| 1548 | Interf.O.membusy<='0'; |
---|
| 1549 | SysRam.O.Addr_wr<=AdrToSet; |
---|
| 1550 | end if; |
---|
| 1551 | |
---|
| 1552 | NextCtx:=dcount; |
---|
| 1553 | end procedure; |
---|
| 1554 | |
---|
| 1555 | -- écriture dans la mémoire |
---|
| 1556 | procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
---|
| 1557 | AdrVect:in std_logic_vector; data: out std_logic_vector) is |
---|
| 1558 | --cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) |
---|
| 1559 | --en ayant vérifié que le bus est bien disponible pour l'écriture |
---|
[15] | 1560 | variable i,dcount : natural:=0; |
---|
[70] | 1561 | variable adresse :natural; |
---|
| 1562 | variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; |
---|
| 1563 | |
---|
| 1564 | begin |
---|
| 1565 | if NextCtx /=0 then --préserver la valeur de count entre les appels |
---|
| 1566 | dcount:=NextCtx; |
---|
| 1567 | else |
---|
| 1568 | |
---|
| 1569 | |
---|
| 1570 | end if; |
---|
| 1571 | |
---|
| 1572 | if dcount=0 then |
---|
| 1573 | if interf.I.ramsel='0' then |
---|
| 1574 | dcount :=dcount+1; |
---|
| 1575 | Interf.O.membusy<='1'; |
---|
| 1576 | end if; |
---|
| 1577 | |
---|
| 1578 | SysRam.O.Addr_rd<=adrToSet; |
---|
| 1579 | elsif dcount=1 then |
---|
| 1580 | data:=SysRam.I.Data_out; |
---|
| 1581 | dcount :=dcount+1; |
---|
| 1582 | SysRam.O.Addr_rd<=adrToSet; |
---|
| 1583 | elsif dcount=2 then |
---|
| 1584 | data:=SysRam.I.Data_out; |
---|
| 1585 | dcount :=dcount+1; |
---|
| 1586 | SysRam.O.Addr_rd<=adrToSet; |
---|
| 1587 | elsif dcount=3 then |
---|
| 1588 | if interf.I.ramsel='0' then |
---|
| 1589 | dcount :=dcount+1; |
---|
| 1590 | SysRam.O.Addr_rd<=adrToSet; |
---|
| 1591 | data:=SysRam.I.Data_out; |
---|
| 1592 | Interf.O.membusy<='0'; |
---|
| 1593 | end if; |
---|
| 1594 | elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM |
---|
| 1595 | dcount:=0; |
---|
| 1596 | Interf.O.membusy<='0'; |
---|
| 1597 | data:=SysRam.I.Data_out; |
---|
| 1598 | end if; |
---|
| 1599 | data:=SysRam.I.Data_out; |
---|
| 1600 | NextCtx:=dcount; |
---|
| 1601 | end procedure; |
---|
| 1602 | |
---|
[74] | 1603 | procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; |
---|
| 1604 | variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is |
---|
| 1605 | --cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle) |
---|
| 1606 | --en ayant vérifié que le bus est bien disponible pour l'écriture |
---|
| 1607 | variable i,dcount : natural:=0; |
---|
| 1608 | variable adresse :natural; |
---|
| 1609 | variable tempdata:std_logic_vector(Word-1 downto 0); |
---|
[70] | 1610 | |
---|
| 1611 | |
---|
[74] | 1612 | begin |
---|
| 1613 | if NextCtx /=0 then --préserver la valeur de count entre les appels |
---|
| 1614 | dcount:=NextCtx; |
---|
| 1615 | else |
---|
| 1616 | |
---|
| 1617 | |
---|
| 1618 | end if; |
---|
| 1619 | |
---|
| 1620 | if dcount=0 then |
---|
| 1621 | if interf.I.ramsel='0' then |
---|
| 1622 | dcount :=dcount+1; |
---|
| 1623 | Interf.O.membusy<='1'; |
---|
| 1624 | end if; |
---|
| 1625 | |
---|
| 1626 | SysRam.O.Addr_rd<=adrVect; |
---|
| 1627 | SysRam.O.Addr_Wr<=adrVect; |
---|
| 1628 | elsif dcount=1 then |
---|
| 1629 | if interf.I.ramsel='0' then |
---|
| 1630 | tempdata:=SysRam.I.Data_out; |
---|
| 1631 | dcount :=dcount+1; |
---|
| 1632 | SysRam.O.Addr_rd<=adrVect; |
---|
| 1633 | end if; |
---|
| 1634 | SysRam.O.enb<='1'; |
---|
| 1635 | SySRam.O.ena<='0'; |
---|
| 1636 | SysRam.O.we<='0'; |
---|
| 1637 | elsif dcount=2 then |
---|
| 1638 | tempdata:=SysRam.I.Data_out; |
---|
| 1639 | dcount :=dcount+1; |
---|
| 1640 | SysRam.O.Addr_rd<=adrVect; |
---|
| 1641 | SysRam.O.enb<='1'; |
---|
| 1642 | SySRam.O.ena<='0'; |
---|
| 1643 | SysRam.O.we<='0'; |
---|
| 1644 | elsif dcount=3 then |
---|
| 1645 | if interf.I.ramsel='0' then |
---|
| 1646 | dcount :=dcount+1; |
---|
| 1647 | SysRam.O.Addr_Wr<=adrVect; |
---|
| 1648 | SysRam.O.We<='0'; |
---|
| 1649 | SysRam.O.ena<='0'; |
---|
| 1650 | SysRam.O.enb<='1'; |
---|
| 1651 | tempdata:=SysRam.I.Data_out; |
---|
| 1652 | Interf.O.membusy<='1'; |
---|
| 1653 | end if; |
---|
| 1654 | elsif dcount=4 then |
---|
| 1655 | if interf.I.ramsel='0' then |
---|
| 1656 | dcount :=dcount+1; |
---|
| 1657 | SysRam.O.Addr_Wr<=adrVect; |
---|
| 1658 | SysRam.O.We<='1'; |
---|
| 1659 | SysRam.O.ena<='1'; |
---|
| 1660 | SysRam.O.enb<='1'; |
---|
| 1661 | tempdata:=SysRam.I.Data_out; |
---|
| 1662 | if BitVal='1' then |
---|
| 1663 | TempData:=Tempdata or BitMask; |
---|
| 1664 | else |
---|
| 1665 | TempData:=TempData and not (BitMAsk); |
---|
| 1666 | end if; |
---|
| 1667 | SysRam.O.Data_in<=TempData; |
---|
| 1668 | Interf.O.membusy<='1'; |
---|
| 1669 | end if; |
---|
| 1670 | elsif dcount=5 then --attente d'écriture |
---|
| 1671 | if interf.I.ramsel='0' then |
---|
| 1672 | dcount :=dcount+1; |
---|
| 1673 | SysRam.O.Addr_rd<=adrVect; |
---|
| 1674 | SysRam.O.We<='1'; |
---|
| 1675 | SysRam.O.ena<='1'; |
---|
| 1676 | --SysRam.O.Data_in<=TempData; |
---|
| 1677 | Interf.O.membusy<='1'; |
---|
| 1678 | end if; |
---|
| 1679 | elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM |
---|
| 1680 | dcount:=0; |
---|
| 1681 | Interf.O.membusy<='0'; |
---|
| 1682 | SysRam.O.We<='0'; |
---|
| 1683 | SysRam.O.ena<='0'; |
---|
| 1684 | |
---|
| 1685 | end if; |
---|
| 1686 | |
---|
| 1687 | NextCtx:=dcount; |
---|
| 1688 | end procedure; |
---|
[70] | 1689 | |
---|
| 1690 | |
---|
| 1691 | |
---|
| 1692 | |
---|
| 1693 | |
---|
| 1694 | |
---|
| 1695 | |
---|
| 1696 | |
---|
| 1697 | |
---|
| 1698 | |
---|
| 1699 | |
---|
| 1700 | |
---|
| 1701 | |
---|
| 1702 | |
---|
[74] | 1703 | |
---|
| 1704 | |
---|
[70] | 1705 | procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is |
---|
| 1706 | --cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle) |
---|
| 1707 | --les données de l'appel de la procédure |
---|
[15] | 1708 | variable i,dcount : natural:=0; |
---|
[70] | 1709 | variable adresse :natural; |
---|
| 1710 | variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; |
---|
| 1711 | begin |
---|
| 1712 | if count /=0 then --préserver la valeur de count entre les appels |
---|
| 1713 | dcount:=count; |
---|
| 1714 | else |
---|
| 1715 | |
---|
| 1716 | |
---|
| 1717 | end if; |
---|
| 1718 | adresse:=Core_base_adr+2; |
---|
[74] | 1719 | AdrToSet:=AdrVect; |
---|
[70] | 1720 | if dcount=0 then |
---|
| 1721 | SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); |
---|
| 1722 | dcount :=dcount+1; |
---|
| 1723 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
| 1724 | elsif dcount=1 then |
---|
[74] | 1725 | |
---|
| 1726 | SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); |
---|
| 1727 | SysRam.O.We<='1';SysRam.O.Ena<='1'; |
---|
[70] | 1728 | dcount :=dcount+1; |
---|
| 1729 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); |
---|
[74] | 1730 | |
---|
[70] | 1731 | elsif dcount=2 then |
---|
[74] | 1732 | SysRam.O.We<='1';SysRam.O.Ena<='1'; |
---|
| 1733 | SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); |
---|
[70] | 1734 | dcount :=dcount+1; |
---|
| 1735 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); |
---|
[74] | 1736 | SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); |
---|
[70] | 1737 | elsif dcount=3 then |
---|
| 1738 | dcount :=dcount+1; |
---|
[74] | 1739 | SysRam.O.We<='1';SysRam.O.Ena<='1'; |
---|
[70] | 1740 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); |
---|
| 1741 | SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); |
---|
| 1742 | elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM |
---|
| 1743 | dcount:=0; |
---|
[74] | 1744 | SysRam.O.We<='0';SysRam.O.Ena<='0'; |
---|
[70] | 1745 | SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); |
---|
| 1746 | end if; |
---|
| 1747 | |
---|
| 1748 | count:=dcount; |
---|
[15] | 1749 | end procedure; |
---|
| 1750 | end MPI_Rma; |
---|