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Changeset 39 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_RMA.vhd
- Timestamp:
- Dec 7, 2012, 11:31:34 AM (12 years ago)
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- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_RMA.vhd
r35 r39 31 31 base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; 32 32 info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); 33 procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); 33 34 -- declare functions and procedure 34 35 procedure ReadMem(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; … … 85 86 86 87 elsif dcount=4 then 88 if interf.ramsel='0' then 87 89 SysRam.we<='1'; 88 90 SysRam.ena<='1'; … … 92 94 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 93 95 dcount:=dcount+1; 96 end if; 94 97 elsif dcount=5 then 98 if interf.ramsel='0' then 95 99 adresse:=core_put_adr+1; 96 100 sysRam.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur 97 101 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 98 102 dcount:=dcount+1; 103 end if; 99 104 elsif dcount=6 then 105 if interf.ramsel='0' then 100 106 adresse:=core_put_adr+2; 101 107 sysRam.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut 102 108 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 103 109 dcount:=dcount+1; 110 end if; 104 111 elsif dcount=7 then 112 if interf.ramsel='0' then 105 113 adresse:=core_put_adr+3; 106 114 sysRam.Data_in<=Addr1(Word-1 downto 0); --source Bas 107 115 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 108 116 dcount:=dcount+1; 117 end if; 109 118 elsif dcount=8 then 119 if interf.ramsel='0' then 110 120 adresse:=core_put_adr+4; 111 121 sysRam.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut 112 122 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 113 123 dcount:=dcount+1; 124 end if; 114 125 elsif dcount=9 then 126 if interf.ramsel='0' then 115 127 adresse:=core_put_adr+5; 116 128 sysRam.Data_in<=Addr2(Word-1 downto 0); -- destination bas 117 129 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 118 130 dcount:=dcount+1; 131 end if; 119 132 elsif dcount=10 then 133 120 134 SysRam.we<='1'; 121 135 SysRam.ena<='1'; 122 136 SysRam.enb<='1'; 137 if interf.ramsel='0' then 123 138 adresse:=core_base_adr+1; 124 139 SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); … … 127 142 Interf.Instr_En<='1'; --active la prise en compte de l'instruction 128 143 dcount:=dcount+1; 144 end if; 129 145 elsif dcount=11 then 130 146 if Interf.Instr_ack='1' then -- le Core a reçu l'instruction ? … … 146 162 SysRam.ena<='1'; -- préparer l'écriture du résultat du Put 147 163 SysRam.enb<='1'; 164 if interf.ramsel='0' then 148 165 config_reg:=SysRam.data_out and x"f6"; 149 166 SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; 150 167 dcount:=dcount+1; 168 end if; 151 169 SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); 152 170 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); … … 183 201 Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; 184 202 Target_Datatype :natural; Win : natural) is 185 variable i, dcount : natural:=0;203 variable i,wcount,dcount : natural range 0 to 255:=0; 186 204 variable adresse :natural; 187 205 variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; … … 201 219 202 220 if rising_edge(clkin) then 203 if dcount>=0 and dcount <=3 then 221 222 if dcount =0 then 223 dcount:=dcount+1; 224 elsif dcount>=1 and dcount <=3 then 204 225 if interf.ramsel='0' then 205 226 SysRam.we<='1'; 206 227 SysRam.ena<='1'; 207 228 SysRam.enb<='0'; 208 WritePtr (get_adr,dcount,SysRam); 209 if dcount =4 then 210 -- fin de l'écriture du pointeur en mémoire 229 wcount:=interf.intstate1; 230 WritePtr (get_adr,wcount,SysRam); 231 interf.intstate1<=wcount; 232 if wcount =0 then 233 dcount:=4; 211 234 end if; 212 235 end if; … … 220 243 sysRam.Data_in<=MPI_GET & std_logic_vector(to_unsigned(Target_Rank,4)); --code fonction 221 244 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 245 222 246 dcount:=dcount+1; 223 247 end if; 224 248 elsif dcount=5 then 225 if Interf.RamSel='0' then 249 if Interf.RamSel='0' then 226 250 SysRam.we<='1'; 227 251 SysRam.ena<='1'; … … 229 253 sysRam.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur 230 254 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 255 231 256 dcount:=dcount+1; 232 257 end if; … … 238 263 sysRam.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut 239 264 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 240 dcount:=dcount+1; 265 266 dcount:=dcount+1; 267 else 268 dcount:=dcount-1; 241 269 end if; 242 270 elsif dcount=7 then … … 247 275 sysRam.Data_in<=Addr1(Word-1 downto 0); --source Bas 248 276 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 249 dcount:=dcount+1; 277 278 dcount:=dcount+1; 279 else 280 dcount:=dcount-1; 250 281 end if; 251 282 elsif dcount=8 then … … 256 287 sysRam.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut 257 288 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 258 dcount:=dcount+1; 289 290 dcount:=dcount+1; 291 else 292 dcount:=dcount-1; 259 293 end if; 260 294 elsif dcount=9 then 261 if Interf.RamSel='0' then 295 if Interf.RamSel='0' then 262 296 SysRam.we<='1'; 263 297 SysRam.ena<='1'; … … 265 299 sysRam.Data_in<=Addr2(Word-1 downto 0); -- destination bas 266 300 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 301 267 302 dcount:=dcount+1; 268 303 end if; 269 304 elsif dcount=10 then 270 if Interf.RamSel='0' then305 271 306 SysRam.we<='1'; 272 307 SysRam.ena<='1'; … … 277 312 sysRam.Data_in<=x"01"; --instruction pulse enable via la mémoire; 278 313 Interf.Instr_En<='1'; --active la prise en compte de l'instruction 314 if Interf.RamSel='0' then 279 315 dcount:=dcount+1; 280 316 end if; … … 294 330 SysRam.enb<='1'; 295 331 elsif dcount=12 then 296 if Interf.RamSel='0' then332 297 333 adresse:=core_base_adr+1; 298 334 SysRam.we<='1'; 299 335 SysRam.ena<='1'; -- préparer l'écriture du résultat du get 300 336 SysRam.enb<='1'; 337 if Interf.RamSel='0' then 301 338 config_reg:=SysRam.data_out and x"f6"; 302 339 SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; 303 340 dcount:=dcount+1; 341 end if; 304 342 SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); 305 343 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 306 end if;344 307 345 elsif dcount=13 then 308 if Interf.RamSel='0' then346 309 347 SysRam.we<='1'; 310 348 SysRam.ena<='1'; -- préparer l'écriture du résultat du GET 311 349 SysRam.enb<='0'; 350 adresse:=core_base_adr+1; 351 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 352 if Interf.RamSel='0' then 312 353 config_reg:=SysRam.data_out and x"f6"; 313 354 SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; 314 355 dcount:=dcount+1; 315 adresse:=core_base_adr+1; 316 sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); 356 317 357 end if; 318 358 elsif dcount=14 then … … 332 372 333 373 NExtCtx:=dcount; 334 end if;374 end if; 335 375 end procedure; 336 376 Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is … … 361 401 adresse_rd:=CORE_INIT_ADR+1; 362 402 sysRam.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); 363 if Interf.Ramsel='0' then403 364 404 NextCtx:=1; 365 end if;405 366 406 elsif NextCtx=1 then 367 407 SysRam.we<='0'; … … 600 640 procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is 601 641 --permet de synchroniser la fin des opérations sur une fenêtre 642 variable dcount : natural range 0 to 255:=0; 643 variable cstatus : std_logic_vector(Word-1 downto 0); 644 602 645 begin 646 647 648 649 if NextCtx =0 then 650 NextCtx:=NextCtx+1; 651 elsif NextCtx=1 then 652 if interf.ramsel='0' then 653 SysRam.we<='0'; 654 SysRam.ena<='0'; 655 SysRam.enb<='1'; 656 SysRam.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); 657 if SysRam.Data_out(5)='1' and SysRam.Data_out(4)='1' and SysRam.Data_out(2)='0' then 658 NextCtx:=NextCtx+1; 659 end if; 660 end if; 661 662 elsif NextCtx=2 then 663 NextCtx:=0; 664 end if; 665 603 666 604 667 end procedure;
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