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source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/load_instr.vhd @ 72

Last change on this file since 72 was 72, checked in by rolagamo, 10 years ago

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 04:57:14 07/15/2012
6	-- Design Name:
7	-- Module Name: load_instr - Behavioral
8	-- Project Name: MPI CORE
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module permet de charger une instruction dans le FIFO 1
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23
24	-- Uncomment the following library declaration if using
25	-- arithmetic functions with Signed or Unsigned values
26	use IEEE.NUMERIC_STD.ALL;
27	use NocLib.CoreTypes.all;
28	-- Uncomment the following library declaration if instantiating
29	-- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity load_instr is
34	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
35	Instruction_en : in STD_LOGIC;
36
37	clk : in STD_LOGIC;
38	reset : in STD_LOGIC;
39	dma_rd_grant : in STD_LOGIC;
40	dma_rd_request : out STD_LOGIC:='0';
41	instruction_ack : out STD_LOGIC:='0';
42	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	fifo_wr :out std_logic:='0';
44	copying :out std_logic:='0';
45	fifo_full : in STD_LOGIC;
46	ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
47	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0);
48	Ram_rd_en : out std_logic);
49	end load_instr;
50
51	architecture Behavioral of load_instr is
52	--déclaration des types manipulés
53	type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout);
54	--déclaration des signaux
55	signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
56	--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM
57	signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
58	signal adr_ptr : natural range 0 to 65536:=0;
59	signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée
60	signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'-');
61	signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo
62	signal fifo_wr_i :std_logic:='0';
63	signal base_adrset_i : std_logic:='0';
64	signal instruction_ack_i :std_logic:='0';
65	signal Dma_rd_request_i :std_logic:='0';
66	signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE
67	signal etloadinst,next_loadinst : typ_loadinst;
68	begin
69	SYNC_PROC: process (clk)
70	begin
71	if rising_edge(clk) then
72	if (reset = '1') or instruction_en='0' then
73	etloadinst <= init;
74	Base_adrSet<= '0';
75	dma_rd_request<='0';
76	instruction_ack<='0';
77	else
78	etloadinst <= next_loadinst;
79	fifo_din <= fifo_din_i;
80	Base_AdrSet<=Base_adrSet_i;
81	ram_address_rd<=ram_address_i;
82	adr_ptr<=to_integer(unsigned(ram_address_i));
83	dma_rd_request<=dma_rd_request_i;
84	instruction_ack<=instruction_ack_i;
85	count<=count_i;
86	Ilen<=Ilen_i;
87
88
89	-- assign other outputs to internal signals
90	end if;
91	end if;
92	end process;
93
94	--
95	OUTPUT_DECODE: process (etloadinst,Count_i,Ram_data,Dma_rd_grant,fifo_wr_i,Ram_address_i)
96	variable Adr_inst1,adr_inst2 : natural;
97	begin
98	--insert statements to decode internal output signals
99	--below is simple example
100	case etloadinst is
101	when init =>
102	Dma_rd_request_i<='0';
103	fifo_wr<='0';
104	copying<='0';
105	Ram_rd_en<='0';
106	Instruction_ack_i<='0';
107	fifo_din_i<=(others=>'-');
108	Base_AdrSet_i<='0';
109
110	when SetAdr =>
111	Dma_rd_request_i<='0';
112	Instruction_ack_i<='0';
113	fifo_wr<='0';
114	copying<='0';
115	Ram_rd_en<='0';
116
117	fifo_din_i<=(others=>'-');
118	Base_AdrSet_i<='1';
119
120	when getbus =>
121	fifo_wr<='0';
122	copying<='1';
123	Ram_rd_en<=Dma_rd_grant;
124	Dma_rd_request_i<='1';
125	Instruction_ack_i<='0';
126	fifo_din_i<=(others=>'-');
127	Base_AdrSet_i<='1';
128	when readptr =>
129	fifo_wr<='0';
130
131	copying<='1';
132	Ram_rd_en<='1';
133	Dma_rd_request_i<='1';
134	Instruction_ack_i<='0';
135	fifo_din_i<=(others=>'-');
136	Base_AdrSet_i<='1';
137	when readmem =>
138	Dma_rd_request_i<='1';
139	copying<='1';
140	Ram_rd_en<='1';
141	fifo_wr<=fifo_wr_i;
142	fifo_din_i<=Ram_data;
143	Base_AdrSet_i<='1';
144	Instruction_ack_i<='0';
145
146	when freebus =>
147	Dma_rd_request_i<='0';
148	fifo_wr<='0';
149	copying<='0';
150	Ram_rd_en<='0';
151	Instruction_ack_i<='1';
152	fifo_din_i<=(others=>'-');
153	Base_AdrSet_i<='1';
154	when st_timeout =>
155	Dma_rd_request_i<='0';
156	fifo_wr<='0';
157	copying<='0';
158	Ram_rd_en<='0';
159	Instruction_ack_i<='0';
160	fifo_din_i<=(others=>'-');
161	Base_AdrSet_i<='1';
162	end case;
163	end process;
164
165	NEXT_STATE_DECODE: process (etloadinst, Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count,Ilen)
166	variable ptr : std_logic_vector(ADRLEN-1 downto 0);
167	variable timeout: natural range 0 to 255;
168	variable Base_AD,ADRtmp,iptr : natural range 0 to 65535;
169	begin
170	--declare default state for next_state to avoid latches
171	next_loadinst <= etloadinst; --default is to stay in current state
172	--insert statements to decode next_state
173	--below is a simple example
174	case (etloadinst) is
175	when init => if base_adrset='1' and Instruction_en='1' then
176	Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur
177	next_loadinst<=getbus;
178	elsif Instruction_en='1' then
179	next_loadinst<=Setadr;
180	Base_Adr<=X"0000";
181	else
182	next_loadinst<=init;
183	Base_Adr<=X"0000";
184	Ilen_i<=0;
185	end if;
186	fifo_wr_i<='0';
187	count_i<=0;
188
189	--
190	When Setadr => if Base_adrSet='0' then
191	Base_Adr<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction
192	--
193	end if;
194	next_loadinst<=init;
195	Ram_address_i<=(others=>'0');
196	count_i<=0;
197	when getbus =>
198	BASE_AD:=to_integer(unsigned(base_adr));
199	if dma_rd_grant = '1' then
200	next_loadinst <= readptr;
201
202	-- prépare la prochaine lecture
203
204	else
205
206	end if;
207	Ram_address_i<=(others=>'0');
208	count_i<=0;
209	When readptr =>
210	if dma_rd_grant = '1' then --s'assurer que le bus est disponible
211
212
213
214	if count=0 then
215	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16));
216	count_i <=count+1;
217	elsif count=1 then-- attend que la donnée soit positionnée
218	count_i <=count+1;
219
220	elsif count=2 then
221	count_i <=count+1;
222
223	elsif count=3 then
224	ptr(Word-1 downto 0):=Ram_data;
225	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
226	count_i <=count+1;
227	elsif count=4 then
228	count_i <=count+1;
229	elsif count=5 then
230	count_i <=count+1;
231	elsif count=6 then
232	ptr(15 downto 8):=Ram_data;
233	count_i<=0;
234	timeout:=0;
235	next_loadinst <= readmem;
236	else
237
238	end if;
239
240	else
241	timeout:=timeout+1;
242	count_i<=0;
243	end if;
244	when readmem =>
245	if dma_rd_grant = '1' then --s'assurer que le bus est disponible
246	if fifo_full='0' then
247	if ilen >0 then
248	if count=0 then
249	iptr:=to_integer(unsigned(ptr));
250	AdrTmp:=iptr;
251	count_i <=count+1;
252	fifo_wr_i<='0';
253	elsif count=1 then
254	count_i <=count+1;
255	fifo_wr_i<='0';
256	elsif count=2 then
257	count_i <=count+1;
258	AdrTmp:=Adr_ptr+1; --incrémentation de l'adresse
259	fifo_wr_i<='0';
260	elsif count=3 then
261	count_i <=count+1;
262	fifo_wr_i<='1'; --écriture de la donnée dans le fifo
263	Ilen_i<=Ilen-1;
264	elsif count=4 then
265	fifo_wr_i<='0';
266	count_i<=1;
267	end if;
268	else
269	fifo_wr_i<='0';
270	next_loadinst <= freebus;
271	end if;
272
273	Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16));
274	end if;
275
276	else
277	timeout:=timeout+1;
278	fifo_wr_i<='0';
279	Count_i<=0; --recommencer les cycles d'attente de la donnée
280	if timeout=50 then
281	next_loadinst<=st_timeout;
282	end if;
283	-- le bus n'est pas libre
284
285	end if;
286
287	when freebus =>
288	fifo_wr_i<='0';
289	count_i<=0;
290	Ram_address_i<=(others=>'0');
291	if instruction_en='0' then
292	next_loadinst <= init;
293	end if;
294	when st_timeout =>
295	fifo_wr_i<='0';
296	Ram_address_i<=(others=>'0');
297	next_loadinst<=init;
298	count_i<=0;
299	end case;
300	end process;
301
302	end Behavioral;
303

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