Changeset 72 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/load_instr.vhd

Timestamp:

Jan 6, 2014, 3:16:44 PM (10 years ago)

Author:

rolagamo

Message:

 

File:

• PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/load_instr.vhd (modified) (7 diffs)

PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/load_instr.vhd

@@ -193 +193 @@
                                                                 end if;
                                                                 next_loadinst<=init;
-                                        Ram_address_i<=(others=>'-');
+                                        Ram_address_i<=(others=>'0');
                                         count_i<=0;
          when getbus =>
@@ -205 +205 @@
                                         
                                 end if;
-                                Ram_address_i<=(others=>'-');
+                                Ram_address_i<=(others=>'0');
                                 count_i<=0;
          When readptr =>
@@ -223 +223 @@
                                         elsif count=3 then
                                                 ptr(Word-1 downto 0):=Ram_data;
-                                                Ram_address_i<=incr_vec(ram_address_i,'1');
+                                                Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
                                                 count_i <=count+1;
                                         elsif count=4 then
-                                                
                                                 count_i <=count+1;
                                         elsif count=5 then
+                                                count_i <=count+1;
+                                        elsif count=6 then
                                                 ptr(15 downto 8):=Ram_data;
                                                 count_i<=0;
@@ -239 +240 @@
                                 else
                                   timeout:=timeout+1;
+                                  count_i<=0;
                                 end if;
                         when readmem =>
@@ -274 +276 @@
                                 else
                                   timeout:=timeout+1;
+                                  fifo_wr_i<='0';
+                                  Count_i<=0; --recommencer les cycles d'attente de la donnée
                                         if timeout=50 then
                                                 next_loadinst<=st_timeout;
                                         end if;
-                                        Ram_address_i<=(others=>'-'); -- le bus n'est pas libre
+                                        -- le bus n'est pas libre
                                         
                                 end if;
@@ -284 +288 @@
                                 fifo_wr_i<='0';
                                 count_i<=0;
-                                 Ram_address_i<=(others=>'-');
+                                 Ram_address_i<=(others=>'0');
             if instruction_en='0' then 
                                         next_loadinst <= init;
@@ -290 +294 @@
                         when st_timeout =>
                                 fifo_wr_i<='0';
-                         Ram_address_i<=(others=>'-');
+                         Ram_address_i<=(others=>'0');
                                 next_loadinst<=init;
                                 count_i<=0;