source: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/modelsim.ini

Last change on this file was 74, checked in by rolagamo, 11 years ago
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1; Copyright 1991-2009 Mentor Graphics Corporation
2;
3; All Rights Reserved.
4;
5; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
6; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
7;   
8
9[Library]
10others = $MODEL_TECH/../modelsim.ini
11;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
12;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
13;mvc_lib = $MODEL_TECH/../mvc_lib
14
15unisim = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/unisim
16simprim = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/simprim
17unimacro = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/unimacro
18xilinxcorelib = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/xilinxcorelib
19[vcom]
20; VHDL93 variable selects language version as the default.
21; Default is VHDL-2002.
22; Value of 0 or 1987 for VHDL-1987.
23; Value of 1 or 1993 for VHDL-1993.
24; Default or value of 2 or 2002 for VHDL-2002.
25; Value of 3 or 2008 for VHDL-2008
26VHDL93 = 93
27
28; Show source line containing error. Default is off.
29; Show_source = 1
30
31; Turn off unbound-component warnings. Default is on.
32; Show_Warning1 = 0
33
34; Turn off process-without-a-wait-statement warnings. Default is on.
35; Show_Warning2 = 0
36
37; Turn off null-range warnings. Default is on.
38; Show_Warning3 = 0
39
40; Turn off no-space-in-time-literal warnings. Default is on.
41; Show_Warning4 = 0
42
43; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
44; Show_Warning5 = 0
45
46; Turn off optimization for IEEE std_logic_1164 package. Default is on.
47; Optimize_1164 = 0
48
49; Turn on resolving of ambiguous function overloading in favor of the
50; "explicit" function declaration (not the one automatically created by
51; the compiler for each type declaration). Default is off.
52; The .ini file has Explicit enabled so that std_logic_signed/unsigned
53; will match the behavior of synthesis tools.
54Explicit = 1
55
56; Turn off acceleration of the VITAL packages. Default is to accelerate.
57; NoVital = 1
58
59; Turn off VITAL compliance checking. Default is checking on.
60; NoVitalCheck = 1
61
62; Ignore VITAL compliance checking errors. Default is to not ignore.
63; IgnoreVitalErrors = 1
64
65; Turn off VITAL compliance checking warnings. Default is to show warnings.
66; Show_VitalChecksWarnings = 0
67
68; Turn off PSL assertion warning messages. Default is to show warnings.
69; Show_PslChecksWarnings = 0
70
71; Enable parsing of embedded PSL assertions. Default is enabled.
72; EmbeddedPsl = 0
73
74; Keep silent about case statement static warnings.
75; Default is to give a warning.
76; NoCaseStaticError = 1
77
78; Keep silent about warnings caused by aggregates that are not locally static.
79; Default is to give a warning.
80; NoOthersStaticError = 1
81
82; Treat as errors:
83;   case statement static warnings
84;   warnings caused by aggregates that are not locally static
85; Overrides NoCaseStaticError, NoOthersStaticError settings.
86; PedanticErrors = 1
87
88; Turn off inclusion of debugging info within design units.
89; Default is to include debugging info.
90; NoDebug = 1
91
92; Turn off "Loading..." messages. Default is messages on.
93; Quiet = 1
94
95; Turn on some limited synthesis rule compliance checking. Checks only:
96;    -- signals used (read) by a process must be in the sensitivity list
97; CheckSynthesis = 1
98
99; Activate optimizations on expressions that do not involve signals,
100; waits, or function/procedure/task invocations. Default is off.
101; ScalarOpts = 1
102
103; Turns on lint-style checking.
104; Show_Lint = 1
105
106; Require the user to specify a configuration for all bindings,
107; and do not generate a compile time default binding for the
108; component. This will result in an elaboration error of
109; 'component not bound' if the user fails to do so. Avoids the rare
110; issue of a false dependency upon the unused default binding.
111; RequireConfigForAllDefaultBinding = 1
112
113; Perform default binding at compile time.
114; Default is to do default binding at load time.
115; BindAtCompile = 1;
116
117; Inhibit range checking on subscripts of arrays. Range checking on
118; scalars defined with subtypes is inhibited by default.
119; NoIndexCheck = 1
120
121; Inhibit range checks on all (implicit and explicit) assignments to
122; scalar objects defined with subtypes.
123; NoRangeCheck = 1
124
125; Run the 0-in compiler on the VHDL source files
126; Default is off.
127; ZeroIn = 1
128
129; Set the options to be passed to the 0-in compiler.
130; Default is "".
131; ZeroInOptions = ""
132
133; Turn on code coverage in VHDL design units. Default is off.
134; Coverage = sbceft
135
136; Turn off code coverage in VHDL subprograms. Default is on.
137; CoverageSub = 0
138
139; Automatically exclude VHDL case statement default branches.
140; Default is to not exclude.
141; CoverExcludeDefault = 1
142
143; Control compiler and VOPT optimizations that are allowed when
144; code coverage is on.  Refer to the comment for this in the [vlog] area.
145; CoverOpt = 3
146
147; Inform code coverage optimizations to respect VHDL 'H' and 'L'
148; values on signals in conditions and expressions, and to not automatically
149; convert them to '1' and '0'. Default is to not convert.
150; CoverRespectHandL = 0
151
152; Increase or decrease the maximum number of rows allowed in a UDP table
153; implementing a VHDL condition coverage or expression coverage expression.
154; More rows leads to a longer compile time, but more expressions covered.
155; CoverMaxUDPRows = 192
156
157; Increase or decrease the maximum number of input patterns that are present
158; in FEC table. This leads to a longer compile time with more expressions
159; covered with FEC metric.
160; CoverMaxFECRows = 192
161
162; Enable or disable Focused Expression Coverage analysis for conditions and
163; expressions. Focused Expression Coverage data is provided by default when
164; expression and/or condition coverage is active.
165; CoverFEC = 0
166
167; Enable or disable short circuit evaluation of conditions and expressions when
168; condition or expression coverage is active. Short circuit evaluation is enabled
169; by default.
170; CoverShortCircuit = 0
171
172; Use this directory for compiler temporary files instead of "work/_temp"
173; CompilerTempDir = /tmp
174
175; Add VHDL-AMS declarations to package STANDARD
176; Default is not to add
177; AmsStandard = 1
178
179; Range and length checking will be performed on array indices and discrete
180; ranges, and when violations are found within subprograms, errors will be
181; reported. Default is to issue warnings for violations, because subprograms
182; may not be invoked.
183; NoDeferSubpgmCheck = 0
184
185; Turn off detection of FSMs having single bit current state variable.
186; FsmSingle = 0
187
188; Turn off reset state transitions in FSM.
189; FsmResetTrans = 0
190
191NoDebug = 0
192CheckSynthesis = 0
193NoVitalCheck = 0
194Optimize_1164 = 1
195NoVital = 0
196Quiet = 0
197Show_source = 0
198DisableOpt = 0
199ZeroIn = 0
200CoverageNoSub = 0
201NoCoverage = 0
202CoverCells = 0
203CoverExcludeDefault = 0
204CoverageFEC = 1
205CoverageShortCircuit = 0
206CoverOpt = 3
207Show_Warning1 = 1
208Show_Warning2 = 1
209Show_Warning3 = 1
210Show_Warning4 = 1
211Show_Warning5 = 1
212Coverage = sbce
213[vlog]
214; Turn off inclusion of debugging info within design units.
215; Default is to include debugging info.
216; NoDebug = 1
217
218; Turn on `protect compiler directive processing.
219; Default is to ignore `protect directives.
220; Protect = 1
221
222; Turn off "Loading..." messages. Default is messages on.
223; Quiet = 1
224
225; Turn on Verilog hazard checking (order-dependent accessing of global vars).
226; Default is off.
227; Hazard = 1
228
229; Turn on converting regular Verilog identifiers to uppercase. Allows case
230; insensitivity for module names. Default is no conversion.
231; UpCase = 1
232
233; Activate optimizations on expressions that do not involve signals,
234; waits, or function/procedure/task invocations. Default is off.
235; ScalarOpts = 1
236
237; Turns on lint-style checking.
238; Show_Lint = 1
239
240; Show source line containing error. Default is off.
241; Show_source = 1
242
243; Turn on bad option warning. Default is off.
244; Show_BadOptionWarning = 1
245
246; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
247; vlog95compat = 1
248
249; Turn off PSL warning messages. Default is to show warnings.
250; Show_PslChecksWarnings = 0
251
252; Enable parsing of embedded PSL assertions. Default is enabled.
253; EmbeddedPsl = 0
254
255; Set the threshold for automatically identifying sparse Verilog memories.
256; A memory with depth equal to or more than the sparse memory threshold gets
257; marked as sparse automatically, unless specified otherwise in source code
258; or by +nosparse commandline option of vlog or vopt.
259; The default is 1M.  (i.e. memories with depth equal
260; to or greater than 1M are marked as sparse)
261; SparseMemThreshold = 1048576
262
263; Set the maximum number of iterations permitted for a generate loop.
264; Restricting this permits the implementation to recognize infinite
265; generate loops.
266; GenerateLoopIterationMax = 100000
267
268; Set the maximum depth permitted for a recursive generate instantiation.
269; Restricting this permits the implementation to recognize infinite
270; recursions.
271; GenerateRecursionDepthMax = 200
272
273; Run the 0-in compiler on the Verilog source files
274; Default is off.
275; ZeroIn = 1
276
277; Set the options to be passed to the 0-in compiler.
278; Default is "".
279; ZeroInOptions = ""
280
281; Set the option to treat all files specified in a vlog invocation as a
282; single compilation unit. The default value is set to 0 which will treat
283; each file as a separate compilation unit as specified in the P1800 draft standard.
284; MultiFileCompilationUnit = 1
285
286; Turn on code coverage in Verilog design units. Default is off.
287; Coverage = sbceft
288
289; Automatically exclude Verilog case statement default branches.
290; Default is to not automatically exclude defaults.
291; CoverExcludeDefault = 1
292
293; Increase or decrease the maximum number of rows allowed in a UDP table
294; implementing a Verilog condition coverage or expression coverage expression.
295; More rows leads to a longer compile time, but more expressions covered.
296; CoverMaxUDPRows = 192
297
298; Increase or decrease the maximum number of input patterns that are present
299; in FEC table. This leads to a longer compile time with more expressions
300; covered with FEC metric.
301; CoverMaxFECRows = 192
302
303; Enable or disable Focused Expression Coverage analysis for conditions and
304; expressions. Focused Expression Coverage data is provided by default when
305; expression and/or condition coverage is active.
306; CoverFEC = 0
307
308; Enable or disable short circuit evaluation of conditions and expressions when
309; condition or expression coverage is active. Short circuit evaluation is enabled
310; by default.
311; CoverShortCircuit = 0
312
313
314; Turn on code coverage in VLOG `celldefine modules and modules included
315; using vlog -v and -y. Default is off.
316; CoverCells = 1
317
318; Control compiler and VOPT optimizations that are allowed when
319; code coverage is on. This is a number from 1 to 4, with the following
320; meanings (the default is 3):
321;    1 -- Turn off all optimizations that affect coverage reports.
322;    2 -- Allow optimizations that allow large performance improvements
323;         by invoking sequential processes only when the data changes.
324;         This may make major reductions in coverage counts.
325;    3 -- In addition, allow optimizations that may change expressions or
326;         remove some statements. Allow constant propagation. Allow VHDL
327;         subprogram inlining and VHDL FF recognition.
328;    4 -- In addition, allow optimizations that may remove major regions of
329;         code by changing assignments to built-ins or removing unused
330;         signals. Change Verilog gates to continuous assignments.
331; CoverOpt = 3
332
333; Specify the override for the default value of "cross_num_print_missing"
334; option for the Cross in Covergroups. If not specified then LRM default
335; value of 0 (zero) is used. This is a compile time option.
336; SVCrossNumPrintMissingDefault = 0
337
338; Setting following to 1 would cause creation of variables which
339; would represent the value of Coverpoint expressions. This is used
340; in conjunction with "SVCoverpointExprVariablePrefix" option
341; in the modelsim.ini
342; EnableSVCoverpointExprVariable = 0
343
344; Specify the override for the prefix used in forming the variable names
345; which represent the Coverpoint expressions. This is used in conjunction with
346; "EnableSVCoverpointExprVariable" option of the modelsim.ini
347; The default prefix is "expr".
348; The variable name is
349;    variable name => <prefix>_<coverpoint name>
350; SVCoverpointExprVariablePrefix = expr
351
352; Override for the default value of the SystemVerilog covergroup,
353; coverpoint, and cross option.goal (defined to be 100 in the LRM).
354; NOTE: It does not override specific assignments in SystemVerilog
355; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
356; in the [vsim] section can override this value.
357; SVCovergroupGoalDefault = 100
358
359; Override for the default value of the SystemVerilog covergroup,
360; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
361; NOTE: It does not override specific assignments in SystemVerilog
362; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
363; in the [vsim] section can override this value.
364; SVCovergroupTypeGoalDefault = 100
365
366; Specify the override for the default value of "strobe" option for the
367; Covergroup Type. This is a compile time option which forces "strobe" to
368; a user specified default value and supersedes SystemVerilog specified
369; default value of '0'(zero). NOTE: This can be overriden by a runtime
370; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
371; SVCovergroupStrobeDefault = 0
372
373; Specify the override for the default value of "merge_instances" option for
374; the Covergroup Type. This is a compile time option which forces
375; "merge_instances" to a user specified default value and supersedes
376; SystemVerilog specified default value of '0'(zero).
377; SVCovergroupMergeInstancesDefault = 0
378
379; Specify the override for the default value of "per_instance" option for the
380; Covergroup variables. This is a compile time option which forces "per_instance"
381; to a user specified default value and supersedes SystemVerilog specified
382; default value of '0'(zero).
383; SVCovergroupPerInstanceDefault = 0
384
385; Specify the override for the default value of "get_inst_coverage" option for the
386; Covergroup variables. This is a compile time option which forces
387; "get_inst_coverage" to a user specified default value and supersedes
388; SystemVerilog specified default value of '0'(zero).
389; SVCovergroupGetInstCoverageDefault = 0
390
391;
392; A space separated list of resource libraries that contain precompiled
393; packages.  The behavior is identical to using the "-L" switch.
394;
395; LibrarySearchPath = <path/lib> [<path/lib> ...]
396LibrarySearchPath = mtiAvm mtiOvm mtiUPF
397
398; The behavior is identical to the "-mixedansiports" switch.  Default is off.
399; MixedAnsiPorts = 1
400
401; Enable SystemVerilog 3.1a $typeof() function. Default is off.
402; EnableTypeOf = 1
403
404; Only allow lower case pragmas. Default is disabled.
405; AcceptLowerCasePragmaOnly = 1
406
407; Set the maximum depth permitted for a recursive include file nesting.
408; IncludeRecursionDepthMax = 5
409
410; Turn off detection of FSMs having single bit current state variable.
411; FsmSingle = 0
412
413; Turn off reset state transitions in FSM.
414; FsmResetTrans = 0
415
416; Turn off detections of FSMs having x-assignment.
417; FsmXAssign = 0
418
419; List of file suffixes which will be read as SystemVerilog.  White space
420; in extensions can be specified with a back-slash: "\ ".  Back-slashes
421; can be specified with two consecutive back-slashes: "\\";
422; SVFileExtensions = sv svp svh
423
424; This setting is the same as the vlog -sv command line switch.
425; Enables SystemVerilog features and keywords when true (1).
426; When false (0), the rules of IEEE Std 1364-2001 are followed and
427; SystemVerilog keywords are ignored.
428; Svlog = 0
429
430; Prints attribute placed upon SV packages during package import
431; when true (1).  The attribute will be ignored when this
432; entry is false (0). The attribute name is "package_load_message".
433; The value of this attribute is a string literal.
434; Default is true (1).
435; PrintSVPackageLoadingAttribute = 1
436
437vlog95compat = 0
438Vlog01Compat = 0
439Svlog = 0
440CoverCells = 0
441CoverExcludeDefault = 0
442CoverageFEC = 0
443CoverageShortCircuit = 0
444CoverOpt = 3
445OptionFile = C:/Core MPI/CORE_MPI/vlog.opt
446Quiet = 0
447Show_source = 0
448Protect = 0
449NoDebug = 0
450Hazard = 0
451UpCase = 0
452DisableOpt = 0
453ZeroIn = 0
454Coverage = sbce
455[sccom]
456; Enable use of SCV include files and library.  Default is off.
457; UseScv = 1
458
459; Add C++ compiler options to the sccom command line by using this variable.
460; CppOptions = -g
461
462; Use custom C++ compiler located at this path rather than the default path.
463; The path should point directly at a compiler executable.
464; CppPath = /usr/bin/g++
465
466; Enable verbose messages from sccom.  Default is off.
467; SccomVerbose = 1
468
469; sccom logfile.  Default is no logfile.
470; SccomLogfile = sccom.log
471
472; Enable use of SC_MS include files and library.  Default is off.
473; UseScMs = 1
474
475UseScv = 0
476UseScMs = 0
477CppOptions =   
478SccomVerbose = 0
479[vopt]
480; Turn on code coverage in vopt.  Default is off.
481; Coverage = sbceft
482
483; Control compiler optimizations that are allowed when
484; code coverage is on.  Refer to the comment for this in the [vlog] area.
485; CoverOpt = 3
486
487; Increase or decrease the maximum number of rows allowed in a UDP table
488; implementing a vopt condition coverage or expression coverage expression.
489; More rows leads to a longer compile time, but more expressions covered.
490; CoverMaxUDPRows = 192
491
492; Increase or decrease the maximum number of input patterns that are present
493; in FEC table. This leads to a longer compile time with more expressions
494; covered with FEC metric.
495; CoverMaxFECRows = 192
496
497[vsim]
498; vopt flow
499; Set to turn on automatic optimization of a design.
500; Default is on
501VoptFlow = 1
502
503; vopt automatic SDF
504; If automatic design optimization is on, enables automatic compilation
505; of SDF files.
506; Default is on, uncomment to turn off.
507; VoptAutoSDFCompile = 0
508
509; Automatic SDF compilation
510; Disables automatic compilation of SDF files in flows that support it.
511; Default is on, uncomment to turn off.
512; NoAutoSDFCompile = 1
513
514; Simulator resolution
515; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
516Resolution = ns
517
518; Disable certain code coverage exclusions automatically.
519; Assertions and FSM are exluded from the code coverage by default
520; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
521; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
522; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
523; Or specify comma or space separated list
524;AutoExclusionsDisable = fsm,assertions
525
526; User time unit for run commands
527; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
528; unit specified for Resolution. For example, if Resolution is 100ps,
529; then UserTimeUnit defaults to ps.
530; Should generally be set to default.
531UserTimeUnit = default
532
533; Default run length
534RunLength = 100
535
536; Maximum iterations that can be run without advancing simulation time
537IterationLimit = 5000
538
539; Control PSL and Verilog Assume directives during simulation
540; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
541; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
542; SimulateAssumeDirectives = 1
543
544; Control the simulation of PSL and SVA
545; These switches can be overridden by the vsim command line switches:
546;    -psl, -nopsl, -sva, -nosva.
547; Set SimulatePSL = 0 to disable PSL simulation
548; Set SimulatePSL = 1 to enable PSL simulation (default)
549; SimulatePSL = 1
550; Set SimulateSVA = 0 to disable SVA simulation
551; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
552; SimulateSVA = 1
553
554; Directives to license manager can be set either as single value or as
555; space separated multi-values:
556; vhdl          Immediately reserve a VHDL license
557; vlog          Immediately reserve a Verilog license
558; plus          Immediately reserve a VHDL and Verilog license
559; nomgc         Do not look for Mentor Graphics Licenses
560; nomti         Do not look for Model Technology Licenses
561; noqueue       Do not wait in the license queue when a license is not available
562; viewsim       Try for viewer license but accept simulator license(s) instead
563;               of queuing for viewer license (PE ONLY)
564; noviewer      Disable checkout of msimviewer and vsim-viewer license
565;               features (PE ONLY)
566; noslvhdl      Disable checkout of qhsimvh and vsim license features
567; noslvlog      Disable checkout of qhsimvl and vsimvlog license features
568; nomix         Disable checkout of msimhdlmix and hdlmix license features
569; nolnl         Disable checkout of msimhdlsim and hdlsim license features
570; mixedonly     Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
571;               features
572; lnlonly       Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
573;               hdlmix license features
574; Single value:
575; License = plus
576; Multi-value:
577; License = noqueue plus
578
579; Stop the simulator after a VHDL/Verilog immediate assertion message
580; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
581BreakOnAssertion = 3
582
583; VHDL assertion Message Format
584; %S - Severity Level
585; %R - Report Message
586; %T - Time of assertion
587; %D - Delta
588; %I - Instance or Region pathname (if available)
589; %i - Instance pathname with process
590; %O - Process name
591; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
592; %P - Instance or Region path without leaf process
593; %F - File
594; %L - Line number of assertion or, if assertion is in a subprogram, line
595;      from which the call is made
596; %% - Print '%' character
597; If specific format for assertion level is defined, use its format.
598; If specific format is not defined for assertion level:
599; - and if failure occurs during elaboration, use MessageFormatBreakLine;
600; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
601;   level), use MessageFormatBreak;
602; - otherwise, use MessageFormat.
603; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
604; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
605; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
606; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
607; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
608; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
609; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
610; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
611
612; Error File - alternate file for storing error messages
613; ErrorFile = error.log
614
615
616; Simulation Breakpoint messages
617; This flag controls the display of function names when reporting the location
618; where the simulator stops do to a breakpoint or fatal error.
619; Example w/function name:  # Break in Process ctr at counter.vhd line 44
620; Example wo/function name: # Break at counter.vhd line 44
621ShowFunctions = 1
622
623; Default radix for all windows and commands.
624; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
625DefaultRadix = symbolic
626
627; VSIM Startup command
628; Startup = do startup.do
629
630; VSIM Shutdown file
631; Filename to save u/i formats and configurations.
632; ShutdownFile = restart.do
633; To explicitly disable auto save:
634; ShutdownFile = --disable-auto-save
635
636; File for saving command transcript
637TranscriptFile = transcript
638
639; File for saving command history
640; CommandHistory = cmdhist.log
641
642; Specify whether paths in simulator commands should be described
643; in VHDL or Verilog format.
644; For VHDL, PathSeparator = /
645; For Verilog, PathSeparator = .
646; Must not be the same character as DatasetSeparator.
647PathSeparator = /
648
649; Specify the dataset separator for fully rooted contexts.
650; The default is ':'. For example: sim:/top
651; Must not be the same character as PathSeparator.
652DatasetSeparator = :
653
654; Specify a unique path separator for the Signal Spy set of functions.
655; The default will be to use the PathSeparator variable.
656; Must not be the same character as DatasetSeparator.
657; SignalSpyPathSeparator = /
658
659; Used to control parsing of HDL identifiers input to the tool.
660; This includes CLI commands, vsim/vopt/vlog/vcom options,
661; string arguments to FLI/VPI/DPI calls, etc.
662; If set to 1, accept either Verilog escaped Id syntax or
663; VHDL extended id syntax, regardless of source language.
664; If set to 0, the syntax of the source language must be used.
665; Each identifier in a hierarchical name may need different syntax,
666; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
667;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
668; GenerousIdentifierParsing = 1
669
670; Disable VHDL assertion messages
671; IgnoreNote = 1
672; IgnoreWarning = 1
673; IgnoreError = 1
674; IgnoreFailure = 1
675
676; Disable System Verilog assertion messages
677; IgnoreSVAInfo = 1
678; IgnoreSVAWarning = 1
679; IgnoreSVAError = 1
680; IgnoreSVAFatal = 1
681
682; Do not print any additional information from Severity System tasks.
683; Only the message provided by the user is printed along with severity
684; information.
685; SVAPrintOnlyUserMessage = 1;
686
687; Default force kind. May be freeze, drive, deposit, or default
688; or in other terms, fixed, wired, or charged.
689; A value of "default" will use the signal kind to determine the
690; force kind, drive for resolved signals, freeze for unresolved signals
691; DefaultForceKind = freeze
692
693; If zero, open files when elaborated; otherwise, open files on
694; first read or write.  Default is 0.
695; DelayFileOpen = 1
696
697; Control VHDL files opened for write.
698;   0 = Buffered, 1 = Unbuffered
699UnbufferedOutput = 0
700
701; Control the number of VHDL files open concurrently.
702; This number should always be less than the current ulimit
703; setting for max file descriptors.
704;   0 = unlimited
705ConcurrentFileLimit = 40
706
707; Control the number of hierarchical regions displayed as
708; part of a signal name shown in the Wave window.
709; A value of zero tells VSIM to display the full name.
710; The default is 0.
711; WaveSignalNameWidth = 0
712
713; Turn off warnings when changing VHDL constants and generics
714; Default is 1 to generate warning messages
715; WarnConstantChange = 0
716
717; Turn off warnings from the std_logic_arith, std_logic_unsigned
718; and std_logic_signed packages.
719; StdArithNoWarnings = 1
720
721; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
722; NumericStdNoWarnings = 1
723
724; Control the format of the (VHDL) FOR generate statement label
725; for each iteration.  Do not quote it.
726; The format string here must contain the conversion codes %s and %d,
727; in that order, and no other conversion codes.  The %s represents
728; the generate_label; the %d represents the generate parameter value
729; at a particular generate iteration (this is the position number if
730; the generate parameter is of an enumeration type).  Embedded whitespace
731; is allowed (but discouraged); leading and trailing whitespace is ignored.
732; Application of the format must result in a unique scope name over all
733; such names in the design so that name lookup can function properly.
734; GenerateFormat = %s__%d
735
736; Specify whether checkpoint files should be compressed.
737; The default is 1 (compressed).
738; CheckpointCompressMode = 0
739
740; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
741; The term "out-of-the-blue" refers to SystemVerilog export function calls
742; made from C functions that don't have the proper context setup
743; (as is the case when running under "DPI-C" import functions).
744; When this is enabled, one can call a DPI export function
745; (but not task) from any C code.
746; The default is 0 (disabled).
747; DpiOutOfTheBlue = 1
748
749; Specify whether continuous assignments are run before other normal priority
750; processes scheduled in the same iteration. This event ordering minimizes race
751; differences between optimized and non-optimized designs, and is the default
752; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
753; ImmediateContinuousAssign to 0.
754; The default is 1 (enabled).
755; ImmediateContinuousAssign = 0
756
757; List of dynamically loaded objects for Verilog PLI applications
758; Veriuser = veriuser.sl
759
760; Which default VPI object model should the tool conform to?
761; The 1364 modes are Verilog-only, for backwards compatibility with older
762; libraries, and SystemVerilog objects are not available in these modes.
763;
764; In the absence of a user-specified default, the tool default is the
765; latest available LRM behavior.
766; Options for PliCompatDefault are:
767;  VPI_COMPATIBILITY_VERSION_1364v1995
768;  VPI_COMPATIBILITY_VERSION_1364v2001
769;  VPI_COMPATIBILITY_VERSION_1364v2005
770;  VPI_COMPATIBILITY_VERSION_1800v2005
771;  VPI_COMPATIBILITY_VERSION_1800v2008
772;
773; Synonyms for each string are also recognized:
774;  VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
775;  VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
776;  VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
777;  VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
778;  VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
779
780
781; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
782
783; Specify default options for the restart command. Options can be one
784; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
785; DefaultRestartOptions = -force
786
787; Turn on (1) or off (0) WLF file compression.
788; The default is 1 (compress WLF file).
789; WLFCompress = 0
790
791; Specify whether to save all design hierarchy (1) in the WLF file
792; or only regions containing logged signals (0).
793; The default is 0 (save only regions with logged signals).
794; WLFSaveAllRegions = 1
795
796; WLF file time limit.  Limit WLF file by time, as closely as possible,
797; to the specified amount of simulation time.  When the limit is exceeded
798; the earliest times get truncated from the file.
799; If both time and size limits are specified the most restrictive is used.
800; UserTimeUnits are used if time units are not specified.
801; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
802; WLFTimeLimit = 0
803
804; WLF file size limit.  Limit WLF file size, as closely as possible,
805; to the specified number of megabytes.  If both time and size limits
806; are specified then the most restrictive is used.
807; The default is 0 (no limit).
808; WLFSizeLimit = 1000
809
810; Specify whether or not a WLF file should be deleted when the
811; simulation ends.  A value of 1 will cause the WLF file to be deleted.
812; The default is 0 (do not delete WLF file when simulation ends).
813; WLFDeleteOnQuit = 1
814
815; Specify whether or not a WLF file should be indexed during
816; simulation.  If set to 0, the WLF file will not be indexed.
817; The default is 1, indexed the WLF file.
818; WLFIndex = 0
819
820; Specify whether or not a WLF file should be optimized during
821; simulation.  If set to 0, the WLF file will not be optimized.
822; The default is 1, optimize the WLF file.
823; WLFOptimize = 0
824
825; Specify the name of the WLF file.
826; The default is vsim.wlf
827; WLFFilename = vsim.wlf
828
829; Specify the WLF reader cache size limit for each open WLF file. 
830; The size is giving in megabytes.  A value of 0 turns off the
831; WLF cache.
832; WLFSimCacheSize allows a different cache size to be set for
833; simulation WLF file independent of post-simulation WLF file
834; viewing.  If WLFSimCacheSize is not set it defaults to the
835; WLFCacheSize setting.
836; The default WLFCacheSize setting is enabled to 256M per open WLF file.
837; WLFCacheSize = 2000
838; WLFSimCacheSize = 500
839
840; Specify the WLF file event collapse mode.
841; 0 = Preserve all events and event order. (same as -wlfnocollapse)
842; 1 = Only record values of logged objects at the end of a simulator iteration.
843;     (same as -wlfcollapsedelta)
844; 2 = Only record values of logged objects at the end of a simulator time step.
845;     (same as -wlfcollapsetime)
846; The default is 1.
847; WLFCollapseMode = 0
848
849; Specify whether WLF file logging can use threads on multi-processor machines
850; if 0, no threads will be used, if 1, threads will be used if the system has
851; more than one processor
852; WLFUseThreads = 1
853
854; Turn on/off undebuggable SystemC type warnings. Default is on.
855; ShowUndebuggableScTypeWarning = 0
856
857; Turn on/off unassociated SystemC name warnings. Default is off.
858; ShowUnassociatedScNameWarning = 1
859
860; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
861; ScShowIeeeDeprecationWarnings = 1
862
863; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
864; ScEnableScSignalWriteCheck = 1
865
866; Set SystemC default time unit.
867; Set to fs, ps, ns, us, ms, or sec with optional
868; prefix of 1, 10, or 100.  The default is 1 ns.
869; The ScTimeUnit value is honored if it is coarser than Resolution.
870; If ScTimeUnit is finer than Resolution, it is set to the value
871; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
872; then the default time unit will be 1 ns.  However if Resolution
873; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
874ScTimeUnit = ns
875
876; Set SystemC sc_main stack size. The stack size is set as an integer
877; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
878; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
879; on the amount of data on the sc_main() stack and the memory required
880; to succesfully execute the longest function call chain of sc_main().
881ScMainStackSize = 10 Mb
882
883; Turn on/off execution of remainder of sc_main upon quitting the current
884; simulation session. If the cumulative length of sc_main() in terms of
885; simulation time units is less than the length of the current simulation
886; run upon quit or restart, sc_main() will be in the middle of execution.
887; This switch gives the option to execute the remainder of sc_main upon
888; quitting simulation. The drawback of not running sc_main till the end
889; is memory leaks for objects created by sc_main. If on, the remainder of
890; sc_main will be executed ignoring all delays. This may cause the simulator
891; to crash if the code in sc_main is dependent on some simulation state.
892; Default is on.
893ScMainFinishOnQuit = 1
894
895; Set the SCV relationship name that will be used to identify phase
896; relations.  If the name given to a transactor relation matches this
897; name, the transactions involved will be treated as phase transactions
898ScvPhaseRelationName = mti_phase
899
900; Customize the vsim kernel shutdown behavior at the end of the simulation.
901; Some common causes of the end of simulation are $finish (implicit or explicit),
902; sc_stop(), tf_dofinish(), and assertion failures.
903; This should be set to "ask", "exit", or "stop". The default is "ask".
904; "ask"   -- In batch mode, the vsim kernel will abruptly exit. 
905;            In GUI mode, a dialog box will pop up and ask for user confirmation
906;            whether or not to quit the simulation.
907; "stop"  -- Cause the simulation to stay loaded in memory. This can make some
908;            post-simulation tasks easier.
909; "exit"  -- The simulation will abruptly exit without asking for any confirmation.
910; "final" -- Run SystemVerilog final blocks then behave as "stop".
911; Note: these ini variables can be overriden by the vsim command
912;       line switch "-onfinish <ask|stop|exit>".
913OnFinish = ask
914
915; Print pending deferred assertion messages.
916; Deferred assertion messages may be scheduled after the $finish in the same
917; time step. Deferred assertions scheduled to print after the $finish are
918; printed before exiting with severity level NOTE since it's not known whether
919; the assertion is still valid due to being printed in the active region
920; instead of the reactive region where they are normally printed.
921; OnFinishPendingAssert = 1;
922
923; Print "simstats" result at the end of simulation before shutdown.
924; If this is enabled, the simstats result will be printed out before shutdown.
925; The default is off.
926; PrintSimStats = 1
927
928; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
929; AssertFile = assert.log
930
931; Run simulator in assertion debug mode. Default is off.
932; AssertionDebug = 1
933
934; Turn on/off PSL/SVA concurrent assertion pass enable.
935; For SVA, Default is on when the assertion has a pass action block, or
936; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
937; For PSL, Default is on only when vsim switch "-assertdebug" is used
938; and the vopt "+acc=a" flag is active.
939; AssertionPassEnable = 0
940
941; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
942; AssertionFailEnable = 0
943
944; Set PSL/SVA concurrent assertion pass limit. Default is -1.
945; Any positive integer, -1 for infinity.
946; AssertionPassLimit = 1
947
948; Set PSL/SVA concurrent assertion fail limit. Default is -1.
949; Any positive integer, -1 for infinity.
950; AssertionFailLimit = 1
951
952; Turn on/off PSL concurrent assertion pass log. Default is off.
953; The flag does not affect SVA
954; AssertionPassLog = 1
955
956; Turn on/off PSL concurrent assertion fail log. Default is on.
957; The flag does not affect SVA
958; AssertionFailLog = 0
959
960; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode.  Default is on.
961; AssertionFailLocalVarLog = 0
962
963; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
964; 0 = Continue  1 = Break  2 = Exit
965; AssertionFailAction = 1
966
967; Enable the active thread monitor in the waveform display when assertion debug is enabled.
968; AssertionActiveThreadMonitor = 1
969
970; Control how many waveform rows will be used for displaying the active threads.  Default is 5.
971; AssertionActiveThreadMonitorLimit = 5
972
973; Control how many thread start times will be preserved for ATV viewing for a given assertion
974; instance.  Default is -1 (ALL).
975; ATVStartTimeKeepCount = -1
976
977; Turn on/off code coverage
978; CodeCoverage = 0
979
980; Count all code coverage condition and expression truth table rows that match.
981; CoverCountAll = 1
982
983; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
984; is to include them.
985; ToggleNoIntegers = 1
986
987; Set the maximum number of values that are collected for toggle coverage of
988; VHDL integers. Default is 100;
989; ToggleMaxIntValues = 100
990
991; Set the maximum number of values that are collected for toggle coverage of
992; Verilog real. Default is 100;
993; ToggleMaxRealValues = 100
994
995; Turn on automatic inclusion of Verilog integers in toggle coverage, except
996; for enumeration types. Default is to include them.
997; ToggleVlogIntegers = 0
998
999; Turn on automatic inclusion of Verilog real type in toggle coverage, except
1000; for shortreal types. Default is to not include them.
1001; ToggleVlogReal = 1
1002
1003; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
1004; Default is to not include them.
1005; ToggleFixedSizeArray = 1
1006
1007; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
1008; are included for toggle coverage. This leads to a longer simulation time with bigger
1009; arrays covered with toggle coverage. Default is 1024.
1010; ToggleMaxFixedSizeArray = 1024
1011
1012; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
1013; TogglePackedAsVec = 0
1014
1015; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
1016; ToggleVlogEnumBits = 0
1017
1018; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
1019; For unlimited width, set to 0.
1020; ToggleWidthLimit = 128
1021
1022; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
1023; reached this count, further activity on the bit is ignored. Default is 1.
1024; For unlimited counts, set to 0.
1025; ToggleCountLimit = 1
1026
1027; Turn on/off all PSL/SVA cover directive enables.  Default is on.
1028; CoverEnable = 0
1029
1030; Turn on/off PSL/SVA cover log.  Default is off.
1031; CoverLog = 1
1032
1033; Set "at_least" value for all PSL/SVA cover directives.  Default is 1.
1034; CoverAtLeast = 2
1035
1036; Set "limit" value for all PSL/SVA cover directives.  Default is -1.
1037; Any positive integer, -1 for infinity.
1038; CoverLimit = 1
1039
1040; Specify the coverage database filename.
1041; Default is "" (i.e. database is NOT automatically saved on close).
1042; UCDBFilename = vsim.ucdb
1043
1044; Specify the maximum limit for the number of Cross (bin) products reported
1045; in XML and UCDB report against a Cross. A warning is issued if the limit
1046; is crossed.
1047; MaxReportRhsSVCrossProducts = 1000
1048
1049; Specify the override for the "auto_bin_max" option for the Covergroups.
1050; If not specified then value from Covergroup "option" is used.
1051; SVCoverpointAutoBinMax = 64
1052
1053; Specify the override for the value of "cross_num_print_missing"
1054; option for the Cross in Covergroups. If not specified then value
1055; specified in the "option.cross_num_print_missing" is used. This
1056; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
1057; value specified by user in source file and any SVCrossNumPrintMissingDefault
1058; specified in modelsim.ini.
1059; SVCrossNumPrintMissing = 0
1060
1061; Specify whether to use the value of "cross_num_print_missing"
1062; option in report and GUI for the Cross in Covergroups. If not specified then
1063; cross_num_print_missing is ignored for creating reports and displaying
1064; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
1065; UseSVCrossNumPrintMissing = 0
1066
1067; Specify the override for the value of "strobe" option for the
1068; Covergroup Type. If not specified then value in "type_option.strobe"
1069; will be used. This is runtime option which forces "strobe" to
1070; user specified value and supersedes user specified values in the
1071; SystemVerilog Code. NOTE: This also overrides the compile time
1072; default value override specified using "SVCovergroupStrobeDefault"
1073; SVCovergroupStrobe = 0
1074
1075; Override for explicit assignments in source code to "option.goal" of
1076; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
1077; default value of "option.goal" (defined to be 100 in the SystemVerilog
1078; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
1079; SVCovergroupGoal = 100
1080
1081; Override for explicit assignments in source code to "type_option.goal" of
1082; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
1083; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
1084; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
1085; SVCovergroupTypeGoal = 100
1086
1087; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
1088; builtin functions, and report. This setting changes the default values of
1089; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
1090; behavior if explicit assignments are not made on option.get_inst_coverage and
1091; type_option.merge_instances by the user. There are two vsim command line
1092; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
1093; The default value of this variable is 1
1094; SVCovergroup63Compatibility = 1
1095
1096; Enable or disable generation of more detailed information about the sampling
1097; of covergroup, cross, and coverpoints. It provides the details of the number
1098; of times the covergroup instance and type were sampled, as well as details
1099; about why covergroup, cross and coverpoint were not covered. A non-zero value
1100; is to enable this feature. 0 is to disable this feature. Default is 0
1101; SVCovergroupSampleInfo = 0
1102
1103; Specify the maximum number of Coverpoint bins in whole design for
1104; all Covergroups.
1105; MaxSVCoverpointBinsDesign = 2147483648
1106
1107; Specify maximum number of Coverpoint bins in any instance of a Covergroup
1108; MaxSVCoverpointBinsInst = 2147483648
1109
1110; Specify the maximum number of Cross bins in whole design for
1111; all Covergroups.
1112; MaxSVCrossBinsDesign = 2147483648
1113
1114; Specify maximum number of Cross bins in any instance of a Covergroup
1115; MaxSVCrossBinsInst = 2147483648
1116
1117; Set weight for all PSL/SVA cover directives.  Default is 1.
1118; CoverWeight = 2
1119
1120; Check vsim plusargs.  Default is 0 (off).
1121; 0 = Don't check plusargs
1122; 1 = Warning on unrecognized plusarg
1123; 2 = Error and exit on unrecognized plusarg
1124; CheckPlusargs = 1
1125
1126; Load the specified shared objects with the RTLD_GLOBAL flag.
1127; This gives global visibility to all symbols in the shared objects,
1128; meaning that subsequently loaded shared objects can bind to symbols
1129; in the global shared objects.  The list of shared objects should
1130; be whitespace delimited.  This option is not supported on the
1131; Windows or AIX platforms.
1132; GlobalSharedObjectList = example1.so example2.so example3.so
1133
1134; Run the 0in tools from within the simulator.
1135; Default is off.
1136; ZeroIn = 1
1137
1138; Set the options to be passed to the 0in runtime tool.
1139; Default value set to "".
1140; ZeroInOptions = ""
1141
1142; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
1143; Sv_Seed = 0
1144
1145; Maximum size of dynamic arrays that are resized during randomize().
1146; The default is 1000. A value of 0 indicates no limit.
1147; SolveArrayResizeMax = 1000
1148
1149; Error message severity when randomize() failure is detected (SystemVerilog).
1150; The default is 0 (no error).
1151; 0 = No error  1 = Warning  2 = Error  3 = Failure  4 = Fatal
1152; SolveFailSeverity = 0
1153
1154; Enable/disable debug information for randomize() failures (SystemVerilog).
1155; The default is 0 (disabled). Set to 1 to enable.
1156; SolveFailDebug = 0
1157
1158; When SolveFailDebug is enabled, this value specifies the algorithm used to
1159; discover conflicts between constraints for randomize() failures.
1160; The default is "many".
1161;
1162; Valid schemes are:
1163;    "many" = best for determining conflicts due to many related constraints
1164;    "few"  = best for determining conflicts due to few related constraints
1165;
1166; SolveFailDebugScheme = many
1167
1168; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
1169; specifies the maximum number of constraint subsets that will be tested for
1170; conflicts.
1171; The default is 0 (no limit).
1172; SolveFailDebugLimit = 0
1173
1174; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
1175; specifies the maximum size of constraint subsets that will be tested for
1176; conflicts.
1177; The default value is 0 (no limit).
1178; SolveFailDebugMaxSet = 0
1179
1180; Maximum size of the solution graph that may be generated during randomize().
1181; This value can be used to force randomize() to abort if the memory
1182; requirements of the constraint scenario exceeds the specified limit. This
1183; value is specified in 1000s of nodes.
1184; The default is 10000. A value of 0 indicates no limit.
1185; SolveGraphMaxSize = 10000
1186
1187; Maximum number of evaluations that may be performed on the solution graph
1188; generated during randomize(). This value can be used to force randomize() to
1189; abort if the complexity of the constraint scenario (in time) exceeds the
1190; specified limit. This value is specified in 10000s of evaluations.
1191; The default is 10000. A value of 0 indicates no limit.
1192; SolveGraphMaxEval = 10000
1193
1194; Use SolveFlags to specify options that will guide the behavior of the
1195; constraint solver. These options may improve the performance of the
1196; constraint solver for some testcases, and decrease the performance of
1197; the constraint solver for others.
1198; The default value is "" (no options).
1199;
1200; Valid flags are:
1201;    c = interleave bits of concatenation operands
1202;    i = disable bit interleaving for >, >=, <, <= constraints
1203;    n = disable bit interleaving for all constraints
1204;    r = reverse bit interleaving
1205;
1206; SolveFlags =
1207
1208; Specify random sequence compatiblity with a prior letter release. This
1209; option is used to get the same random sequences during simulation as
1210; as a prior letter release. Only prior letter releases (of the current
1211; number release) are allowed.
1212; Note: To achieve the same random sequences, solver optimizations and/or
1213; bug fixes introduced since the specified release may be disabled -
1214; yielding the performance / behavior of the prior release.
1215; Default value set to "" (random compatibility not required).
1216; SolveRev =
1217
1218; Environment variable expansion of command line arguments has been depricated
1219; in favor shell level expansion.  Universal environment variable expansion
1220; inside -f files is support and continued support for MGC Location Maps provide
1221; alternative methods for handling flexible pathnames.
1222; The following line may be uncommented and the value set to 1 to re-enable this
1223; deprecated behavior.  The default value is 0.
1224; DeprecatedEnvironmentVariableExpansion = 0
1225
1226; Turn on/off collapsing of bus ports in VCD dumpports output
1227DumpportsCollapse = 1
1228
1229; Location of Multi-Level Verification Component (MVC) installation.
1230; The default location is the product installation directory.
1231; MvcHome = $MODEL_TECH/...
1232
1233IgnoreError = 1
1234[lmc]
1235; The simulator's interface to Logic Modeling's SmartModel SWIFT software
1236libsm = $MODEL_TECH/libsm.sl
1237; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
1238; libsm = $MODEL_TECH/libsm.dll
1239;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
1240; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
1241;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
1242; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
1243;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
1244; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
1245;  Logic Modeling's SmartModel SWIFT software (Windows NT)
1246; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
1247;  Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
1248; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
1249;  Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
1250; libswift = $LMC_HOME/lib/linux.lib/libswift.so
1251
1252; The simulator's interface to Logic Modeling's hardware modeler SFI software
1253libhm = $MODEL_TECH/libhm.sl
1254; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
1255; libhm = $MODEL_TECH/libhm.dll
1256;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
1257; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
1258;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
1259; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
1260;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
1261; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
1262;  Logic Modeling's hardware modeler SFI software (Windows NT)
1263; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
1264;  Logic Modeling's hardware modeler SFI software (Linux)
1265; libsfi = <sfi_dir>/lib/linux/libsfi.so
1266
1267[msg_system]
1268; Change a message severity or suppress a message.
1269; The format is: <msg directive> = <msg number>[,<msg number>...]
1270; suppress can be used to achieve +nowarn<CODE> functionality
1271; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
1272; Examples:
1273;   note = 3009
1274;   warning = 3033
1275;   error = 3010,3016
1276;   fatal = 3016,3033
1277;   suppress = 3009,3016,3043
1278;   suppress = 3009,CNNODP,3043,TFMPC
1279; The command verror <msg number> can be used to get the complete
1280; description of a message.
1281
1282; Control transcripting of Verilog display system task messages and
1283; PLI/FLI print function call messages.  The system tasks include
1284; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho].  They
1285; also include the analogous file I/O tasks that write to STDOUT
1286; (i.e. $fwrite or $fdisplay).  The PLI/FLI calls include io_printf,
1287; vpi_printf, mti_PrintMessage, and mti_PrintFormatted.  The default
1288; is to have messages appear only in the transcript.  The other
1289; settings are to send messages to the wlf file only (messages that
1290; are recorded in the wlf file can be viewed in the MsgViewer) or
1291; to both the transcript and the wlf file.  The valid values are
1292;    tran  {transcript only (default)}
1293;    wlf   {wlf file only}
1294;    both  {transcript and wlf file}
1295; displaymsgmode = tran
1296
1297; Control transcripting of elaboration/runtime messages not
1298; addressed by the displaymsgmode setting.  The default is to
1299; have messages appear in the transcript and recorded in the wlf
1300; file (messages that are recorded in the wlf file can be viewed
1301; in the MsgViewer).  The other settings are to send messages
1302; only to the transcript or only to the wlf file.  The valid
1303; values are
1304;    both  {default}
1305;    tran  {transcript only}
1306;    wlf   {wlf file only}
1307; msgmode = both
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