1 | Release 12.3 par M.70d (nt64) |
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2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
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3 | |
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4 | GAMOM-PC:: Fri Aug 03 10:50:23 2012 |
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5 | |
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6 | par -w -intstyle ise -ol high -t 1 CORE_MPI_map.ncd CORE_MPI.ncd CORE_MPI.pcf |
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7 | |
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8 | |
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9 | Constraints file: CORE_MPI.pcf. |
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10 | Loading device for application Rf_Device from file '3s1200e.nph' in environment d:\Xilinx\12.3\ISE_DS\ISE\. |
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11 | "CORE_MPI" is an NCD, version 3.2, device xc3s1200e, package ft256, speed -5 |
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12 | vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv |
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13 | INFO:Security:54 - 'xc3s1200e' is a WebPack part. |
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14 | WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue |
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15 | to function, but you no longer qualify for Xilinx software updates or new releases. |
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16 | |
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17 | ---------------------------------------------------------------------- |
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18 | |
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19 | Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) |
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20 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) |
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21 | |
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22 | INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par |
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23 | -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all |
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24 | internal clocks in this design. Because there are not defined timing requirements, a timing score will not be |
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25 | reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. |
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26 | Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
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27 | |
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28 | Device speed data version: "PRODUCTION 1.27 2010-09-15". |
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29 | |
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30 | |
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31 | Design Summary Report: |
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32 | |
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33 | Number of External IOBs 95 out of 190 50% |
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34 | |
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35 | Number of External Input IOBs 31 |
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36 | |
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37 | Number of External Input IBUFs 31 |
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38 | |
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39 | Number of External Output IOBs 64 |
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40 | |
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41 | Number of External Output IOBs 64 |
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42 | |
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43 | Number of External Bidir IOBs 0 |
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44 | |
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45 | |
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46 | Number of BUFGMUXs 3 out of 24 12% |
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47 | Number of Slices 791 out of 8672 9% |
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48 | Number of SLICEMs 40 out of 4336 1% |
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49 | |
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50 | |
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51 | |
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52 | Overall effort level (-ol): High |
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53 | Placer effort level (-pl): High |
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54 | Placer cost table entry (-t): 1 |
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55 | Router effort level (-rl): High |
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56 | |
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57 | Starting initial Timing Analysis. REAL time: 4 secs |
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58 | Finished initial Timing Analysis. REAL time: 4 secs |
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59 | |
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60 | |
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61 | Starting Placer |
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62 | Total REAL time at the beginning of Placer: 4 secs |
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63 | Total CPU time at the beginning of Placer: 1 secs |
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64 | |
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65 | Phase 1.1 Initial Placement Analysis |
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66 | Phase 1.1 Initial Placement Analysis (Checksum:605e1) REAL time: 4 secs |
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67 | |
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68 | Phase 2.7 Design Feasibility Check |
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69 | Phase 2.7 Design Feasibility Check (Checksum:605e1) REAL time: 4 secs |
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70 | |
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71 | Phase 3.31 Local Placement Optimization |
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72 | Phase 3.31 Local Placement Optimization (Checksum:605e1) REAL time: 4 secs |
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73 | |
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74 | Phase 4.2 Initial Clock and IO Placement |
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75 | .... |
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76 | Phase 4.2 Initial Clock and IO Placement (Checksum:d0963d4) REAL time: 4 secs |
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77 | |
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78 | Phase 5.30 Global Clock Region Assignment |
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79 | Phase 5.30 Global Clock Region Assignment (Checksum:d0963d4) REAL time: 4 secs |
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80 | |
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81 | Phase 6.36 Local Placement Optimization |
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82 | Phase 6.36 Local Placement Optimization (Checksum:d0963d4) REAL time: 4 secs |
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83 | |
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84 | Phase 7.3 Local Placement Optimization |
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85 | ... |
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86 | Phase 7.3 Local Placement Optimization (Checksum:540caf82) REAL time: 5 secs |
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87 | |
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88 | Phase 8.5 Local Placement Optimization |
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89 | Phase 8.5 Local Placement Optimization (Checksum:540caf82) REAL time: 5 secs |
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90 | |
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91 | Phase 9.8 Global Placement |
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92 | ............................ |
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93 | ............................................................... |
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94 | ................................... |
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95 | ..................................................... |
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96 | .......................................................... |
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97 | Phase 9.8 Global Placement (Checksum:3441d173) REAL time: 11 secs |
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98 | |
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99 | Phase 10.5 Local Placement Optimization |
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100 | Phase 10.5 Local Placement Optimization (Checksum:3441d173) REAL time: 11 secs |
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101 | |
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102 | Phase 11.18 Placement Optimization |
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103 | Phase 11.18 Placement Optimization (Checksum:d6f58577) REAL time: 13 secs |
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104 | |
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105 | Phase 12.5 Local Placement Optimization |
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106 | Phase 12.5 Local Placement Optimization (Checksum:d6f58577) REAL time: 13 secs |
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107 | |
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108 | Total REAL time to Placer completion: 13 secs |
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109 | Total CPU time to Placer completion: 11 secs |
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110 | Writing design to file CORE_MPI.ncd |
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111 | |
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112 | |
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113 | |
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114 | Starting Router |
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115 | |
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116 | |
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117 | Phase 1 : 5847 unrouted; REAL time: 20 secs |
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118 | |
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119 | Phase 2 : 5365 unrouted; REAL time: 20 secs |
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120 | |
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121 | Phase 3 : 1243 unrouted; REAL time: 21 secs |
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122 | |
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123 | Phase 4 : 1368 unrouted; (Par is working to improve performance) REAL time: 22 secs |
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124 | |
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125 | Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 22 secs |
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126 | |
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127 | Updating file: CORE_MPI.ncd with current fully routed design. |
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128 | |
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129 | Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs |
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130 | |
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131 | Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 33 secs |
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132 | |
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133 | Updating file: CORE_MPI.ncd with current fully routed design. |
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134 | |
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135 | Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 35 secs |
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136 | |
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137 | Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 35 secs |
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138 | |
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139 | Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs |
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140 | |
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141 | Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs |
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142 | |
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143 | Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs |
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144 | WARNING:Route:455 - CLK Net:LD_instr/etloadinst_cmp_eq0022 may have excessive skew because |
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145 | 0 CLK pins and 2 NON_CLK pins failed to route using a CLK template. |
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146 | WARNING:Route:455 - CLK Net:LD_instr/etloadinst_cmp_eq0019 may have excessive skew because |
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147 | 0 CLK pins and 7 NON_CLK pins failed to route using a CLK template. |
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148 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/timeout_i_not0001 may have excessive skew because |
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149 | 4 CLK pins and 0 NON_CLK pins failed to route using a CLK template. |
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150 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/CM_RDY may have excessive skew because |
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151 | 1 CLK pins and 3 NON_CLK pins failed to route using a CLK template. |
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152 | WARNING:Route:455 - CLK Net:dma_data_in_not0001 may have excessive skew because |
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153 | 3 CLK pins and 0 NON_CLK pins failed to route using a CLK template. |
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154 | WARNING:Route:455 - CLK Net:MPI_CORE_EX1_FSM/ram_rd_or0000 may have excessive skew because |
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155 | 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. |
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156 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd11 may have excessive skew because |
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157 | 0 CLK pins and 13 NON_CLK pins failed to route using a CLK template. |
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158 | WARNING:Route:455 - CLK Net:MPI_CORE_EX2_FSM/ex2_state_mach_FSM_FFd18 may have excessive skew because |
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159 | 1 CLK pins and 5 NON_CLK pins failed to route using a CLK template. |
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160 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd12 may have excessive skew because |
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161 | 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. |
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162 | WARNING:Route:455 - CLK Net:IAck may have excessive skew because |
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163 | 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. |
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164 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 may have excessive skew because |
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165 | 0 CLK pins and 8 NON_CLK pins failed to route using a CLK template. |
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166 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 may have excessive skew because |
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167 | 1 CLK pins and 10 NON_CLK pins failed to route using a CLK template. |
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168 | WARNING:Route:455 - CLK Net:MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 may have excessive skew because |
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169 | 1 CLK pins and 4 NON_CLK pins failed to route using a CLK template. |
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170 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/DS_RDY may have excessive skew because |
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171 | 1 CLK pins and 18 NON_CLK pins failed to route using a CLK template. |
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172 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd9 may have excessive skew because |
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173 | 1 CLK pins and 24 NON_CLK pins failed to route using a CLK template. |
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174 | WARNING:Route:455 - CLK Net:MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd7 may have excessive skew because |
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175 | 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. |
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176 | WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 may have excessive skew because |
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177 | 0 CLK pins and 6 NON_CLK pins failed to route using a CLK template. |
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178 | WARNING:Route:455 - CLK Net:dma_rd_grant<3> may have excessive skew because |
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179 | 0 CLK pins and 97 NON_CLK pins failed to route using a CLK template. |
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180 | |
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181 | Total REAL time to Router completion: 36 secs |
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182 | Total CPU time to Router completion: 33 secs |
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183 | |
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184 | Partition Implementation Status |
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185 | ------------------------------- |
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186 | |
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187 | No Partitions were found in this design. |
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188 | |
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189 | ------------------------------- |
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190 | |
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191 | Generating "PAR" statistics. |
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192 | |
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193 | ************************** |
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194 | Generating Clock Report |
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195 | ************************** |
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196 | |
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197 | +---------------------+--------------+------+------+------------+-------------+ |
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198 | | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| |
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199 | +---------------------+--------------+------+------+------------+-------------+ |
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200 | | clkout_OBUF | BUFGMUX_X2Y10| No | 289 | 0.178 | 0.328 | |
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201 | +---------------------+--------------+------+------+------------+-------------+ |
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202 | |LD_instr/etloadinst_ | | | | | | |
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203 | | cmp_eq0020 | BUFGMUX_X1Y10| No | 17 | 0.069 | 0.225 | |
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204 | +---------------------+--------------+------+------+------------+-------------+ |
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205 | |MPI_CORE_EX4_FSM/stI | | | | | | |
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206 | | nit2_FSM_FFd2 | BUFGMUX_X1Y0| No | 26 | 0.108 | 0.325 | |
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207 | +---------------------+--------------+------+------+------------+-------------+ |
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208 | | dma_rd_grant<3> | Local| | 105 | 0.099 | 2.200 | |
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209 | +---------------------+--------------+------+------+------------+-------------+ |
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210 | |LD_instr/Mtrien_Ram_ | | | | | | |
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211 | | address_i_not0001 | Local| | 1 | 0.000 | 0.742 | |
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212 | +---------------------+--------------+------+------+------------+-------------+ |
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213 | |MPI_CORE_EX4_FSM/stI | | | | | | |
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214 | | nit2_FSM_FFd9 | Local| | 25 | 0.000 | 1.150 | |
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215 | +---------------------+--------------+------+------+------------+-------------+ |
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216 | |MPI_CORE_EX4_FSM/stI | | | | | | |
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217 | | nit2_FSM_FFd11 | Local| | 15 | 0.000 | 1.752 | |
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218 | +---------------------+--------------+------+------+------------+-------------+ |
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219 | |MPI_CORE_EX4_FSM/stI | | | | | | |
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220 | | nit2_FSM_FFd12 | Local| | 12 | 0.000 | 1.825 | |
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221 | +---------------------+--------------+------+------+------------+-------------+ |
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222 | |MPI_CORE_EX4_FSM/Nex | | | | | | |
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223 | | tRank_or0000 | Local| | 5 | 0.008 | 1.288 | |
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224 | +---------------------+--------------+------+------+------------+-------------+ |
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225 | |MPI_CORE_EX4_FSM/DS_ | | | | | | |
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226 | | RDY | Local| | 24 | 0.739 | 2.022 | |
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227 | +---------------------+--------------+------+------+------------+-------------+ |
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228 | |LD_instr/count_i_not | | | | | | |
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229 | | 0001 | Local| | 10 | 0.065 | 1.634 | |
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230 | +---------------------+--------------+------+------+------------+-------------+ |
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231 | |LD_instr/Mtridata_Ra | | | | | | |
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232 | | m_address_i_not0001 | Local| | 14 | 0.212 | 1.819 | |
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233 | +---------------------+--------------+------+------+------------+-------------+ |
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234 | |LD_instr/etloadinst_ | | | | | | |
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235 | | cmp_eq0022 | Local| | 7 | 0.238 | 2.258 | |
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236 | +---------------------+--------------+------+------+------------+-------------+ |
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237 | |LD_instr/etloadinst_ | | | | | | |
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238 | | cmp_eq0019 | Local| | 11 | 0.132 | 1.645 | |
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239 | +---------------------+--------------+------+------+------------+-------------+ |
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240 | |MPI_CORE_EX4_FSM/stI | | | | | | |
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241 | | nit2_FSM_FFd10 | Local| | 11 | 0.000 | 1.166 | |
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242 | +---------------------+--------------+------+------+------------+-------------+ |
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243 | |MPI_CORE_EX4_FSM/Por | | | | | | |
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244 | | tNum_i_or0000 | Local| | 2 | 0.003 | 1.577 | |
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245 | +---------------------+--------------+------+------+------------+-------------+ |
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246 | |MPI_CORE_EX4_FSM/CTR | | | | | | |
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247 | | _or0000 | Local| | 1 | 0.000 | 0.980 | |
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248 | +---------------------+--------------+------+------+------------+-------------+ |
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249 | |MPI_CORE_EX1_FSM/ex1 | | | | | | |
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250 | |_state_mach_FSM_FFd7 | | | | | | |
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251 | | | Local| | 12 | 0.000 | 2.998 | |
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252 | +---------------------+--------------+------+------+------------+-------------+ |
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253 | |MPI_CORE_DMA_ARBITER | | | | | | |
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254 | |/dma_wr_grant_0_not0 | | | | | | |
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255 | | 001 | Local| | 1 | 0.000 | 0.979 | |
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256 | +---------------------+--------------+------+------+------------+-------------+ |
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257 | |MPI_CORE_EX4_FSM/Dat | | | | | | |
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258 | | aRam_or0000 | Local| | 4 | 0.002 | 1.323 | |
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259 | +---------------------+--------------+------+------+------------+-------------+ |
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260 | |MPI_CORE_EX4_FSM/Ran | | | | | | |
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261 | | kAsked_i_or0000 | Local| | 1 | 0.000 | 0.742 | |
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262 | +---------------------+--------------+------+------+------------+-------------+ |
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263 | |MPI_CORE_EX4_FSM/tim | | | | | | |
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264 | | eout_i_not0001 | Local| | 5 | 1.297 | 3.312 | |
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265 | +---------------------+--------------+------+------+------------+-------------+ |
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266 | |MPI_CORE_EX1_FSM/App | | | | | | |
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267 | | InitReq_or0000 | Local| | 1 | 0.000 | 0.717 | |
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268 | +---------------------+--------------+------+------+------------+-------------+ |
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269 | | IAck | Local| | 2 | 0.000 | 0.947 | |
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270 | +---------------------+--------------+------+------+------------+-------------+ |
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271 | |MPI_CORE_DMA_ARBITER | | | | | | |
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272 | |/dma_rd_grant_0_not0 | | | | | | |
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273 | | 001 | Local| | 1 | 0.000 | 0.938 | |
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274 | +---------------------+--------------+------+------+------------+-------------+ |
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275 | |MPI_CORE_EX4_FSM/Dat | | | | | | |
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276 | | aToSend_0_or0000 | Local| | 3 | 0.178 | 1.759 | |
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277 | +---------------------+--------------+------+------+------------+-------------+ |
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278 | |MPI_CORE_EX4_FSM/Dat | | | | | | |
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279 | | alen_or0000 | Local| | 3 | 0.034 | 1.010 | |
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280 | +---------------------+--------------+------+------+------------+-------------+ |
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281 | |MPI_CORE_DMA_ARBITER | | | | | | |
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282 | |/dma_wr_grant_1_cmp_ | | | | | | |
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283 | | eq0000 | Local| | 1 | 0.000 | 0.245 | |
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284 | +---------------------+--------------+------+------+------------+-------------+ |
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285 | |MPI_CORE_EX2_FSM/fif | | | | | | |
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286 | | o_wr_en_or0000 | Local| | 1 | 0.000 | 0.245 | |
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287 | +---------------------+--------------+------+------+------------+-------------+ |
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288 | |MPI_CORE_EX2_FSM/ex2 | | | | | | |
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289 | |_state_mach_FSM_FFd1 | | | | | | |
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290 | | 8 | Local| | 6 | 0.000 | 0.634 | |
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291 | +---------------------+--------------+------+------+------------+-------------+ |
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292 | |MPI_CORE_EX4_FSM/Cmd | | | | | | |
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293 | |Received_2_cmp_eq000 | | | | | | |
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294 | | 0 | Local| | 5 | 0.009 | 1.615 | |
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295 | +---------------------+--------------+------+------+------------+-------------+ |
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296 | |MPI_CORE_EX4_FSM/etc | | | | | | |
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297 | | md_FSM_FFd9 | Local| | 9 | 0.118 | 1.860 | |
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298 | +---------------------+--------------+------+------+------------+-------------+ |
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299 | |MPI_CORE_DMA_ARBITER | | | | | | |
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300 | |/dma_rd_grant_3_cmp_ | | | | | | |
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301 | | eq0000 | Local| | 5 | 0.000 | 0.997 | |
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302 | +---------------------+--------------+------+------+------------+-------------+ |
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303 | |MPI_CORE_DMA_ARBITER | | | | | | |
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304 | |/dma_rd_grant_1_cmp_ | | | | | | |
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305 | | eq0000 | Local| | 1 | 0.000 | 0.245 | |
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306 | +---------------------+--------------+------+------+------------+-------------+ |
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307 | |MPI_CORE_DMA_ARBITER | | | | | | |
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308 | |/dma_wr_grant_2_cmp_ | | | | | | |
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309 | | eq0000 | Local| | 1 | 0.000 | 0.979 | |
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310 | +---------------------+--------------+------+------+------------+-------------+ |
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311 | |MPI_CORE_EX4_FSM/CM_ | | | | | | |
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312 | | RDY | Local| | 4 | 0.000 | 0.557 | |
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313 | +---------------------+--------------+------+------+------------+-------------+ |
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314 | |LD_instr/timeout_not | | | | | | |
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315 | | 0001 | Local| | 6 | 0.183 | 1.801 | |
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316 | +---------------------+--------------+------+------+------------+-------------+ |
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317 | |MPI_CORE_DMA_ARBITER | | | | | | |
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318 | |/dma_rd_grant_2_cmp_ | | | | | | |
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319 | | eq0000 | Local| | 1 | 0.000 | 0.245 | |
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320 | +---------------------+--------------+------+------+------------+-------------+ |
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321 | |MPI_CORE_DMA_ARBITER | | | | | | |
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322 | |/dma_wr_grant_3_cmp_ | | | | | | |
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323 | | eq0000 | Local| | 1 | 0.000 | 0.245 | |
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324 | +---------------------+--------------+------+------+------------+-------------+ |
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325 | |LD_instr/fifo_wr_i_n | | | | | | |
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326 | | ot0001 | Local| | 1 | 0.000 | 0.745 | |
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327 | +---------------------+--------------+------+------+------------+-------------+ |
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328 | |MPI_CORE_EX4_FSM/stI | | | | | | |
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329 | | nit2_FSM_FFd5 | Local| | 11 | 0.031 | 1.936 | |
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330 | +---------------------+--------------+------+------+------------+-------------+ |
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331 | |MPI_CORE_EX4_FSM/WeR | | | | | | |
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332 | | am_or0000 | Local| | 1 | 0.000 | 0.981 | |
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333 | +---------------------+--------------+------+------+------------+-------------+ |
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334 | | dma_data_in_not0001 | Local| | 5 | 0.784 | 2.286 | |
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335 | +---------------------+--------------+------+------+------------+-------------+ |
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336 | |MPI_CORE_EX4_FSM/DS_ | | | | | | |
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337 | | Ack_or0000 | Local| | 1 | 0.000 | 0.757 | |
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338 | +---------------------+--------------+------+------+------------+-------------+ |
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339 | |MPI_CORE_EX1_FSM/ram | | | | | | |
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340 | | _rd_or0000 | Local| | 2 | 0.000 | 0.733 | |
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341 | +---------------------+--------------+------+------+------------+-------------+ |
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342 | |MPI_CORE_EX1_FSM/ram | | | | | | |
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343 | | _wr_or0000 | Local| | 1 | 0.000 | 1.040 | |
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344 | +---------------------+--------------+------+------+------------+-------------+ |
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345 | |MPI_CORE_EX1_FSM/Res | | | | | | |
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346 | | ult_1_or0000 | Local| | 1 | 0.000 | 1.339 | |
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347 | +---------------------+--------------+------+------+------------+-------------+ |
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348 | |
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349 | * Net Skew is the difference between the minimum and maximum routing |
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350 | only delays for the net. Note this is different from Clock Skew which |
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351 | is reported in TRCE timing report. Clock Skew is the difference between |
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352 | the minimum and maximum path delays which includes logic delays. |
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353 | |
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354 | Timing Score: 0 (Setup: 0, Hold: 0) |
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355 | |
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356 | Asterisk (*) preceding a constraint indicates it was not met. |
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357 | This may be due to a setup or hold violation. |
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358 | |
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359 | ---------------------------------------------------------------------------------------------------------- |
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360 | Constraint | Check | Worst Case | Best Case | Timing | Timing |
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361 | | | Slack | Achievable | Errors | Score |
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362 | ---------------------------------------------------------------------------------------------------------- |
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363 | Autotimespec constraint for clock net clk | SETUP | N/A| 7.585ns| N/A| 0 |
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364 | out_OBUF | HOLD | 0.627ns| | 0| 0 |
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365 | ---------------------------------------------------------------------------------------------------------- |
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366 | Autotimespec constraint for clock net dma | SETUP | N/A| 2.016ns| N/A| 0 |
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367 | _rd_grant<3> | HOLD | 1.200ns| | 0| 0 |
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368 | ---------------------------------------------------------------------------------------------------------- |
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369 | Autotimespec constraint for clock net MPI | SETUP | N/A| 4.044ns| N/A| 0 |
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370 | _CORE_EX4_FSM/NextRank_or0000 | HOLD | 1.076ns| | 0| 0 |
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371 | ---------------------------------------------------------------------------------------------------------- |
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372 | Autotimespec constraint for clock net LD_ | SETUP | N/A| 6.878ns| N/A| 0 |
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373 | instr/Mtridata_Ram_address_i_not0001 | HOLD | 1.411ns| | 0| 0 |
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374 | ---------------------------------------------------------------------------------------------------------- |
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375 | Autotimespec constraint for clock net LD_ | SETUP | N/A| 5.451ns| N/A| 0 |
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376 | instr/etloadinst_cmp_eq0020 | HOLD | 1.200ns| | 0| 0 |
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377 | ---------------------------------------------------------------------------------------------------------- |
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378 | Autotimespec constraint for clock net MPI | SETUP | N/A| 1.807ns| N/A| 0 |
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379 | _CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 | HOLD | 1.200ns| | 0| 0 |
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380 | ---------------------------------------------------------------------------------------------------------- |
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381 | Autotimespec constraint for clock net LD_ | SETUP | N/A| 3.654ns| N/A| 0 |
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382 | instr/timeout_not0001 | HOLD | 1.408ns| | 0| 0 |
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383 | ---------------------------------------------------------------------------------------------------------- |
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384 | Autotimespec constraint for clock net MPI | SETUP | N/A| 3.476ns| N/A| 0 |
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385 | _CORE_EX4_FSM/stInit2_FSM_FFd2 | HOLD | 1.450ns| | 0| 0 |
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386 | ---------------------------------------------------------------------------------------------------------- |
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387 | |
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388 | |
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389 | All constraints were met. |
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390 | INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the |
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391 | constraint is not analyzed due to the following: No paths covered by this |
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392 | constraint; Other constraints intersect with this constraint; or This |
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393 | constraint was disabled by a Path Tracing Control. Please run the Timespec |
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394 | Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. |
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395 | |
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396 | |
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397 | Generating Pad Report. |
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398 | |
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399 | All signals are completely routed. |
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400 | |
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401 | Total REAL time to PAR completion: 37 secs |
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402 | Total CPU time to PAR completion: 34 secs |
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403 | |
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404 | Peak Memory Usage: 315 MB |
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405 | |
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406 | Placement: Completed - No errors found. |
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407 | Routing: Completed - No errors found. |
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408 | |
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409 | Number of error messages: 0 |
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410 | Number of warning messages: 18 |
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411 | Number of info messages: 1 |
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412 | |
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413 | Writing design to file CORE_MPI.ncd |
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414 | |
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415 | |
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416 | |
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417 | PAR done! |
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