[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 04:35:05 10/15/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: FIfo_mem - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | |
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| 21 | library IEEE; |
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| 22 | use IEEE.std_logic_1164.all; |
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| 23 | use IEEE.std_logic_unsigned.all; |
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| 24 | entity FIFO_LOGIC is |
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| 25 | generic (N: integer := 3); |
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| 26 | port (CLK, PUSH, POP, INIT: in std_logic; |
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| 27 | ADD: out std_logic_vector(N-1 downto 0); |
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| 28 | FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); |
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| 29 | end entity FIFO_LOGIC; |
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| 30 | architecture RTL of FIFO_LOGIC is |
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| 31 | signal WPTR, RPTR: std_logic_vector(N-1 downto 0); |
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| 32 | signal LASTOP: std_logic; |
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| 33 | begin |
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| 34 | SYNC: process (CLK) begin |
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| 35 | if (CLK'event and CLK = '1') then |
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| 36 | if (INIT = '1') then -- initialization -- |
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| 37 | WPTR <= (others => '0'); |
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| 38 | RPTR <= (others => '0'); |
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| 39 | LASTOP <= '0'; |
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| 40 | elsif (POP = '1' and EMPTY = '0') then -- pop -- |
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| 41 | RPTR <= RPTR + 1; |
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| 42 | LASTOP <= '0'; |
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| 43 | elsif (PUSH = '1' and FULL = '0') then -- push -- |
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| 44 | WPTR <= WPTR + 1; |
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| 45 | LASTOP <= '1'; |
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| 46 | end if; -- otherwise all Fs hold their value -- |
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| 47 | end if; |
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| 48 | end process SYNC; |
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| 49 | COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY) begin |
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| 50 | -- full and empty flags -- |
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| 51 | if (RPTR = WPTR) then |
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| 52 | if (LASTOP = '1') then |
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| 53 | FULL <= '1'; |
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| 54 | EMPTY <= '0'; |
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| 55 | else |
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| 56 | FULL <= '0'; |
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| 57 | EMPTY <= '1'; |
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| 58 | end if; |
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| 59 | else |
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| 60 | FULL <= '0'; |
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| 61 | EMPTY <= '0'; |
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| 62 | end if; |
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| 63 | -- address, write enable and nopush/nopop logic -- |
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| 64 | if (POP = '0' and PUSH = '0') then -- no operation -- |
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| 65 | ADD <= RPTR; |
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| 66 | WE <= '0'; |
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| 67 | NOPUSH <= '0'; |
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| 68 | NOPOP <= '0'; |
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| 69 | elsif (POP = '0' and PUSH = '1') then -- push only -- |
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| 70 | ADD <= WPTR; |
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| 71 | NOPOP <= '0'; |
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| 72 | if (FULL = '0') then -- valid write condition -- |
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| 73 | WE <= '1'; |
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| 74 | NOPUSH <= '0'; |
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| 75 | else -- no write condition -- |
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| 76 | WE <= '0'; |
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| 77 | NOPUSH <= '1'; |
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| 78 | end if; |
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| 79 | elsif (POP = '1' and PUSH = '0') then -- pop only -- |
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| 80 | ADD <= RPTR; |
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| 81 | NOPUSH <= '0'; |
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| 82 | WE <= '0'; |
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| 83 | if (EMPTY = '0') then -- valid read condition -- |
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| 84 | NOPOP <= '0'; |
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| 85 | else |
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| 86 | NOPOP <= '1'; -- no red condition -- |
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| 87 | end if; |
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| 88 | else -- push and pop at same time - |
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| 89 | if (EMPTY = '0') then -- valid pop -- |
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| 90 | ADD <= RPTR; |
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| 91 | WE <= '0'; |
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| 92 | NOPUSH <= '1'; |
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| 93 | NOPOP <= '0'; |
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| 94 | else |
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| 95 | ADD <= wptr; |
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| 96 | WE <= '1'; |
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| 97 | NOPUSH <= '0'; |
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| 98 | NOPOP <= '1'; |
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| 99 | end if; |
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| 100 | end if; |
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| 101 | end process COMB; |
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| 102 | end architecture RTL; |
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