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1	Release 12.3 Map M.70d (nt64)
2	Xilinx Mapping Report File for Design 'MPI_NOC'
3
4	Design Information
5	------------------
6	Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off
7	-c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf
8	Target Device : xc3s1200e
9	Target Package : ft256
10	Target Speed : -5
11	Mapper Version : spartan3e -- $Revision: 1.52 $
12	Mapped Date : Fri Aug 03 10:15:46 2012
13
14	Design Summary
15	--------------
16	Number of errors: 0
17	Number of warnings: 80
18	Logic Utilization:
19	Total Number Slice Registers: 1,420 out of 17,344 8%
20	Number used as Flip Flops: 883
21	Number used as Latches: 537
22	Number of 4 input LUTs: 2,986 out of 17,344 17%
23	Logic Distribution:
24	Number of occupied Slices: 1,832 out of 8,672 21%
25	Number of Slices containing only related logic: 1,832 out of 1,832 100%
26	Number of Slices containing unrelated logic: 0 out of 1,832 0%
27	*See NOTES below for an explanation of the effects of unrelated logic.
28	Total Number of 4 input LUTs: 3,188 out of 17,344 18%
29	Number used as logic: 2,826
30	Number used as a route-thru: 202
31	Number used for Dual Port RAMs: 160
32	(Two LUTs used per Dual Port RAM)
33
34	The Slice Logic Distribution report is not meaningful if the design is
35	over-mapped for a non-slice resource or if Placement fails.
36
37	Number of bonded IOBs: 146 out of 190 76%
38	Number of RAMB16s: 4 out of 28 14%
39	Number of BUFGMUXs: 5 out of 24 20%
40
41	Average Fanout of Non-Clock Nets: 3.61
42
43	Peak Memory Usage: 289 MB
44	Total REAL time to MAP completion: 10 secs
45	Total CPU time to MAP completion: 5 secs
46
47	NOTES:
48
49	Related logic is defined as being logic that shares connectivity - e.g. two
50	LUTs are "related" if they share common inputs. When assembling slices,
51	Map gives priority to combine logic that is related. Doing so results in
52	the best timing performance.
53
54	Unrelated logic shares no connectivity. Map will only begin packing
55	unrelated logic into a slice once 99% of the slices are occupied through
56	related logic packing.
57
58	Note that once logic distribution reaches the 99% level through related
59	logic packing, this does not mean the device is completely utilized.
60	Unrelated logic packing will then begin, continuing until all usable LUTs
61	and FFs are occupied. Depending on your timing budget, increased levels of
62	unrelated logic packing may adversely affect the overall timing performance
63	of your design.
64
65	Table of Contents
66	-----------------
67	Section 1 - Errors
68	Section 2 - Warnings
69	Section 3 - Informational
70	Section 4 - Removed Logic Summary
71	Section 5 - Removed Logic
72	Section 6 - IOB Properties
73	Section 7 - RPMs
74	Section 8 - Guide Report
75	Section 9 - Area Group and Partition Summary
76	Section 10 - Timing Report
77	Section 11 - Configuration String Information
78	Section 12 - Control Set Information
79	Section 13 - Utilization by Hierarchy
80
81	Section 1 - Errors
82	------------------
83
84	Section 2 - Warnings
85	--------------------
86	WARNING:Security:42 - Your software subscription period has lapsed. Your current
87	version of Xilinx tools will continue to function, but you no longer qualify for
88	Xilinx software updates or new releases.
89	WARNING:PhysDesignRules:372 - Gated clock. Clock net
90	connect_core[1].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin.
91	This is not good design practice. Use the CE pin to control the loading of
92	data into the flip-flop.
93	WARNING:PhysDesignRules:372 - Gated clock. Clock net
94	connect_core[2].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin.
95	This is not good design practice. Use the CE pin to control the loading of
96	data into the flip-flop.
97	WARNING:PhysDesignRules:372 - Gated clock. Clock net
98	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is
99	sourced by a combinatorial pin. This is not good design practice. Use the CE
100	pin to control the loading of data into the flip-flop.
101	WARNING:PhysDesignRules:372 - Gated clock. Clock net
102	connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a
103	combinatorial pin. This is not good design practice. Use the CE pin to
104	control the loading of data into the flip-flop.
105	WARNING:PhysDesignRules:372 - Gated clock. Clock net
106	connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a
107	combinatorial pin. This is not good design practice. Use the CE pin to
108	control the loading of data into the flip-flop.
109	WARNING:PhysDesignRules:372 - Gated clock. Clock net
110	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a
111	combinatorial pin. This is not good design practice. Use the CE pin to
112	control the loading of data into the flip-flop.
113	WARNING:PhysDesignRules:372 - Gated clock. Clock net
114	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a
115	combinatorial pin. This is not good design practice. Use the CE pin to
116	control the loading of data into the flip-flop.
117	WARNING:PhysDesignRules:372 - Gated clock. Clock net
118	connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by
119	a combinatorial pin. This is not good design practice. Use the CE pin to
120	control the loading of data into the flip-flop.
121	WARNING:PhysDesignRules:372 - Gated clock. Clock net
122	connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by
123	a combinatorial pin. This is not good design practice. Use the CE pin to
124	control the loading of data into the flip-flop.
125	WARNING:PhysDesignRules:372 - Gated clock. Clock net
126	connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a
127	combinatorial pin. This is not good design practice. Use the CE pin to
128	control the loading of data into the flip-flop.
129	WARNING:PhysDesignRules:372 - Gated clock. Clock net
130	connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a
131	combinatorial pin. This is not good design practice. Use the CE pin to
132	control the loading of data into the flip-flop.
133	WARNING:PhysDesignRules:372 - Gated clock. Clock net
134	connect_core[1].hardmpi/LD_instr/count_i_not0001 is sourced by a
135	combinatorial pin. This is not good design practice. Use the CE pin to
136	control the loading of data into the flip-flop.
137	WARNING:PhysDesignRules:372 - Gated clock. Clock net
138	connect_core[2].hardmpi/LD_instr/count_i_not0001 is sourced by a
139	combinatorial pin. This is not good design practice. Use the CE pin to
140	control the loading of data into the flip-flop.
141	WARNING:PhysDesignRules:372 - Gated clock. Clock net
142	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is
143	sourced by a combinatorial pin. This is not good design practice. Use the CE
144	pin to control the loading of data into the flip-flop.
145	WARNING:PhysDesignRules:372 - Gated clock. Clock net
146	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is
147	sourced by a combinatorial pin. This is not good design practice. Use the CE
148	pin to control the loading of data into the flip-flop.
149	WARNING:PhysDesignRules:372 - Gated clock. Clock net
150	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is
151	sourced by a combinatorial pin. This is not good design practice. Use the CE
152	pin to control the loading of data into the flip-flop.
153	WARNING:PhysDesignRules:372 - Gated clock. Clock net
154	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is
155	sourced by a combinatorial pin. This is not good design practice. Use the CE
156	pin to control the loading of data into the flip-flop.
157	WARNING:PhysDesignRules:372 - Gated clock. Clock net
158	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is
159	sourced by a combinatorial pin. This is not good design practice. Use the CE
160	pin to control the loading of data into the flip-flop.
161	WARNING:PhysDesignRules:372 - Gated clock. Clock net
162	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is
163	sourced by a combinatorial pin. This is not good design practice. Use the CE
164	pin to control the loading of data into the flip-flop.
165	WARNING:PhysDesignRules:372 - Gated clock. Clock net
166	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is
167	sourced by a combinatorial pin. This is not good design practice. Use the CE
168	pin to control the loading of data into the flip-flop.
169	WARNING:PhysDesignRules:372 - Gated clock. Clock net
170	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is
171	sourced by a combinatorial pin. This is not good design practice. Use the CE
172	pin to control the loading of data into the flip-flop.
173	WARNING:PhysDesignRules:372 - Gated clock. Clock net
174	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a
175	combinatorial pin. This is not good design practice. Use the CE pin to
176	control the loading of data into the flip-flop.
177	WARNING:PhysDesignRules:372 - Gated clock. Clock net
178	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a
179	combinatorial pin. This is not good design practice. Use the CE pin to
180	control the loading of data into the flip-flop.
181	WARNING:PhysDesignRules:372 - Gated clock. Clock net
182	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000 is
183	sourced by a combinatorial pin. This is not good design practice. Use the CE
184	pin to control the loading of data into the flip-flop.
185	WARNING:PhysDesignRules:372 - Gated clock. Clock net
186	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is
187	sourced by a combinatorial pin. This is not good design practice. Use the CE
188	pin to control the loading of data into the flip-flop.
189	WARNING:PhysDesignRules:372 - Gated clock. Clock net
190	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a
191	combinatorial pin. This is not good design practice. Use the CE pin to
192	control the loading of data into the flip-flop.
193	WARNING:PhysDesignRules:372 - Gated clock. Clock net
194	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a
195	combinatorial pin. This is not good design practice. Use the CE pin to
196	control the loading of data into the flip-flop.
197	WARNING:PhysDesignRules:372 - Gated clock. Clock net
198	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a
199	combinatorial pin. This is not good design practice. Use the CE pin to
200	control the loading of data into the flip-flop.
201	WARNING:PhysDesignRules:372 - Gated clock. Clock net
202	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a
203	combinatorial pin. This is not good design practice. Use the CE pin to
204	control the loading of data into the flip-flop.
205	WARNING:PhysDesignRules:372 - Gated clock. Clock net
206	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000 is
207	sourced by a combinatorial pin. This is not good design practice. Use the CE
208	pin to control the loading of data into the flip-flop.
209	WARNING:PhysDesignRules:372 - Gated clock. Clock net
210	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000
211	is sourced by a combinatorial pin. This is not good design practice. Use the
212	CE pin to control the loading of data into the flip-flop.
213	WARNING:PhysDesignRules:372 - Gated clock. Clock net
214	connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a
215	combinatorial pin. This is not good design practice. Use the CE pin to
216	control the loading of data into the flip-flop.
217	WARNING:PhysDesignRules:372 - Gated clock. Clock net
218	connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a
219	combinatorial pin. This is not good design practice. Use the CE pin to
220	control the loading of data into the flip-flop.
221	WARNING:PhysDesignRules:372 - Gated clock. Clock net
222	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is
223	sourced by a combinatorial pin. This is not good design practice. Use the CE
224	pin to control the loading of data into the flip-flop.
225	WARNING:PhysDesignRules:372 - Gated clock. Clock net
226	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is
227	sourced by a combinatorial pin. This is not good design practice. Use the CE
228	pin to control the loading of data into the flip-flop.
229	WARNING:PhysDesignRules:372 - Gated clock. Clock net
230	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000
231	is sourced by a combinatorial pin. This is not good design practice. Use the
232	CE pin to control the loading of data into the flip-flop.
233	WARNING:PhysDesignRules:372 - Gated clock. Clock net
234	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is
235	sourced by a combinatorial pin. This is not good design practice. Use the CE
236	pin to control the loading of data into the flip-flop.
237	WARNING:PhysDesignRules:372 - Gated clock. Clock net
238	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is
239	sourced by a combinatorial pin. This is not good design practice. Use the CE
240	pin to control the loading of data into the flip-flop.
241	WARNING:PhysDesignRules:372 - Gated clock. Clock net
242	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is
243	sourced by a combinatorial pin. This is not good design practice. Use the CE
244	pin to control the loading of data into the flip-flop.
245	WARNING:PhysDesignRules:372 - Gated clock. Clock net
246	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is
247	sourced by a combinatorial pin. This is not good design practice. Use the CE
248	pin to control the loading of data into the flip-flop.
249	WARNING:PhysDesignRules:372 - Gated clock. Clock net
250	connect_core[1].hardmpi/LD_instr/timeout_not0001 is sourced by a
251	combinatorial pin. This is not good design practice. Use the CE pin to
252	control the loading of data into the flip-flop.
253	WARNING:PhysDesignRules:372 - Gated clock. Clock net
254	connect_core[1].hardmpi/dma_data_in_not0001 is sourced by a combinatorial
255	pin. This is not good design practice. Use the CE pin to control the loading
256	of data into the flip-flop.
257	WARNING:PhysDesignRules:372 - Gated clock. Clock net
258	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is
259	sourced by a combinatorial pin. This is not good design practice. Use the CE
260	pin to control the loading of data into the flip-flop.
261	WARNING:PhysDesignRules:372 - Gated clock. Clock net
262	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is
263	sourced by a combinatorial pin. This is not good design practice. Use the CE
264	pin to control the loading of data into the flip-flop.
265	WARNING:PhysDesignRules:372 - Gated clock. Clock net
266	connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is
267	sourced by a combinatorial pin. This is not good design practice. Use the CE
268	pin to control the loading of data into the flip-flop.
269	WARNING:PhysDesignRules:372 - Gated clock. Clock net
270	connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is
271	sourced by a combinatorial pin. This is not good design practice. Use the CE
272	pin to control the loading of data into the flip-flop.
273	WARNING:PhysDesignRules:372 - Gated clock. Clock net
274	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a
275	combinatorial pin. This is not good design practice. Use the CE pin to
276	control the loading of data into the flip-flop.
277	WARNING:PhysDesignRules:372 - Gated clock. Clock net
278	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a
279	combinatorial pin. This is not good design practice. Use the CE pin to
280	control the loading of data into the flip-flop.
281	WARNING:PhysDesignRules:372 - Gated clock. Clock net
282	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a
283	combinatorial pin. This is not good design practice. Use the CE pin to
284	control the loading of data into the flip-flop.
285	WARNING:PhysDesignRules:372 - Gated clock. Clock net
286	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a
287	combinatorial pin. This is not good design practice. Use the CE pin to
288	control the loading of data into the flip-flop.
289	WARNING:PhysDesignRules:372 - Gated clock. Clock net
290	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00
291	00 is sourced by a combinatorial pin. This is not good design practice. Use
292	the CE pin to control the loading of data into the flip-flop.
293	WARNING:PhysDesignRules:372 - Gated clock. Clock net
294	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00
295	00 is sourced by a combinatorial pin. This is not good design practice. Use
296	the CE pin to control the loading of data into the flip-flop.
297	WARNING:PhysDesignRules:372 - Gated clock. Clock net
298	connect_core[2].hardmpi/dma_data_in_not0001 is sourced by a combinatorial
299	pin. This is not good design practice. Use the CE pin to control the loading
300	of data into the flip-flop.
301	WARNING:PhysDesignRules:372 - Gated clock. Clock net
302	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a
303	combinatorial pin. This is not good design practice. Use the CE pin to
304	control the loading of data into the flip-flop.
305	WARNING:PhysDesignRules:372 - Gated clock. Clock net
306	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a
307	combinatorial pin. This is not good design practice. Use the CE pin to
308	control the loading of data into the flip-flop.
309	WARNING:PhysDesignRules:372 - Gated clock. Clock net
310	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a
311	combinatorial pin. This is not good design practice. Use the CE pin to
312	control the loading of data into the flip-flop.
313	WARNING:PhysDesignRules:372 - Gated clock. Clock net
314	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a
315	combinatorial pin. This is not good design practice. Use the CE pin to
316	control the loading of data into the flip-flop.
317	WARNING:PhysDesignRules:372 - Gated clock. Clock net
318	connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a
319	combinatorial pin. This is not good design practice. Use the CE pin to
320	control the loading of data into the flip-flop.
321	WARNING:PhysDesignRules:372 - Gated clock. Clock net
322	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a
323	combinatorial pin. This is not good design practice. Use the CE pin to
324	control the loading of data into the flip-flop.
325	WARNING:PhysDesignRules:372 - Gated clock. Clock net
326	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a
327	combinatorial pin. This is not good design practice. Use the CE pin to
328	control the loading of data into the flip-flop.
329	WARNING:PhysDesignRules:372 - Gated clock. Clock net
330	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000 is
331	sourced by a combinatorial pin. This is not good design practice. Use the CE
332	pin to control the loading of data into the flip-flop.
333	WARNING:PhysDesignRules:372 - Gated clock. Clock net
334	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000 is
335	sourced by a combinatorial pin. This is not good design practice. Use the CE
336	pin to control the loading of data into the flip-flop.
337	WARNING:PhysDesignRules:372 - Gated clock. Clock net
338	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a
339	combinatorial pin. This is not good design practice. Use the CE pin to
340	control the loading of data into the flip-flop.
341	WARNING:PhysDesignRules:372 - Gated clock. Clock net
342	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a
343	combinatorial pin. This is not good design practice. Use the CE pin to
344	control the loading of data into the flip-flop.
345	WARNING:PhysDesignRules:372 - Gated clock. Clock net
346	connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a
347	combinatorial pin. This is not good design practice. Use the CE pin to
348	control the loading of data into the flip-flop.
349	WARNING:PhysDesignRules:372 - Gated clock. Clock net
350	connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a
351	combinatorial pin. This is not good design practice. Use the CE pin to
352	control the loading of data into the flip-flop.
353	WARNING:PhysDesignRules:372 - Gated clock. Clock net
354	connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a
355	combinatorial pin. This is not good design practice. Use the CE pin to
356	control the loading of data into the flip-flop.
357	WARNING:PhysDesignRules:372 - Gated clock. Clock net
358	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or
359	0000 is sourced by a combinatorial pin. This is not good design practice. Use
360	the CE pin to control the loading of data into the flip-flop.
361	WARNING:PhysDesignRules:372 - Gated clock. Clock net
362	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or
363	0000 is sourced by a combinatorial pin. This is not good design practice. Use
364	the CE pin to control the loading of data into the flip-flop.
365	WARNING:PhysDesignRules:372 - Gated clock. Clock net
366	connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a
367	combinatorial pin. This is not good design practice. Use the CE pin to
368	control the loading of data into the flip-flop.
369	WARNING:PhysDesignRules:372 - Gated clock. Clock net
370	connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a
371	combinatorial pin. This is not good design practice. Use the CE pin to
372	control the loading of data into the flip-flop.
373	WARNING:PhysDesignRules:372 - Gated clock. Clock net
374	connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced
375	by a combinatorial pin. This is not good design practice. Use the CE pin to
376	control the loading of data into the flip-flop.
377	WARNING:PhysDesignRules:372 - Gated clock. Clock net
378	connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced
379	by a combinatorial pin. This is not good design practice. Use the CE pin to
380	control the loading of data into the flip-flop.
381	WARNING:PhysDesignRules:372 - Gated clock. Clock net
382	connect_core[2].hardmpi/LD_instr/timeout_not0001 is sourced by a
383	combinatorial pin. This is not good design practice. Use the CE pin to
384	control the loading of data into the flip-flop.
385	WARNING:PhysDesignRules:372 - Gated clock. Clock net
386	connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a
387	combinatorial pin. This is not good design practice. Use the CE pin to
388	control the loading of data into the flip-flop.
389	WARNING:PhysDesignRules:372 - Gated clock. Clock net
390	connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a
391	combinatorial pin. This is not good design practice. Use the CE pin to
392	control the loading of data into the flip-flop.
393	WARNING:PhysDesignRules:372 - Gated clock. Clock net
394	connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a
395	combinatorial pin. This is not good design practice. Use the CE pin to
396	control the loading of data into the flip-flop.
397	WARNING:PhysDesignRules:372 - Gated clock. Clock net
398	connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a
399	combinatorial pin. This is not good design practice. Use the CE pin to
400	control the loading of data into the flip-flop.
401	WARNING:PhysDesignRules:372 - Gated clock. Clock net
402	connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a
403	combinatorial pin. This is not good design practice. Use the CE pin to
404	control the loading of data into the flip-flop.
405	WARNING:PhysDesignRules:372 - Gated clock. Clock net
406	connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a
407	combinatorial pin. This is not good design practice. Use the CE pin to
408	control the loading of data into the flip-flop.
409
410	Section 3 - Informational
411	-------------------------
412	INFO:Security:54 - 'xc3s1200e' is a WebPack part.
413	INFO:LIT:243 - Logical network MPI_Node_in<2>_clk has no load.
414	INFO:LIT:395 - The above info message is repeated 95 more times for the
415	following (max. 5 shown):
416	MPI_Node_in<2>_packet_ack,
417	MPI_Node_in<1>_packet_ack,
418	MPI_Node_in<2>_reset,
419	connect_core[2].hardmpi/MyRank<0>,
420	connect_core[2].hardmpi/MyRank<1>
421	To see the details of these info messages, please use the -detail switch.
422	INFO:MapLib:562 - No environment variables are currently set.
423	INFO:LIT:244 - All of the single ended outputs in this design are using slew
424	rate limited output drivers. The delay on speed critical single ended outputs
425	can be dramatically reduced by designating them as fast outputs.
426
427	Section 4 - Removed Logic Summary
428	---------------------------------
429	41 block(s) optimized away
430
431	Section 5 - Removed Logic
432	-------------------------
433
434	Optimized Block(s):
435	TYPE BLOCK
436	GND
437	Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
438	FO/XST_GND
439	VCC
440	Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
441	FO/XST_VCC
442	GND
443	Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
444	FO/fifo_RAM_256/XST_GND
445	VCC
446	Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
447	FO/fifo_RAM_256/XST_VCC
448	GND
449	Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
450	FO/XST_GND
451	VCC
452	Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
453	FO/XST_VCC
454	GND
455	Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
456	FO/fifo_RAM_256/XST_GND
457	VCC
458	Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI
459	FO/fifo_RAM_256/XST_VCC
460	GND
461	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_GND
462	VCC
463	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_VCC
464	GND
465	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM
466	_256/XST_GND
467	VCC
468	Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM
469	_256/XST_VCC
470	GND Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/XST_GND
471	VCC Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/XST_VCC
472	GND
473	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_GND
474	VCC
475	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_VCC
476	GND
477	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM
478	_256/XST_GND
479	VCC
480	Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM
481	_256/XST_VCC
482	VCC Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/XST_VCC
483	GND connect_core[1].hardmpi/Instruction_Fifo2/XST_GND
484	GND connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND
485	GND connect_core[1].hardmpi/LD_instr/XST_GND
486	VCC connect_core[1].hardmpi/LD_instr/XST_VCC
487	GND connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/XST_GND
488	GND connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_GND
489	VCC connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_VCC
490	GND connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_GND
491	GND connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_GND
492	VCC connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_VCC
493	GND connect_core[1].hardmpi/XST_GND
494	GND connect_core[2].hardmpi/Instruction_Fifo2/XST_GND
495	GND connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND
496	GND connect_core[2].hardmpi/LD_instr/XST_GND
497	VCC connect_core[2].hardmpi/LD_instr/XST_VCC
498	GND connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/XST_GND
499	GND connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_GND
500	VCC connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_VCC
501	GND connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_GND
502	GND connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_GND
503	VCC connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_VCC
504	GND connect_core[2].hardmpi/XST_GND
505
506	To enable printing of redundant blocks removed and signals merged, set the
507	detailed map report option and rerun map.
508
509	Section 6 - IOB Properties
510	--------------------------
511
512	+---------------------------------------------------------------------------------------------------------------------------------------------------------+
513	\| IOB Name \| Type \| Direction \| IO Standard \| Diff \| Drive \| Slew \| Reg (s) \| Resistor \| IOB \|
514	\| \| \| \| \| Term \| Strength \| Rate \| \| \| Delay \|
515	+---------------------------------------------------------------------------------------------------------------------------------------------------------+
516	\| MPI_Node_Out<1>_PushOut<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
517	\| MPI_Node_Out<1>_PushOut<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
518	\| MPI_Node_Out<1>_PushOut<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
519	\| MPI_Node_Out<1>_PushOut<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
520	\| MPI_Node_Out<1>_PushOut<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
521	\| MPI_Node_Out<1>_PushOut<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
522	\| MPI_Node_Out<1>_PushOut<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
523	\| MPI_Node_Out<1>_PushOut<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
524	\| MPI_Node_Out<1>_barrier_completed \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
525	\| MPI_Node_Out<1>_hold_req \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
526	\| MPI_Node_Out<1>_instruction_fifo_f \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
527	\| ull \| \| \| \| \| \| \| \| \| \|
528	\| MPI_Node_Out<1>_packet_received \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
529	\| MPI_Node_Out<1>_ram_address_rd<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
530	\| MPI_Node_Out<1>_ram_address_rd<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
531	\| MPI_Node_Out<1>_ram_address_rd<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
532	\| MPI_Node_Out<1>_ram_address_rd<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
533	\| MPI_Node_Out<1>_ram_address_rd<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
534	\| MPI_Node_Out<1>_ram_address_rd<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
535	\| MPI_Node_Out<1>_ram_address_rd<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
536	\| MPI_Node_Out<1>_ram_address_rd<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
537	\| MPI_Node_Out<1>_ram_address_rd<8> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
538	\| MPI_Node_Out<1>_ram_address_rd<9> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
539	\| MPI_Node_Out<1>_ram_address_rd<10> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
540	\| MPI_Node_Out<1>_ram_address_rd<11> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
541	\| MPI_Node_Out<1>_ram_address_rd<12> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
542	\| MPI_Node_Out<1>_ram_address_rd<13> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
543	\| MPI_Node_Out<1>_ram_address_rd<14> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
544	\| MPI_Node_Out<1>_ram_address_rd<15> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
545	\| MPI_Node_Out<1>_ram_address_wr<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
546	\| MPI_Node_Out<1>_ram_address_wr<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
547	\| MPI_Node_Out<1>_ram_address_wr<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
548	\| MPI_Node_Out<1>_ram_address_wr<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
549	\| MPI_Node_Out<1>_ram_address_wr<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
550	\| MPI_Node_Out<1>_ram_address_wr<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
551	\| MPI_Node_Out<1>_ram_address_wr<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
552	\| MPI_Node_Out<1>_ram_address_wr<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
553	\| MPI_Node_Out<1>_ram_address_wr<8> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
554	\| MPI_Node_Out<1>_ram_address_wr<9> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
555	\| MPI_Node_Out<1>_ram_address_wr<10> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
556	\| MPI_Node_Out<1>_ram_address_wr<11> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
557	\| MPI_Node_Out<1>_ram_address_wr<12> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
558	\| MPI_Node_Out<1>_ram_address_wr<13> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
559	\| MPI_Node_Out<1>_ram_address_wr<14> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
560	\| MPI_Node_Out<1>_ram_address_wr<15> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
561	\| MPI_Node_Out<1>_ram_data_in<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
562	\| MPI_Node_Out<1>_ram_data_in<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
563	\| MPI_Node_Out<1>_ram_data_in<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
564	\| MPI_Node_Out<1>_ram_data_in<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
565	\| MPI_Node_Out<1>_ram_data_in<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
566	\| MPI_Node_Out<1>_ram_data_in<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
567	\| MPI_Node_Out<1>_ram_data_in<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
568	\| MPI_Node_Out<1>_ram_data_in<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
569	\| MPI_Node_Out<1>_ram_en \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
570	\| MPI_Node_Out<1>_ram_we \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
571	\| MPI_Node_Out<2>_PushOut<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
572	\| MPI_Node_Out<2>_PushOut<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
573	\| MPI_Node_Out<2>_PushOut<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
574	\| MPI_Node_Out<2>_PushOut<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
575	\| MPI_Node_Out<2>_PushOut<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
576	\| MPI_Node_Out<2>_PushOut<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
577	\| MPI_Node_Out<2>_PushOut<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
578	\| MPI_Node_Out<2>_PushOut<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
579	\| MPI_Node_Out<2>_barrier_completed \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
580	\| MPI_Node_Out<2>_hold_req \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
581	\| MPI_Node_Out<2>_instruction_fifo_f \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
582	\| ull \| \| \| \| \| \| \| \| \| \|
583	\| MPI_Node_Out<2>_packet_received \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
584	\| MPI_Node_Out<2>_ram_address_rd<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
585	\| MPI_Node_Out<2>_ram_address_rd<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
586	\| MPI_Node_Out<2>_ram_address_rd<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
587	\| MPI_Node_Out<2>_ram_address_rd<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
588	\| MPI_Node_Out<2>_ram_address_rd<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
589	\| MPI_Node_Out<2>_ram_address_rd<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
590	\| MPI_Node_Out<2>_ram_address_rd<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
591	\| MPI_Node_Out<2>_ram_address_rd<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
592	\| MPI_Node_Out<2>_ram_address_rd<8> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
593	\| MPI_Node_Out<2>_ram_address_rd<9> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
594	\| MPI_Node_Out<2>_ram_address_rd<10> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
595	\| MPI_Node_Out<2>_ram_address_rd<11> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
596	\| MPI_Node_Out<2>_ram_address_rd<12> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
597	\| MPI_Node_Out<2>_ram_address_rd<13> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
598	\| MPI_Node_Out<2>_ram_address_rd<14> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
599	\| MPI_Node_Out<2>_ram_address_rd<15> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
600	\| MPI_Node_Out<2>_ram_address_wr<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
601	\| MPI_Node_Out<2>_ram_address_wr<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
602	\| MPI_Node_Out<2>_ram_address_wr<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
603	\| MPI_Node_Out<2>_ram_address_wr<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
604	\| MPI_Node_Out<2>_ram_address_wr<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
605	\| MPI_Node_Out<2>_ram_address_wr<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
606	\| MPI_Node_Out<2>_ram_address_wr<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
607	\| MPI_Node_Out<2>_ram_address_wr<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
608	\| MPI_Node_Out<2>_ram_address_wr<8> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
609	\| MPI_Node_Out<2>_ram_address_wr<9> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
610	\| MPI_Node_Out<2>_ram_address_wr<10> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
611	\| MPI_Node_Out<2>_ram_address_wr<11> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
612	\| MPI_Node_Out<2>_ram_address_wr<12> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
613	\| MPI_Node_Out<2>_ram_address_wr<13> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
614	\| MPI_Node_Out<2>_ram_address_wr<14> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
615	\| MPI_Node_Out<2>_ram_address_wr<15> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
616	\| MPI_Node_Out<2>_ram_data_in<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
617	\| MPI_Node_Out<2>_ram_data_in<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
618	\| MPI_Node_Out<2>_ram_data_in<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
619	\| MPI_Node_Out<2>_ram_data_in<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
620	\| MPI_Node_Out<2>_ram_data_in<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
621	\| MPI_Node_Out<2>_ram_data_in<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
622	\| MPI_Node_Out<2>_ram_data_in<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
623	\| MPI_Node_Out<2>_ram_data_in<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
624	\| MPI_Node_Out<2>_ram_en \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
625	\| MPI_Node_Out<2>_ram_we \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
626	\| MPI_Node_in<1>_clk \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
627	\| MPI_Node_in<1>_hold_ack \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
628	\| MPI_Node_in<1>_instruction<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
629	\| MPI_Node_in<1>_instruction<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
630	\| MPI_Node_in<1>_instruction<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
631	\| MPI_Node_in<1>_instruction<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
632	\| MPI_Node_in<1>_instruction<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
633	\| MPI_Node_in<1>_instruction<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
634	\| MPI_Node_in<1>_instruction<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
635	\| MPI_Node_in<1>_instruction<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
636	\| MPI_Node_in<1>_instruction_en \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
637	\| MPI_Node_in<1>_ram_data_out<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
638	\| MPI_Node_in<1>_ram_data_out<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
639	\| MPI_Node_in<1>_ram_data_out<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
640	\| MPI_Node_in<1>_ram_data_out<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
641	\| MPI_Node_in<1>_ram_data_out<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
642	\| MPI_Node_in<1>_ram_data_out<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
643	\| MPI_Node_in<1>_ram_data_out<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
644	\| MPI_Node_in<1>_ram_data_out<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
645	\| MPI_Node_in<1>_reset \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
646	\| MPI_Node_in<2>_hold_ack \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
647	\| MPI_Node_in<2>_instruction<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
648	\| MPI_Node_in<2>_instruction<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
649	\| MPI_Node_in<2>_instruction<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
650	\| MPI_Node_in<2>_instruction<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
651	\| MPI_Node_in<2>_instruction<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
652	\| MPI_Node_in<2>_instruction<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
653	\| MPI_Node_in<2>_instruction<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
654	\| MPI_Node_in<2>_instruction<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
655	\| MPI_Node_in<2>_instruction_en \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
656	\| MPI_Node_in<2>_ram_data_out<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
657	\| MPI_Node_in<2>_ram_data_out<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
658	\| MPI_Node_in<2>_ram_data_out<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
659	\| MPI_Node_in<2>_ram_data_out<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
660	\| MPI_Node_in<2>_ram_data_out<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
661	\| MPI_Node_in<2>_ram_data_out<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
662	\| MPI_Node_in<2>_ram_data_out<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
663	\| MPI_Node_in<2>_ram_data_out<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
664	+---------------------------------------------------------------------------------------------------------------------------------------------------------+
665
666	Section 7 - RPMs
667	----------------
668
669	Section 8 - Guide Report
670	------------------------
671	Guide not run on this design.
672
673	Section 9 - Area Group and Partition Summary
674	--------------------------------------------
675
676	Partition Implementation Status
677	-------------------------------
678
679	No Partitions were found in this design.
680
681	-------------------------------
682
683	Area Group Information
684	----------------------
685
686	No area groups were found in this design.
687
688	----------------------
689
690	Section 10 - Timing Report
691	--------------------------
692	This design was not run using timing mode.
693
694	Section 11 - Configuration String Details
695	-----------------------------------------
696	Use the "-detail" map option to print out Configuration Strings
697
698	Section 12 - Control Set Information
699	------------------------------------
700	No control set information for this architecture.
701
702	Section 13 - Utilization by Hierarchy
703	-------------------------------------
704	Use the "-detail" map option to print out the Utilization by Hierarchy section.

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