1 | Release 12.3 par M.70d (nt64) |
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2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
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3 | |
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4 | GAMOM-PC:: Tue Aug 14 16:11:11 2012 |
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5 | |
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6 | par -w -intstyle ise -ol high -mt off MultiMPITest_map.ncd MultiMPITest.ncd |
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7 | MultiMPITest.pcf |
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8 | |
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9 | |
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10 | Constraints file: MultiMPITest.pcf. |
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11 | Loading device for application Rf_Device from file '6slx100.nph' in environment d:\Xilinx\12.3\ISE_DS\ISE\. |
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12 | "MultiMPITest" is an NCD, version 3.2, device xc6slx100, package fgg484, speed -3 |
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13 | vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv |
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14 | INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. |
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15 | WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue |
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16 | to function, but you no longer qualify for Xilinx software updates or new releases. |
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17 | |
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18 | ---------------------------------------------------------------------- |
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19 | |
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20 | Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) |
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21 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) |
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22 | |
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23 | INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par |
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24 | -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all |
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25 | internal clocks in this design. Because there are not defined timing requirements, a timing score will not be |
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26 | reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. |
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27 | Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
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28 | |
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29 | Device speed data version: "PRODUCTION 1.12c 2010-09-15". |
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30 | |
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31 | |
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32 | |
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33 | Device Utilization Summary: |
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34 | |
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35 | Slice Logic Utilization: |
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36 | Number of Slice Registers: 1,515 out of 126,576 1% |
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37 | Number used as Flip Flops: 1,137 |
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38 | Number used as Latches: 378 |
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39 | Number used as Latch-thrus: 0 |
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40 | Number used as AND/OR logics: 0 |
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41 | Number of Slice LUTs: 3,025 out of 63,288 4% |
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42 | Number used as logic: 2,942 out of 63,288 4% |
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43 | Number using O6 output only: 2,058 |
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44 | Number using O5 output only: 294 |
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45 | Number using O5 and O6: 590 |
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46 | Number used as ROM: 0 |
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47 | Number used as Memory: 48 out of 15,616 1% |
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48 | Number used as Dual Port RAM: 48 |
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49 | Number using O6 output only: 48 |
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50 | Number using O5 output only: 0 |
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51 | Number using O5 and O6: 0 |
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52 | Number used as Single Port RAM: 0 |
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53 | Number used as Shift Register: 0 |
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54 | Number used exclusively as route-thrus: 35 |
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55 | Number with same-slice register load: 7 |
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56 | Number with same-slice carry load: 28 |
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57 | Number with other load: 0 |
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58 | |
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59 | Slice Logic Distribution: |
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60 | Number of occupied Slices: 1,099 out of 15,822 6% |
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61 | Number of LUT Flip Flop pairs used: 3,230 |
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62 | Number with an unused Flip Flop: 1,806 out of 3,230 55% |
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63 | Number with an unused LUT: 205 out of 3,230 6% |
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64 | Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% |
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65 | Number of slice register sites lost |
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66 | to control set restrictions: 0 out of 126,576 0% |
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67 | |
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68 | A LUT Flip Flop pair for this architecture represents one LUT paired with |
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69 | one Flip Flop within a slice. A control set is a unique combination of |
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70 | clock, reset, set, and enable signals for a registered element. |
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71 | The Slice Logic Distribution report is not meaningful if the design is |
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72 | over-mapped for a non-slice resource or if Placement fails. |
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73 | |
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74 | IO Utilization: |
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75 | Number of bonded IOBs: 10 out of 326 3% |
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76 | |
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77 | Specific Feature Utilization: |
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78 | Number of RAMB16BWERs: 64 out of 268 23% |
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79 | Number of RAMB8BWERs: 4 out of 536 1% |
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80 | Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
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81 | Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
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82 | Number of BUFG/BUFGMUXs: 3 out of 16 18% |
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83 | Number used as BUFGs: 3 |
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84 | Number used as BUFGMUX: 0 |
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85 | Number of DCM/DCM_CLKGENs: 0 out of 12 0% |
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86 | Number of ILOGIC2/ISERDES2s: 0 out of 506 0% |
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87 | Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% |
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88 | Number of OLOGIC2/OSERDES2s: 0 out of 506 0% |
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89 | Number of BSCANs: 0 out of 4 0% |
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90 | Number of BUFHs: 0 out of 384 0% |
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91 | Number of BUFPLLs: 0 out of 8 0% |
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92 | Number of BUFPLL_MCBs: 0 out of 4 0% |
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93 | Number of DSP48A1s: 0 out of 180 0% |
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94 | Number of ICAPs: 0 out of 1 0% |
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95 | Number of MCBs: 0 out of 4 0% |
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96 | Number of PCILOGICSEs: 0 out of 2 0% |
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97 | Number of PLL_ADVs: 0 out of 6 0% |
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98 | Number of PMVs: 0 out of 1 0% |
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99 | Number of STARTUPs: 0 out of 1 0% |
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100 | Number of SUSPEND_SYNCs: 0 out of 1 0% |
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101 | |
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102 | |
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103 | Overall effort level (-ol): High |
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104 | Router effort level (-rl): High |
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105 | |
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106 | Starting initial Timing Analysis. REAL time: 9 secs |
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107 | Finished initial Timing Analysis. REAL time: 9 secs |
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108 | |
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109 | WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt |
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110 | to route this signal. |
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111 | WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt |
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112 | to route this signal. |
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113 | WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt |
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114 | to route this signal. |
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115 | WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt |
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116 | to route this signal. |
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117 | WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt |
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118 | to route this signal. |
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119 | WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt |
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120 | to route this signal. |
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121 | WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt |
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122 | to route this signal. |
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123 | WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt |
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124 | to route this signal. |
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125 | Starting Router |
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126 | |
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127 | |
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128 | Phase 1 : 19877 unrouted; REAL time: 11 secs |
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129 | |
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130 | Phase 2 : 17702 unrouted; REAL time: 14 secs |
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131 | |
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132 | Phase 3 : 7443 unrouted; REAL time: 23 secs |
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133 | |
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134 | Phase 4 : 7448 unrouted; (Par is working to improve performance) REAL time: 27 secs |
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135 | |
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136 | Updating file: MultiMPITest.ncd with current fully routed design. |
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137 | |
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138 | Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs |
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139 | |
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140 | Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs |
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141 | |
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142 | Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs |
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143 | |
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144 | Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs |
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145 | |
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146 | Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 38 secs |
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147 | |
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148 | Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 39 secs |
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149 | Total REAL time to Router completion: 39 secs |
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150 | Total CPU time to Router completion: 40 secs |
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151 | |
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152 | Partition Implementation Status |
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153 | ------------------------------- |
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154 | |
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155 | No Partitions were found in this design. |
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156 | |
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157 | ------------------------------- |
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158 | |
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159 | Generating "PAR" statistics. |
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160 | INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. |
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161 | Timing Score: 293 (Setup: 293, Hold: 0) |
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162 | |
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163 | Asterisk (*) preceding a constraint indicates it was not met. |
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164 | This may be due to a setup or hold violation. |
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165 | |
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166 | ---------------------------------------------------------------------------------------------------------- |
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167 | Constraint | Check | Worst Case | Best Case | Timing | Timing |
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168 | | | Slack | Achievable | Errors | Score |
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169 | ---------------------------------------------------------------------------------------------------------- |
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170 | Autotimespec constraint for clock net clk | SETUP | N/A| 9.399ns| N/A| 0 |
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171 | m_BUFGP | HOLD | 0.278ns| | 0| 0 |
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172 | ---------------------------------------------------------------------------------------------------------- |
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173 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.579ns| N/A| 0 |
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174 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.905ns| | 0| 0 |
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175 | nst[2]_PWR_99_o_Mux_295_o | | | | | |
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176 | ---------------------------------------------------------------------------------------------------------- |
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177 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.211ns| N/A| 0 |
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178 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.898ns| | 0| 0 |
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179 | nst[2]_PWR_99_o_Mux_295_o | | | | | |
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180 | ---------------------------------------------------------------------------------------------------------- |
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181 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.058ns| N/A| 0 |
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182 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.867ns| | 0| 0 |
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183 | nst[2]_PWR_72_o_Mux_259_o | | | | | |
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184 | ---------------------------------------------------------------------------------------------------------- |
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185 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.073ns| N/A| 0 |
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186 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.922ns| | 0| 0 |
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187 | nst[2]_PWR_72_o_Mux_259_o | | | | | |
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188 | ---------------------------------------------------------------------------------------------------------- |
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189 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.673ns| N/A| 0 |
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190 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.867ns| | 0| 0 |
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191 | nst[2]_PWR_93_o_Mux_287_o | | | | | |
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192 | ---------------------------------------------------------------------------------------------------------- |
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193 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.262ns| N/A| 0 |
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194 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 1.054ns| | 0| 0 |
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195 | nst[2]_PWR_93_o_Mux_287_o | | | | | |
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196 | ---------------------------------------------------------------------------------------------------------- |
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197 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.275ns| N/A| 0 |
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198 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.016ns| | 0| 0 |
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199 | nst[2]_PWR_105_o_Mux_303_o | | | | | |
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200 | ---------------------------------------------------------------------------------------------------------- |
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201 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.214ns| N/A| 43 |
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202 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 1.038ns| | 0| 0 |
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203 | nst[2]_PWR_105_o_Mux_303_o | | | | | |
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204 | ---------------------------------------------------------------------------------------------------------- |
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205 | Autotimespec constraint for clock net uut | SETUP | N/A| 1.947ns| N/A| 0 |
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206 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.729ns| | 0| 0 |
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207 | nst[2]_PWR_66_o_Mux_251_o | | | | | |
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208 | ---------------------------------------------------------------------------------------------------------- |
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209 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.486ns| N/A| 0 |
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210 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.935ns| | 0| 0 |
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211 | nst[2]_PWR_66_o_Mux_251_o | | | | | |
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212 | ---------------------------------------------------------------------------------------------------------- |
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213 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.797ns| N/A| 0 |
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214 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.148ns| | 0| 0 |
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215 | nst[2]_PWR_90_o_Mux_283_o | | | | | |
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216 | ---------------------------------------------------------------------------------------------------------- |
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217 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.023ns| N/A| 0 |
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218 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.942ns| | 0| 0 |
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219 | nst[2]_PWR_90_o_Mux_283_o | | | | | |
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220 | ---------------------------------------------------------------------------------------------------------- |
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221 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.265ns| N/A| 0 |
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222 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.052ns| | 0| 0 |
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223 | nst[2]_PWR_102_o_Mux_299_o | | | | | |
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224 | ---------------------------------------------------------------------------------------------------------- |
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225 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.074ns| N/A| 0 |
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226 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.880ns| | 0| 0 |
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227 | nst[2]_PWR_102_o_Mux_299_o | | | | | |
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228 | ---------------------------------------------------------------------------------------------------------- |
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229 | Autotimespec constraint for clock net uut | SETUP | N/A| 1.444ns| N/A| 0 |
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230 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.642ns| | 0| 0 |
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231 | nst[2]_PWR_69_o_Mux_255_o | | | | | |
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232 | ---------------------------------------------------------------------------------------------------------- |
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233 | Autotimespec constraint for clock net uut | SETUP | N/A| 1.455ns| N/A| 0 |
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234 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.476ns| | 0| 0 |
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235 | nst[2]_PWR_69_o_Mux_255_o | | | | | |
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236 | ---------------------------------------------------------------------------------------------------------- |
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237 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.460ns| N/A| 0 |
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238 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.135ns| | 0| 0 |
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239 | nst[2]_PWR_84_o_Mux_275_o | | | | | |
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240 | ---------------------------------------------------------------------------------------------------------- |
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241 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.483ns| N/A| 0 |
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242 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 1.163ns| | 0| 0 |
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243 | nst[2]_PWR_84_o_Mux_275_o | | | | | |
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244 | ---------------------------------------------------------------------------------------------------------- |
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245 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.207ns| N/A| 0 |
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246 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.957ns| | 0| 0 |
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247 | nst[2]_PWR_81_o_Mux_271_o | | | | | |
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248 | ---------------------------------------------------------------------------------------------------------- |
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249 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.721ns| N/A| 0 |
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250 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.990ns| | 0| 0 |
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251 | nst[2]_PWR_81_o_Mux_271_o | | | | | |
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252 | ---------------------------------------------------------------------------------------------------------- |
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253 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.040ns| N/A| 0 |
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254 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.837ns| | 0| 0 |
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255 | nst[2]_PWR_60_o_Mux_243_o | | | | | |
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256 | ---------------------------------------------------------------------------------------------------------- |
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257 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.187ns| N/A| 168 |
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258 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.864ns| | 0| 0 |
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259 | nst[2]_PWR_60_o_Mux_243_o | | | | | |
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260 | ---------------------------------------------------------------------------------------------------------- |
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261 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.524ns| N/A| 0 |
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262 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.072ns| | 0| 0 |
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263 | nst[2]_PWR_87_o_Mux_279_o | | | | | |
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264 | ---------------------------------------------------------------------------------------------------------- |
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265 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.433ns| N/A| 0 |
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266 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.593ns| | 0| 0 |
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267 | nst[2]_PWR_87_o_Mux_279_o | | | | | |
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268 | ---------------------------------------------------------------------------------------------------------- |
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269 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.022ns| N/A| 0 |
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270 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.741ns| | 0| 0 |
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271 | nst[2]_PWR_78_o_Mux_267_o | | | | | |
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272 | ---------------------------------------------------------------------------------------------------------- |
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273 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.893ns| N/A| 7 |
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274 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.009ns| | 0| 0 |
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275 | nst[2]_PWR_96_o_Mux_291_o | | | | | |
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276 | ---------------------------------------------------------------------------------------------------------- |
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277 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.247ns| N/A| 0 |
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278 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.704ns| | 0| 0 |
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279 | nst[2]_PWR_96_o_Mux_291_o | | | | | |
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280 | ---------------------------------------------------------------------------------------------------------- |
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281 | Autotimespec constraint for clock net uut | SETUP | N/A| 1.914ns| N/A| 0 |
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282 | /connect_core[1].hardmpi/MPI_CORE_EX4_FSM | HOLD | 0.530ns| | 0| 0 |
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283 | /stInit2_FSM_FFd1_BUFG | | | | | |
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284 | ---------------------------------------------------------------------------------------------------------- |
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285 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.130ns| N/A| 0 |
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286 | /connect_core[2].hardmpi/MPI_CORE_EX4_FSM | HOLD | 0.545ns| | 0| 0 |
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287 | /stInit2_FSM_FFd1_BUFG | | | | | |
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288 | ---------------------------------------------------------------------------------------------------------- |
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289 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.453ns| N/A| 0 |
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290 | /connect_core[1].hardmpi/MPI_CORE_EX4_FSM | HOLD | 0.979ns| | 0| 0 |
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291 | /stInit2[3]_PWR_316_o_Mux_111_o | | | | | |
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292 | ---------------------------------------------------------------------------------------------------------- |
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293 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.866ns| N/A| 0 |
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294 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.402ns| | 0| 0 |
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295 | nst[2]_PWR_140_o_Mux_371_o | | | | | |
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296 | ---------------------------------------------------------------------------------------------------------- |
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297 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.958ns| N/A| 0 |
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298 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.476ns| | 0| 0 |
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299 | nst[2]_PWR_140_o_Mux_371_o | | | | | |
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300 | ---------------------------------------------------------------------------------------------------------- |
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301 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.531ns| N/A| 0 |
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302 | /connect_core[2].hardmpi/MPI_CORE_EX4_FSM | HOLD | 1.012ns| | 0| 0 |
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303 | /stInit2[3]_PWR_316_o_Mux_111_o | | | | | |
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304 | ---------------------------------------------------------------------------------------------------------- |
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305 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.200ns| N/A| 0 |
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306 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.964ns| | 0| 0 |
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307 | nst[2]_PWR_75_o_Mux_263_o | | | | | |
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308 | ---------------------------------------------------------------------------------------------------------- |
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309 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.188ns| N/A| 0 |
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310 | /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.963ns| | 0| 0 |
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311 | nst[2]_PWR_63_o_Mux_247_o | | | | | |
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312 | ---------------------------------------------------------------------------------------------------------- |
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313 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.692ns| N/A| 0 |
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314 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.199ns| | 0| 0 |
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315 | nst[2]_PWR_63_o_Mux_247_o | | | | | |
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316 | ---------------------------------------------------------------------------------------------------------- |
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317 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.413ns| N/A| 0 |
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318 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.076ns| | 0| 0 |
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319 | nst[2]_PWR_75_o_Mux_263_o | | | | | |
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320 | ---------------------------------------------------------------------------------------------------------- |
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321 | Autotimespec constraint for clock net uut | SETUP | N/A| 2.116ns| N/A| 75 |
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322 | /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.940ns| | 0| 0 |
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323 | nst[2]_PWR_78_o_Mux_267_o | | | | | |
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324 | ---------------------------------------------------------------------------------------------------------- |
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325 | |
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326 | |
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327 | 4 constraints not met. |
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328 | INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the |
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329 | constraint is not analyzed due to the following: No paths covered by this |
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330 | constraint; Other constraints intersect with this constraint; or This |
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331 | constraint was disabled by a Path Tracing Control. Please run the Timespec |
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332 | Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. |
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333 | |
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334 | |
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335 | Generating Pad Report. |
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336 | |
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337 | All signals are completely routed. |
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338 | |
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339 | WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. |
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340 | |
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341 | Total REAL time to PAR completion: 41 secs |
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342 | Total CPU time to PAR completion: 41 secs |
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343 | |
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344 | Peak Memory Usage: 570 MB |
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345 | |
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346 | Placer: Placement generated during map. |
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347 | Routing: Completed - No errors found. |
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348 | |
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349 | Number of error messages: 0 |
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350 | Number of warning messages: 10 |
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351 | Number of info messages: 2 |
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352 | |
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353 | Writing design to file MultiMPITest.ncd |
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354 | |
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355 | |
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356 | |
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357 | PAR done! |
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