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MultiMPITest.par @ 15

Last change on this file since 15 was 15, checked in by rolagamo, 12 years ago

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1	Release 12.3 par M.70d (nt64)
2	Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
3
4	GAMOM-PC:: Tue Aug 14 16:11:11 2012
5
6	par -w -intstyle ise -ol high -mt off MultiMPITest_map.ncd MultiMPITest.ncd
7	MultiMPITest.pcf
8
9
10	Constraints file: MultiMPITest.pcf.
11	Loading device for application Rf_Device from file '6slx100.nph' in environment d:\Xilinx\12.3\ISE_DS\ISE\.
12	"MultiMPITest" is an NCD, version 3.2, device xc6slx100, package fgg484, speed -3
13	vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
14	INFO:Security:56 - Part 'xc6slx100' is not a WebPack part.
15	WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
16	to function, but you no longer qualify for Xilinx software updates or new releases.
17
18	----------------------------------------------------------------------
19
20	Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
21	Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
22
23	INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
24	-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
25	internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
26	reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
27	Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
28
29	Device speed data version: "PRODUCTION 1.12c 2010-09-15".
30
31
32
33	Device Utilization Summary:
34
35	Slice Logic Utilization:
36	Number of Slice Registers: 1,515 out of 126,576 1%
37	Number used as Flip Flops: 1,137
38	Number used as Latches: 378
39	Number used as Latch-thrus: 0
40	Number used as AND/OR logics: 0
41	Number of Slice LUTs: 3,025 out of 63,288 4%
42	Number used as logic: 2,942 out of 63,288 4%
43	Number using O6 output only: 2,058
44	Number using O5 output only: 294
45	Number using O5 and O6: 590
46	Number used as ROM: 0
47	Number used as Memory: 48 out of 15,616 1%
48	Number used as Dual Port RAM: 48
49	Number using O6 output only: 48
50	Number using O5 output only: 0
51	Number using O5 and O6: 0
52	Number used as Single Port RAM: 0
53	Number used as Shift Register: 0
54	Number used exclusively as route-thrus: 35
55	Number with same-slice register load: 7
56	Number with same-slice carry load: 28
57	Number with other load: 0
58
59	Slice Logic Distribution:
60	Number of occupied Slices: 1,099 out of 15,822 6%
61	Number of LUT Flip Flop pairs used: 3,230
62	Number with an unused Flip Flop: 1,806 out of 3,230 55%
63	Number with an unused LUT: 205 out of 3,230 6%
64	Number of fully used LUT-FF pairs: 1,219 out of 3,230 37%
65	Number of slice register sites lost
66	to control set restrictions: 0 out of 126,576 0%
67
68	A LUT Flip Flop pair for this architecture represents one LUT paired with
69	one Flip Flop within a slice. A control set is a unique combination of
70	clock, reset, set, and enable signals for a registered element.
71	The Slice Logic Distribution report is not meaningful if the design is
72	over-mapped for a non-slice resource or if Placement fails.
73
74	IO Utilization:
75	Number of bonded IOBs: 10 out of 326 3%
76
77	Specific Feature Utilization:
78	Number of RAMB16BWERs: 64 out of 268 23%
79	Number of RAMB8BWERs: 4 out of 536 1%
80	Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
81	Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
82	Number of BUFG/BUFGMUXs: 3 out of 16 18%
83	Number used as BUFGs: 3
84	Number used as BUFGMUX: 0
85	Number of DCM/DCM_CLKGENs: 0 out of 12 0%
86	Number of ILOGIC2/ISERDES2s: 0 out of 506 0%
87	Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0%
88	Number of OLOGIC2/OSERDES2s: 0 out of 506 0%
89	Number of BSCANs: 0 out of 4 0%
90	Number of BUFHs: 0 out of 384 0%
91	Number of BUFPLLs: 0 out of 8 0%
92	Number of BUFPLL_MCBs: 0 out of 4 0%
93	Number of DSP48A1s: 0 out of 180 0%
94	Number of ICAPs: 0 out of 1 0%
95	Number of MCBs: 0 out of 4 0%
96	Number of PCILOGICSEs: 0 out of 2 0%
97	Number of PLL_ADVs: 0 out of 6 0%
98	Number of PMVs: 0 out of 1 0%
99	Number of STARTUPs: 0 out of 1 0%
100	Number of SUSPEND_SYNCs: 0 out of 1 0%
101
102
103	Overall effort level (-ol): High
104	Router effort level (-rl): High
105
106	Starting initial Timing Analysis. REAL time: 9 secs
107	Finished initial Timing Analysis. REAL time: 9 secs
108
109	WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt
110	to route this signal.
111	WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt
112	to route this signal.
113	WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt
114	to route this signal.
115	WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt
116	to route this signal.
117	WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt
118	to route this signal.
119	WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt
120	to route this signal.
121	WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt
122	to route this signal.
123	WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt
124	to route this signal.
125	Starting Router
126
127
128	Phase 1 : 19877 unrouted; REAL time: 11 secs
129
130	Phase 2 : 17702 unrouted; REAL time: 14 secs
131
132	Phase 3 : 7443 unrouted; REAL time: 23 secs
133
134	Phase 4 : 7448 unrouted; (Par is working to improve performance) REAL time: 27 secs
135
136	Updating file: MultiMPITest.ncd with current fully routed design.
137
138	Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs
139
140	Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs
141
142	Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs
143
144	Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs
145
146	Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 38 secs
147
148	Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 39 secs
149	Total REAL time to Router completion: 39 secs
150	Total CPU time to Router completion: 40 secs
151
152	Partition Implementation Status
153	-------------------------------
154
155	No Partitions were found in this design.
156
157	-------------------------------
158
159	Generating "PAR" statistics.
160	INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
161	Timing Score: 293 (Setup: 293, Hold: 0)
162
163	Asterisk (*) preceding a constraint indicates it was not met.
164	This may be due to a setup or hold violation.
165
166	----------------------------------------------------------------------------------------------------------
167	Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing
168	\| \| Slack \| Achievable \| Errors \| Score
169	----------------------------------------------------------------------------------------------------------
170	Autotimespec constraint for clock net clk \| SETUP \| N/A\| 9.399ns\| N/A\| 0
171	m_BUFGP \| HOLD \| 0.278ns\| \| 0\| 0
172	----------------------------------------------------------------------------------------------------------
173	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.579ns\| N/A\| 0
174	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.905ns\| \| 0\| 0
175	nst[2]_PWR_99_o_Mux_295_o \| \| \| \| \|
176	----------------------------------------------------------------------------------------------------------
177	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.211ns\| N/A\| 0
178	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.898ns\| \| 0\| 0
179	nst[2]_PWR_99_o_Mux_295_o \| \| \| \| \|
180	----------------------------------------------------------------------------------------------------------
181	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.058ns\| N/A\| 0
182	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.867ns\| \| 0\| 0
183	nst[2]_PWR_72_o_Mux_259_o \| \| \| \| \|
184	----------------------------------------------------------------------------------------------------------
185	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.073ns\| N/A\| 0
186	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.922ns\| \| 0\| 0
187	nst[2]_PWR_72_o_Mux_259_o \| \| \| \| \|
188	----------------------------------------------------------------------------------------------------------
189	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.673ns\| N/A\| 0
190	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.867ns\| \| 0\| 0
191	nst[2]_PWR_93_o_Mux_287_o \| \| \| \| \|
192	----------------------------------------------------------------------------------------------------------
193	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.262ns\| N/A\| 0
194	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 1.054ns\| \| 0\| 0
195	nst[2]_PWR_93_o_Mux_287_o \| \| \| \| \|
196	----------------------------------------------------------------------------------------------------------
197	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.275ns\| N/A\| 0
198	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.016ns\| \| 0\| 0
199	nst[2]_PWR_105_o_Mux_303_o \| \| \| \| \|
200	----------------------------------------------------------------------------------------------------------
201	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.214ns\| N/A\| 43
202	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 1.038ns\| \| 0\| 0
203	nst[2]_PWR_105_o_Mux_303_o \| \| \| \| \|
204	----------------------------------------------------------------------------------------------------------
205	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 1.947ns\| N/A\| 0
206	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.729ns\| \| 0\| 0
207	nst[2]_PWR_66_o_Mux_251_o \| \| \| \| \|
208	----------------------------------------------------------------------------------------------------------
209	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.486ns\| N/A\| 0
210	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.935ns\| \| 0\| 0
211	nst[2]_PWR_66_o_Mux_251_o \| \| \| \| \|
212	----------------------------------------------------------------------------------------------------------
213	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.797ns\| N/A\| 0
214	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.148ns\| \| 0\| 0
215	nst[2]_PWR_90_o_Mux_283_o \| \| \| \| \|
216	----------------------------------------------------------------------------------------------------------
217	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.023ns\| N/A\| 0
218	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.942ns\| \| 0\| 0
219	nst[2]_PWR_90_o_Mux_283_o \| \| \| \| \|
220	----------------------------------------------------------------------------------------------------------
221	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.265ns\| N/A\| 0
222	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.052ns\| \| 0\| 0
223	nst[2]_PWR_102_o_Mux_299_o \| \| \| \| \|
224	----------------------------------------------------------------------------------------------------------
225	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.074ns\| N/A\| 0
226	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.880ns\| \| 0\| 0
227	nst[2]_PWR_102_o_Mux_299_o \| \| \| \| \|
228	----------------------------------------------------------------------------------------------------------
229	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 1.444ns\| N/A\| 0
230	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.642ns\| \| 0\| 0
231	nst[2]_PWR_69_o_Mux_255_o \| \| \| \| \|
232	----------------------------------------------------------------------------------------------------------
233	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 1.455ns\| N/A\| 0
234	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.476ns\| \| 0\| 0
235	nst[2]_PWR_69_o_Mux_255_o \| \| \| \| \|
236	----------------------------------------------------------------------------------------------------------
237	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.460ns\| N/A\| 0
238	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.135ns\| \| 0\| 0
239	nst[2]_PWR_84_o_Mux_275_o \| \| \| \| \|
240	----------------------------------------------------------------------------------------------------------
241	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.483ns\| N/A\| 0
242	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 1.163ns\| \| 0\| 0
243	nst[2]_PWR_84_o_Mux_275_o \| \| \| \| \|
244	----------------------------------------------------------------------------------------------------------
245	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.207ns\| N/A\| 0
246	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.957ns\| \| 0\| 0
247	nst[2]_PWR_81_o_Mux_271_o \| \| \| \| \|
248	----------------------------------------------------------------------------------------------------------
249	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.721ns\| N/A\| 0
250	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.990ns\| \| 0\| 0
251	nst[2]_PWR_81_o_Mux_271_o \| \| \| \| \|
252	----------------------------------------------------------------------------------------------------------
253	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.040ns\| N/A\| 0
254	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.837ns\| \| 0\| 0
255	nst[2]_PWR_60_o_Mux_243_o \| \| \| \| \|
256	----------------------------------------------------------------------------------------------------------
257	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.187ns\| N/A\| 168
258	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.864ns\| \| 0\| 0
259	nst[2]_PWR_60_o_Mux_243_o \| \| \| \| \|
260	----------------------------------------------------------------------------------------------------------
261	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.524ns\| N/A\| 0
262	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.072ns\| \| 0\| 0
263	nst[2]_PWR_87_o_Mux_279_o \| \| \| \| \|
264	----------------------------------------------------------------------------------------------------------
265	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.433ns\| N/A\| 0
266	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.593ns\| \| 0\| 0
267	nst[2]_PWR_87_o_Mux_279_o \| \| \| \| \|
268	----------------------------------------------------------------------------------------------------------
269	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.022ns\| N/A\| 0
270	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.741ns\| \| 0\| 0
271	nst[2]_PWR_78_o_Mux_267_o \| \| \| \| \|
272	----------------------------------------------------------------------------------------------------------
273	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.893ns\| N/A\| 7
274	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.009ns\| \| 0\| 0
275	nst[2]_PWR_96_o_Mux_291_o \| \| \| \| \|
276	----------------------------------------------------------------------------------------------------------
277	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.247ns\| N/A\| 0
278	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.704ns\| \| 0\| 0
279	nst[2]_PWR_96_o_Mux_291_o \| \| \| \| \|
280	----------------------------------------------------------------------------------------------------------
281	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 1.914ns\| N/A\| 0
282	/connect_core[1].hardmpi/MPI_CORE_EX4_FSM \| HOLD \| 0.530ns\| \| 0\| 0
283	/stInit2_FSM_FFd1_BUFG \| \| \| \| \|
284	----------------------------------------------------------------------------------------------------------
285	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.130ns\| N/A\| 0
286	/connect_core[2].hardmpi/MPI_CORE_EX4_FSM \| HOLD \| 0.545ns\| \| 0\| 0
287	/stInit2_FSM_FFd1_BUFG \| \| \| \| \|
288	----------------------------------------------------------------------------------------------------------
289	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.453ns\| N/A\| 0
290	/connect_core[1].hardmpi/MPI_CORE_EX4_FSM \| HOLD \| 0.979ns\| \| 0\| 0
291	/stInit2[3]_PWR_316_o_Mux_111_o \| \| \| \| \|
292	----------------------------------------------------------------------------------------------------------
293	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.866ns\| N/A\| 0
294	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.402ns\| \| 0\| 0
295	nst[2]_PWR_140_o_Mux_371_o \| \| \| \| \|
296	----------------------------------------------------------------------------------------------------------
297	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.958ns\| N/A\| 0
298	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.476ns\| \| 0\| 0
299	nst[2]_PWR_140_o_Mux_371_o \| \| \| \| \|
300	----------------------------------------------------------------------------------------------------------
301	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.531ns\| N/A\| 0
302	/connect_core[2].hardmpi/MPI_CORE_EX4_FSM \| HOLD \| 1.012ns\| \| 0\| 0
303	/stInit2[3]_PWR_316_o_Mux_111_o \| \| \| \| \|
304	----------------------------------------------------------------------------------------------------------
305	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.200ns\| N/A\| 0
306	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.964ns\| \| 0\| 0
307	nst[2]_PWR_75_o_Mux_263_o \| \| \| \| \|
308	----------------------------------------------------------------------------------------------------------
309	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.188ns\| N/A\| 0
310	/connect_core[2].hardmpi/LD_instr/etloadi \| HOLD \| 0.963ns\| \| 0\| 0
311	nst[2]_PWR_63_o_Mux_247_o \| \| \| \| \|
312	----------------------------------------------------------------------------------------------------------
313	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.692ns\| N/A\| 0
314	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.199ns\| \| 0\| 0
315	nst[2]_PWR_63_o_Mux_247_o \| \| \| \| \|
316	----------------------------------------------------------------------------------------------------------
317	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.413ns\| N/A\| 0
318	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 1.076ns\| \| 0\| 0
319	nst[2]_PWR_75_o_Mux_263_o \| \| \| \| \|
320	----------------------------------------------------------------------------------------------------------
321	Autotimespec constraint for clock net uut \| SETUP \| N/A\| 2.116ns\| N/A\| 75
322	/connect_core[1].hardmpi/LD_instr/etloadi \| HOLD \| 0.940ns\| \| 0\| 0
323	nst[2]_PWR_78_o_Mux_267_o \| \| \| \| \|
324	----------------------------------------------------------------------------------------------------------
325
326
327	4 constraints not met.
328	INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
329	constraint is not analyzed due to the following: No paths covered by this
330	constraint; Other constraints intersect with this constraint; or This
331	constraint was disabled by a Path Tracing Control. Please run the Timespec
332	Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
333
334
335	Generating Pad Report.
336
337	All signals are completely routed.
338
339	WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
340
341	Total REAL time to PAR completion: 41 secs
342	Total CPU time to PAR completion: 41 secs
343
344	Peak Memory Usage: 570 MB
345
346	Placer: Placement generated during map.
347	Routing: Completed - No errors found.
348
349	Number of error messages: 0
350	Number of warning messages: 10
351	Number of info messages: 2
352
353	Writing design to file MultiMPITest.ncd
354
355
356
357	PAR done!

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