Rev | Line | |
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[15] | 1 | Release 12.3 - par M.70d (nt64) |
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| 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
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| 3 | |
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| 4 | Tue Aug 14 16:11:52 2012 |
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| 5 | |
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| 6 | All signals are completely routed. |
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| 7 | |
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| 8 | WARNING:ParHelpers:361 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC |
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| 9 | warnings. |
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| 10 | |
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| 11 | uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O |
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| 12 | uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O |
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| 13 | uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O |
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| 14 | uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O |
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| 15 | uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O |
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| 16 | uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O |
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| 17 | uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O |
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| 18 | uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O |
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| 19 | |
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| 20 | |
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