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[15] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
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| 2 | <!-- IMPORTANT: This is an internal file that has been generated |
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| 3 | by the Xilinx ISE software. Any direct editing or |
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| 4 | changes made to this file may result in unpredictable |
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| 5 | behavior or data corruption. It is strongly advised that |
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| 6 | users do not edit the contents of this file. --> |
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| 7 | <messages> |
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| 8 | <msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> library for correct compilation and simulation. |
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| 9 | </msg> |
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| 10 | |
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| 11 | </messages> |
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| 12 | |
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