source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/netgen.xmsgs @ 15

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
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<messages>
<msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> library for correct compilation and simulation. 
</msg>

</messages>