source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/planAhead_run_1/planAhead.log @ 16

Last change on this file since 16 was 15, checked in by rolagamo, 12 years ago
File size: 14.2 KB
Line 
1#-----------------------------------------------------------
2# PlanAhead v12.3
3# Build 101344 by hdbuild on Sat Sep  4 00:26:34 MDT 2010
4# Start of session at: Fri Aug 17 14:11:50 2012
5# Process ID: 17924
6# Log file: C:/Core MPI/CORE_MPI/planAhead_run_1/planAhead.log
7# Journal file: C:/Core MPI/CORE_MPI/planAhead_run_1/planAhead.jou
8#-----------------------------------------------------------
9INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead
10INFO: [HD-Licensing 1] Got a license: PlanAhead
11INFO: [HD-Licensing 3] Your PlanAhead license expires in -291 day(s)
12INFO: [HD-ArchReader 0] Loading parts and site information from D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\arch.xml
13INFO: [HD-RTPRIM 0] Parsing RTL primitives file 'D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
14INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file 'D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
15start_gui -source {C:/Core MPI/CORE_MPI/pa.fromHdl.tcl}
16# create_project -name MPI_CORE_COMPONENTS -dir "C:/Core MPI/CORE_MPI/planAhead_run_1" -part xc6slx100fgg484-3
17# set_param project.pinAheadLayout yes
18# set srcset [get_property srcset [current_run -impl]]
19# set_property top MultiMPITest $srcset
20# set_param project.paUcfFile  "MultiMPITest.ucf"
21# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/CoreTypes.vhd}]]
22# set_property file_type VHDL $hdlfile
23# set_property library NocLib $hdlfile
24# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/RAM_256.vhd}]]
25# set_property file_type VHDL $hdlfile
26# set_property library NocLib $hdlfile
27# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Arbiter.vhd}]]
28# set_property file_type VHDL $hdlfile
29# set_property library NocLib $hdlfile
30# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd}]]
31# set_property file_type VHDL $hdlfile
32# set_property library NocLib $hdlfile
33# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbit.vhd}]]
34# set_property file_type VHDL $hdlfile
35# set_property library NocLib $hdlfile
36# set hdlfile [add_files [list {round_robbin_machine.vhd}]]
37# set_property file_type VHDL $hdlfile
38# set_property library work $hdlfile
39# set hdlfile [add_files [list {RAM_64.vhd}]]
40# set_property file_type VHDL $hdlfile
41# set_property library work $hdlfile
42# set hdlfile [add_files [list {Packet_type.vhd}]]
43# set_property file_type VHDL $hdlfile
44# set_property library work $hdlfile
45# set hdlfile [add_files [list {MUX8.vhd}]]
46# set_property file_type VHDL $hdlfile
47# set_property library work $hdlfile
48# set hdlfile [add_files [list {MUX1.vhd}]]
49# set_property file_type VHDL $hdlfile
50# set_property library work $hdlfile
51# set hdlfile [add_files [list {DEMUX1.vhd}]]
52# set_property file_type VHDL $hdlfile
53# set_property library work $hdlfile
54# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Scheduler.vhd}]]
55# set_property file_type VHDL $hdlfile
56# set_property library NocLib $hdlfile
57# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd}]]
58# set_property file_type VHDL $hdlfile
59# set_property library NocLib $hdlfile
60# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd}]]
61# set_property file_type VHDL $hdlfile
62# set_property library NocLib $hdlfile
63# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbar.vhd}]]
64# set_property file_type VHDL $hdlfile
65# set_property library NocLib $hdlfile
66# set hdlfile [add_files [list {MPI_CORE_SCHEDULER.vhd}]]
67# set_property file_type VHDL $hdlfile
68# set_property library work $hdlfile
69# set hdlfile [add_files [list {load_instr.vhd}]]
70# set_property file_type VHDL $hdlfile
71# set_property library work $hdlfile
72# set hdlfile [add_files [list {FIFO_64_FWFT.vhd}]]
73# set_property file_type VHDL $hdlfile
74# set_property library work $hdlfile
75# set hdlfile [add_files [list {EX4_FSM.vhd}]]
76# set_property file_type VHDL $hdlfile
77# set_property library work $hdlfile
78# set hdlfile [add_files [list {EX3_FSM.vhd}]]
79# set_property file_type VHDL $hdlfile
80# set_property library work $hdlfile
81# set hdlfile [add_files [list {EX2_FSM.vhd}]]
82# set_property file_type VHDL $hdlfile
83# set_property library work $hdlfile
84# set hdlfile [add_files [list {EX1_FSM.vhd}]]
85# set_property file_type VHDL $hdlfile
86# set_property library work $hdlfile
87# set hdlfile [add_files [list {Ex0_Fsm.vhd}]]
88# set_property file_type VHDL $hdlfile
89# set_property library work $hdlfile
90# set hdlfile [add_files [list {DMA_ARBITER.vhd}]]
91# set_property file_type VHDL $hdlfile
92# set_property library work $hdlfile
93# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd}]]
94# set_property file_type VHDL $hdlfile
95# set_property library NocLib $hdlfile
96# set hdlfile [add_files [list {RAM_32_32.vhd}]]
97# set_property file_type VHDL $hdlfile
98# set_property library work $hdlfile
99# set hdlfile [add_files [list {CORE_MPI.vhd}]]
100# set_property file_type VHDL $hdlfile
101# set_property library work $hdlfile
102# set hdlfile [add_files [list {PE.vhd}]]
103# set_property file_type VHDL $hdlfile
104# set_property library work $hdlfile
105# set hdlfile [add_files [list {MPI_NOC.vhd}]]
106# set_property file_type VHDL $hdlfile
107# set_property library work $hdlfile
108# set hdlfile [add_files [list {MultiMPITest.vhd}]]
109# set_property file_type VHDL $hdlfile
110# set_property library work $hdlfile
111# add_files "MultiMPITest.ucf" -fileset [get_property constrset [current_run]]
112# add_files -norecurse { {C:/Core MPI/CORE_MPI} }
113# open_rtl_design -part xc6slx100fgg484-3
114INFO: [HD-RTLIN 2] Parsing VHDL file "D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
115INFO: [HD-RTLIN 2] Parsing package <attributes>.
116INFO: [HD-RTLIN 2] Parsing VHDL file "D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
117INFO: [HD-RTLIN 2] Parsing package <attributes>.
118INFO: [HD-RTLIN 2] Parsing Verilog file "C:\Core MPI\CORE_MPI\Ex0_FSM.v" into library work
119INFO: [HD-RTLIN 2] Parsing module <Ex0_FSM>.
120INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" into library NocLib
121INFO: [HD-RTLIN 2] Parsing package <CoreTypes>.
122INFO: [HD-RTLIN 2] Parsing package body <CoreTypes>.
123INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\RAM_256.vhd" into library NocLib
124INFO: [HD-RTLIN 2] Parsing entity <RAM_256>.
125INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_256>.
126INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Arbiter.vhd" into library NocLib
127INFO: [HD-RTLIN 2] Parsing entity <Arbiter>.
128INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <arbiter>.
129INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\FIFO_256_FWFT.vhd" into library NocLib
130INFO: [HD-RTLIN 2] Parsing entity <FIFO_256_FWFT>.
131INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <fifo_256_fwft>.
132INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbit.vhd" into library NocLib
133INFO: [HD-RTLIN 2] Parsing entity <Crossbit>.
134INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <crossbit>.
135INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" into library work
136INFO: [HD-RTLIN 2] Parsing entity <round_robbin_machine>.
137INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <round_robbin_machine>.
138INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_64.vhd" into library work
139INFO: [HD-RTLIN 2] Parsing entity <RAM_64>.
140INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_64>.
141INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Packet_type.vhd" into library work
142INFO: [HD-RTLIN 2] Parsing package <Packet_type>.
143INFO: [HD-RTLIN 2] Parsing package body <Packet_type>.
144INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MUX8.vhd" into library work
145INFO: [HD-RTLIN 2] Parsing entity <MUX8>.
146INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mux8>.
147INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MUX1.vhd" into library work
148INFO: [HD-RTLIN 2] Parsing entity <MUX1>.
149INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mux1>.
150INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\DEMUX1.vhd" into library work
151INFO: [HD-RTLIN 2] Parsing entity <DEMUX1>.
152INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <demux1>.
153INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Scheduler.vhd" into library NocLib
154INFO: [HD-RTLIN 2] Parsing entity <Scheduler>.
155INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <scheduler>.
156INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\OUTPUT_PORT_MODULE.vhd" into library NocLib
157INFO: [HD-RTLIN 2] Parsing entity <OUTPUT_PORT_MODULE>.
158INFO: [HD-RTLIN 2] Parsing architecture <Behavioral_description> of entity <output_port_module>.
159INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd" into library NocLib
160INFO: [HD-RTLIN 2] Parsing entity <INPUT_PORT_MODULE>.
161INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <input_port_module>.
162INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd" into library NocLib
163INFO: [HD-RTLIN 2] Parsing entity <Crossbar>.
164INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <crossbar>.
165INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" into library work
166INFO: [HD-RTLIN 2] Parsing entity <MPI_CORE_SCHEDULER>.
167INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mpi_core_scheduler>.
168INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\load_instr.vhd" into library work
169INFO: [HD-RTLIN 2] Parsing entity <load_instr>.
170INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <load_instr>.
171INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" into library work
172INFO: [HD-RTLIN 2] Parsing entity <FIFO_64_FWFT>.
173INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <fifo_64_fwft>.
174INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" into library work
175INFO: [HD-RTLIN 2] Parsing entity <EX4_FSM>.
176INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex4_fsm>.
177INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" into library work
178INFO: [HD-RTLIN 2] Parsing entity <EX3_FSM>.
179INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex3_fsm>.
180INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" into library work
181INFO: [HD-RTLIN 2] Parsing entity <EX2_FSM>.
182INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex2_fsm>.
183INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" into library work
184INFO: [HD-RTLIN 2] Parsing entity <EX1_FSM>.
185INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex1_fsm>.
186INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" into library work
187INFO: [HD-RTLIN 2] Parsing entity <Ex0_Fsm>.
188INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex0_fsm>.
189INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" into library work
190INFO: [HD-RTLIN 2] Parsing entity <DMA_ARBITER>.
191INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <dma_arbiter>.
192INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.vhd" into library NocLib
193INFO: [HD-RTLIN 2] Parsing entity <SWITCH_GEN>.
194INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <switch_gen>.
195INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_32_32.vhd" into library work
196INFO: [HD-RTLIN 2] Parsing entity <RAM_v>.
197INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_v>.
198INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" into library work
199INFO: [HD-RTLIN 2] Parsing entity <CORE_MPI>.
200INFO: [HD-RTLIN 2] Parsing architecture <Structural> of entity <core_mpi>.
201INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\PE.vhd" into library work
202INFO: [HD-RTLIN 2] Parsing entity <PE>.
203INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <pe>.
204INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_NOC.vhd" into library work
205INFO: [HD-RTLIN 2] Parsing entity <MPI_NOC>.
206INFO: [HD-RTLIN 2] Parsing architecture <structural> of entity <mpi_noc>.
207INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MultiMPITest.vhd" into library work
208INFO: [HD-RTLIN 2] Parsing entity <MultiMPITest>.
209INFO: [HD-RTLIN 2] Parsing architecture <behavior> of entity <multimpitest>.
210INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_MUX.vhd" into library work
211INFO: [HD-RTLIN 2] Parsing entity <RAM_MUX>.
212INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_mux>.
213INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Processing_node.vhd" into library work
214INFO: [HD-RTLIN 2] Parsing entity <PROCESSING_ELEMENT>.
215ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(43) Syntax error near "downto".
216ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(53) Syntax error near ")".
217ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(62) Syntax error near "type".
218ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(66) <typ_mae> is not declared.
219ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(70) Syntax error near "BEGIN".
220ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(81) Syntax error near "begin".
221INFO: [HD-RTLIN 2] VHDL file C:\Core MPI\CORE_MPI\Processing_node.vhd ignored due to errors
222INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_RMA.vhd" into library work
223INFO: [HD-RTLIN 2] Parsing package <Mpi_Rma>.
224INFO: [HD-RTLIN 2] Parsing package body <MPI_Rma>.
225INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_PKG.vhd" into library work
226INFO: [HD-RTLIN 2] Parsing package <mpi_pkg>.
227INFO: [HD-RTLIN 2] Parsing package body <MPI_PKG>.
228INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPICORETEST.vhd" into library work
229INFO: [HD-RTLIN 2] Parsing entity <MPICORETEST>.
230INFO: [HD-RTLIN 2] Parsing architecture <behavior> of entity <mpicoretest>.
231ERROR: Unable to process your HDL design.  Please review Elaboration Messages.
232exit
233INFO: [HD-Application 0] Exiting PlanAhead...
234INFO: [HD-Licensing 2] Releasing license: PlanAhead
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