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OUTPUT_PORT_MODULE.vhd @ 139

Last change on this file since 139 was 139, checked in by rolagamo, 10 years ago
Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
File size: 7.1 KB

Line
1
2	----------------------------------------------------------------------------------
3	-- Company:
4	-- Engineer:
5	--
6	-- Create Date: 09:29:48 04/18/2011
7	-- Design Name:
8	-- Module Name: OUTPUT_PORT_MODULE - Behavioral_description
9	-- Project Name:
10	-- Target Devices:
11	-- Tool versions:
12	-- Description:
13	-- cette version du module de sortie se limite à une instance du fifo ordinaire
14	-- les données son emise en sortie à chaque cycle d'horloge
15	-- Dependencies:
16	--
17	-- Revision: 07-08-2013
18	-- Revision 0.01 - File Created
19	-- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis
20	-- longtemps
21	--Revision: Mai-02-2014
22	-- Revision 0.01 - File
23	-- Additional Comments: Passage à la version 16 bits
24	-- longtemps
25	----------------------------------------------------------------------------------
26	library IEEE;
27	use IEEE.STD_LOGIC_1164.ALL;
28	--use IEEE.STD_LOGIC_ARITH.ALL;
29	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
30	USE ieee.numeric_std.ALL;
31	Library NocLib;
32	use NocLib.CoreTypes.all;
33	---- Uncomment the following library declaration if instantiating
34	---- any Xilinx primitives in this code.
35	--library UNISIM;
36	--use UNISIM.VComponents.all;
37
38	entity OUTPUT_PORT_MODULE is
39	generic( nbyte : positive:=2); -- le nombre de Byte dans chaque mot du port par défaut 2
40
41	Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0);
42	reset : in STD_LOGIC;
43	clk : in STD_LOGIC;
44	wr_en : in STD_LOGIC;
45	data_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
46	fifo_full : out std_logic;
47	data_avalaible : out std_logic;
48	rd_out_en : in STD_LOGIC);
49	end OUTPUT_PORT_MODULE;
50
51	architecture Behavioral_description of OUTPUT_PORT_MODULE is
52	-- declaration du FIFO 64 octets
53	component FIFO_256_FWFT
54	port (
55	clk: IN std_logic;
56	din: IN std_logic_VECTOR(Word-1 downto 0);
57	rd_en: IN std_logic;
58	srst: IN std_logic;
59	wr_en: IN std_logic;
60	dout: out std_logic_VECTOR(Word-1 downto 0);
61	empty: OUT std_logic;
62	full: OUT std_logic);
63	end component;
64	--definition du type etat pour les fsm
65	type typ_outfsm is (Idle,waiting,dropping,reading);
66	type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
67	type typ_store is (idle,accu,transf);
68	signal EtRec : typ_receiv;
69	signal Et_store,next_et_store: typ_store;
70	signal Et_out_fsm : typ_outfsm;
71	signal fifo_empty ,fifo_wr: std_logic:='0';
72	signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes
73	signal tlimit : natural:=0; --permet de compter les impulsions de temps
74	signal n : natural:=0; --utiliser pour la mae du tampon de sortie
75	signal nib : natural:=nbyte; --nombre de byte à transférer
76	signal rcv_start : std_logic; --début de la réception
77	signal rcv_ack : std_logic; -- acquittement de la réception
78	signal rcv_comp : std_logic; -- fin de la réception
79	signal spop,pop,rd_en,dat_avail : std_logic:='0';
80	signal fifo_in :std_logic_vector(Word-1 downto 0); --le tampon de données d'entrée
81	signal mem,fifo_out : std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel
82	begin
83	-- instantiation du FIFO_64
84	OUTPUT_PORT_FIFO : FIFO_256_FWFT
85	port map (
86	clk => clk,
87	din => fifo_in,
88	rd_en => rd_en,
89	srst => reset,
90	wr_en => fifo_wr,
91	dout => fifo_out,
92	empty => fifo_empty,
93	full => fifo_full);
94	--sync_store_state:process (clk)
95	--begin
96	--if rising_edge(clk) then
97	-- if reset='1' then
98	-- et_store<=idle;
99	-- else
100	-- et_store<=next_et_store;
101	-- end if;
102	--
103	--end if;
104	--end process sync_store_state;
105	next_store_state:process (clk)
106	begin
107	if rising_edge(clk) then
108	case et_store is
109	when idle =>
110	if wr_en='1' then
111	et_store<=transf;
112	nib<=nib-1;
113	else
114	nib<=nbyte;
115	end if;
116
117
118	when accu =>
119
120	if nib=1 then
121	et_store<=transf;
122
123	nib<=nbyte;
124	else
125	nib<=nib-1;
126	end if;
127
128	when transf =>
129	--next_et_store<=idle;
130	if wr_en='1' then
131	if nib=1 then
132	nib<=nbyte;
133	else
134	nib<=nib-1;
135	end if;
136	et_store<=accu;
137	else
138	nib<=nbyte;
139	et_store<=idle;
140	end if;
141	end case ;
142
143	end if;
144	end process next_store_state;
145
146	val_store_state:process (et_store,nib,data_in,wr_en)
147	begin
148	--case et_store is
149	--when transf =>fifo_wr<='1';
150	--when others => fifo_wr<='0';
151	--end case;
152	if nib=1 then
153	fifo_wr<='1';
154	else
155	fifo_wr<='0';
156	end if;
157	fifo_in(8nib-1 downto 8(nib-1))<=data_in;
158	end process val_store_state;
159
160
161	outport_proc : process(clk,reset,fifo_empty)
162	begin
163
164	if rising_edge(clk) then
165	if reset='1' then
166	n<=0;
167	Et_out_fsm<=Idle;
168	else
169	case(Et_out_fsm) is
170
171	when Idle => --idle
172	if fifo_empty = '0' then
173	Et_Out_fsm<=waiting;
174	end if;
175	tlimit<=0;
176	sw<='0';
177	when reading =>
178	if rd_out_en='0' then
179	Et_out_fsm<=Idle;
180	end if;
181	sw<='0';
182	when waiting => --counting
183	if rd_out_en='1' then
184	Et_out_fsm<=reading;
185	elsif tlimit=5000 then
186	Et_out_fsm<=dropping;
187	tlimit<=0;
188	else
189	tlimit<=tlimit+1;
190	end if;
191	sw<='0';
192	when dropping => --dropping packet
193	if n=0 then
194	rcv_start<='1';
195	n<=1;
196	sw<='1';
197	elsif n=1 then
198	if rcv_comp='1' then
199	rcv_ack<='1';
200	rcv_start<='0';
201	n<=2;
202	end if;
203	sw<='1';
204	elsif n=2 then
205	sw<='0';
206	Et_out_fsm<=Idle;
207	report "Attention Paquet perdu !à Output_Port_Module";
208	n<=0;
209	end if;
210
211	end case;
212	end if;
213	end if;
214	end process outport_proc;
215	data_out<=fifo_out;
216	mux_proc : process (sw,rd_out_en,pop,fifo_empty)
217	begin
218	if sw='1' then --mode drop
219	rd_en<=pop;
220	data_avalaible <='0'; --plus de données dans le tampon !
221	else
222	rd_en<=rd_out_en;
223	data_avalaible <= not fifo_empty;
224	end if;
225	end process mux_proc;
226	proc_receiv : process (clk,reset)
227	variable dlen,i: natural range 0 to 255 :=0;
228
229	begin
230	if reset='1' then
231	etrec<=r_wait;
232
233	else
234	if rising_edge(clk) then -- le process s'exécute sur chaque front
235	-- montant de l'horloge
236	case etrec is
237	when r_wait =>
238
239	i:=0;
240	if fifo_empty='0' and rcv_start='1' then
241
242	etrec<=r_head;
243	mem<=fifo_out;
244
245	end if;
246	when r_head =>
247	mem<=fifo_out; --l'en-tête
248
249	etrec<=r_len;
250	when r_len =>
251	dlen:=to_integer(unsigned(fifo_out));
252	mem<=fifo_out; -- la longueur
253
254	if dlen>2 then
255	etrec<=r_data;
256	else
257	etrec<=r_end;
258	end if;
259	i:=1;
260
261	when r_data =>
262	if fifo_empty='0' then
263	if i<dlen-2 then
264	i:=i+1;
265	mem<=fifo_out;
266
267
268	else
269	etrec<=r_pulse;
270
271	mem<=fifo_out;
272	end if;
273	-- time out à prévoir ici
274	end if;
275	when r_pulse =>
276	etrec<=r_end;
277
278	when r_end =>
279	if rcv_ack='1' then
280	etrec<=r_wait;
281	end if;
282
283	when others =>
284
285
286	etrec<=r_wait;
287	end case;
288	end if;
289	end if;
290	end process;
291
292	pop<=spop;
293
294	rec_value : process (etrec)
295	begin
296	case etrec is
297	when r_wait =>
298	spop<='0';
299	rcv_comp<='0';
300	when r_head =>
301
302	spop<='1';
303	rcv_comp<='0';
304
305	when r_len =>
306	spop<='1';
307	when r_data =>
308	spop<='1';
309	when r_pulse =>
310	spop<='0';
311	rcv_comp<='1';
312	when r_end =>
313	spop<='0';
314	rcv_comp<='1';
315	when others =>
316	spop<='0';
317	rcv_comp<='0';
318	end case;
319	end process;
320
321	end Behavioral_description;
322

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/OUTPUT_PORT_MODULE.vhd @ 139

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