Changeset 139 for PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/OUTPUT_PORT_MODULE.vhd

Timestamp:

May 21, 2014, 11:36:19 AM (10 years ago)

Author:

rolagamo

Message:

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

Location:

PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0

Files:

• . (copied) (copied from PROJECT_CORE_MPI/MPI_HCL/TRUNK)
• NOC (copied) (copied from PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC)
• NOC/OUTPUT_PORT_MODULE.vhd (modified) (4 diffs)

PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/OUTPUT_PORT_MODULE.vhd

@@ -19 +19 @@
 -- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis
 -- longtemps
---
+--Revision: Mai-02-2014
+-- Revision 0.01 - File 
+-- Additional Comments: Passage à la version 16 bits
+-- longtemps
 ----------------------------------------------------------------------------------
 library IEEE;
@@ -34 +37 @@
 
 entity OUTPUT_PORT_MODULE is
-    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+        generic(        nbyte : positive:=2); -- le nombre de Byte dans chaque mot du port par défaut 2
+  
+    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
            reset : in  STD_LOGIC;
            clk : in  STD_LOGIC;
@@ -60 +65 @@
 type typ_outfsm is (Idle,waiting,dropping,reading);
 type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
-
+type typ_store is (idle,accu,transf);
 signal EtRec : typ_receiv;
+signal Et_store,next_et_store: typ_store;
 signal Et_out_fsm : typ_outfsm;
-signal fifo_empty : std_logic;  
+signal fifo_empty ,fifo_wr: std_logic:='0';     
 signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes
 signal tlimit : natural:=0; --permet de compter les impulsions de temps
 signal n : natural:=0; --utiliser pour la mae du tampon de sortie
+signal nib : natural:=nbyte; --nombre de byte à transférer
 signal rcv_start :  std_logic; --début de la réception
 signal  rcv_ack : std_logic;   -- acquittement de la réception
 signal  rcv_comp :  std_logic; -- fin de la réception
 signal   spop,pop,rd_en,dat_avail :  std_logic:='0';
+signal fifo_in :std_logic_vector(Word-1 downto 0); --le tampon de données d'entrée
 signal  mem,fifo_out :  std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel
 begin
@@ -77 +85 @@
                 port map (
                         clk => clk,
-                        din => data_in,
+                        din => fifo_in,
                         rd_en => rd_en,
                         srst => reset,
-                        wr_en => wr_en,
+                        wr_en => fifo_wr,
                         dout => fifo_out,
                         empty => fifo_empty,
                         full => fifo_full);
-                        
+--sync_store_state:process (clk)
+--begin
+--if rising_edge(clk) then
+--              if reset='1' then
+--                      et_store<=idle;
+--              else
+--                      et_store<=next_et_store;
+--              end if;
+--
+--end if;
+--end process sync_store_state;                 
+next_store_state:process (clk)
+begin
+if rising_edge(clk) then
+case et_store is
+when idle =>
+if wr_en='1' then
+et_store<=transf;
+nib<=nib-1;
+else
+ nib<=nbyte; 
+end if;
+
+
+when accu =>
+                
+                if nib=1 then
+                  et_store<=transf;
+                  
+                  nib<=nbyte;
+                else
+                 nib<=nib-1; 
+                end if;
+
+when transf =>
+        --next_et_store<=idle;  
+        if wr_en='1' then
+          if nib=1 then 
+            nib<=nbyte;
+           else
+         nib<=nib-1;
+          end if; 
+         et_store<=accu;
+        else
+         nib<=nbyte;
+         et_store<=idle;
+        end if;
+end case ;
+
+end if;
+end process next_store_state;
+
+val_store_state:process (et_store,nib,data_in,wr_en)
+begin
+--case et_store is
+--when transf =>fifo_wr<='1';
+--when others => fifo_wr<='0';
+--end case;
+if nib=1 then
+  fifo_wr<='1';
+else
+  fifo_wr<='0';
+end if;
+fifo_in(8*nib-1 downto 8*(nib-1))<=data_in;
+end process val_store_state;
+
 
 outport_proc : process(clk,reset,fifo_empty)
 begin
+
 if rising_edge(clk) then
 if reset='1' then