1 | --------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: KIEGAING EMMANUEL GEL EN 5 |
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4 | -- |
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5 | -- Create Date: 03:56:34 05/06/2011 |
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6 | -- Design Name: |
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7 | -- Module Name: Sheduler - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: Module de l'ordonnanceur du switch crossbar |
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12 | -- l'algorithme utilisée est le DPA (diagonal propagation arbiter) |
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13 | -- |
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14 | -- Dependencies: |
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15 | -- |
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16 | -- Revision: |
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17 | -- Revision 0.01 - File Created |
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18 | -- Additional Comments: |
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19 | -- |
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20 | ---------------------------------------------------------------------------------- |
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21 | library IEEE; |
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22 | use IEEE.STD_LOGIC_1164.ALL; |
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23 | use IEEE.STD_LOGIC_ARITH.ALL; |
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24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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25 | --use Work.Sheduler_package.all; |
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26 | |
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27 | ---- Uncomment the following library declaration if instantiating |
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28 | ---- any Xilinx primitives in this code. |
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29 | --library UNISIM; |
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30 | --use UNISIM.VComponents.all; |
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31 | entity Scheduler3_3 is |
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32 | Port ( Req : in STD_LOGIC_VECTOR (9 downto 1); |
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33 | Fifo_full : in STD_LOGIC_VECTOR (3 downto 1); |
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34 | clk : in STD_LOGIC; |
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35 | reset : in STD_LOGIC; |
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36 | priority_rotation : in STD_LOGIC_VECTOR (3 downto 1); |
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37 | port_grant : out STD_LOGIC_VECTOR (9 downto 1)); |
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38 | end Scheduler3_3; |
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39 | |
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40 | architecture Behavioral of Scheduler3_3 is |
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41 | constant NB_IO:positive:=3; |
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42 | --Declaration du types |
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43 | --tableau de signaux de connexion des cellules arbitres |
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44 | TYPE C_Bar_Signal_Array IS ARRAY(5 downto 1) of STD_LOGIC_VECTOR(3 downto 1); |
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45 | -- declaration du composant cellule d'arbitrage |
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46 | Component Arbiter |
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47 | PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; |
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48 | Grant,East,South : out STD_LOGIC ); |
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49 | End Component; |
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50 | -- |
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51 | component Def_Request is |
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52 | generic (NB_IO :positive:=3); |
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53 | Port ( Req : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); |
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54 | clk : in STD_LOGIC; |
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55 | reset : in STD_LOGIC; |
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56 | fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1); |
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57 | priority_rotation : in STD_LOGIC_VECTOR (NB_IO downto 1); |
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58 | grant : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); |
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59 | request : out STD_LOGIC_VECTOR (NB_IO**2 downto 1)); |
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60 | end component; |
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61 | constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S |
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62 | --Signaux de connexion des cellues |
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63 | SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north |
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64 | SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west |
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65 | SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité |
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66 | SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation |
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67 | SIGNAL Signal_priority : STD_LOGIC_VECTOR (2*NB_IO-1 DOWNTO 1);--signal pour la connection des vecteurs de priorité |
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68 | SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest |
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69 | |
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70 | signal priority_rotation_en : std_logic; |
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71 | |
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72 | signal Grant,request : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); |
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73 | begin |
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74 | |
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75 | --validation de la rotation de priorité lorsque aucun port n'emet |
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76 | |
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77 | --priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else '0'; |
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78 | priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; |
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79 | --latch servant qui memorise le signal grant pendant a transmission |
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80 | --cette instance permet de déterminer le vecteur request |
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81 | --en fonction de l'état fifo_full et de la requête initiale |
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82 | inst_defreq: def_request generic map (NB_IO) |
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83 | port map (clk=>clk, |
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84 | reset=>reset, |
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85 | req=>req, |
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86 | fifo_full=>fifo_full, |
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87 | priority_rotation=>priority_rotation, |
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88 | grant=>grant, |
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89 | request=>request |
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90 | ); |
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91 | port_grant <= grant; |
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92 | Grant(1) <= Signal_grant(1)(1) or Signal_grant(4)(1); -- Grant(1,1) |
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93 | Grant(2) <= Signal_grant(2)(2) or Signal_grant(5)(2); -- Grant(1,2) |
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94 | Grant(3) <= Signal_grant(3)(3) ; -- Grant(1,3) |
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95 | Grant(4) <= Signal_grant(2)(1) or Signal_grant(5)(1); -- Grant(2,1) |
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96 | Grant(5) <= Signal_grant(3)(2) ; -- Grant(2,2) |
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97 | Grant(6) <= Signal_grant(1)(3) or Signal_grant(4)(3); -- Grant(2,3) |
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98 | Grant(7) <= Signal_grant(3)(1) ; -- Grant(3,1) |
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99 | Grant(8) <= Signal_grant(1)(2) or Signal_grant(4)(2); -- Grant(3,2) |
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100 | Grant(9) <= Signal_grant(2)(3) or Signal_grant(5)(3); -- Grant(3,3) |
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101 | High <= '1'; |
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102 | |
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103 | ----instantiations des cellules arbitres et interconnection |
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104 | |
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105 | -------------------------- Diagonale n° 1 |
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106 | |
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107 | |
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108 | Arbiter_1_1 : Arbiter |
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109 | |
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110 | PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(1), |
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111 | South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); |
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112 | |
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113 | Arbiter_1_2 : Arbiter |
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114 | |
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115 | PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(2), |
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116 | South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); |
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117 | |
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118 | Arbiter_1_3 : Arbiter |
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119 | |
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120 | PORT MAP (Request => Request(6), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(3), |
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121 | South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); |
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122 | |
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123 | -------------------------- Diagonale n° 2 |
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124 | |
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125 | |
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126 | Arbiter_2_1 : Arbiter |
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127 | |
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128 | PORT MAP (Request => Request(4), North => south_2_north(1)(1), West => east_2_west(1)(3), P => Signal_priority(4), Fifo_full => Fifo_full(1), |
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129 | South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); |
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130 | |
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131 | Arbiter_2_2 : Arbiter |
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132 | |
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133 | PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), |
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134 | South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); |
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135 | |
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136 | Arbiter_2_3 : Arbiter |
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137 | |
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138 | PORT MAP (Request => Request(9), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), |
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139 | South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); |
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140 | |
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141 | -------------------------- Diagonale n° 3 |
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142 | |
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143 | |
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144 | Arbiter_3_1 : Arbiter |
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145 | |
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146 | PORT MAP (Request => Request(7), North => south_2_north(2)(1), West => east_2_west(2)(3), P => Signal_priority(3), Fifo_full => Fifo_full(1), |
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147 | South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); |
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148 | |
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149 | Arbiter_3_2 : Arbiter |
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150 | |
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151 | PORT MAP (Request => Request(5), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), |
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152 | South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); |
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153 | |
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154 | Arbiter_3_3 : Arbiter |
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155 | |
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156 | PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), |
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157 | South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); |
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158 | |
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159 | -------------------------- Diagonale n° 4 |
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160 | |
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161 | |
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162 | Arbiter_4_1 : Arbiter |
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163 | |
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164 | PORT MAP (Request => Request(1), North => south_2_north(3)(1), West => east_2_west(3)(3), P => Signal_priority(2), Fifo_full => Fifo_full(1), |
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165 | South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); |
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166 | |
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167 | Arbiter_4_2 : Arbiter |
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168 | |
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169 | PORT MAP (Request => Request(8), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), |
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170 | South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); |
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171 | |
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172 | Arbiter_4_3 : Arbiter |
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173 | |
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174 | PORT MAP (Request => Request(6), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), |
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175 | South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); |
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176 | |
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177 | -------------------------- Diagonale n° 5 |
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178 | |
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179 | |
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180 | Arbiter_5_1 : Arbiter |
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181 | |
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182 | PORT MAP (Request => Request(4), North => south_2_north(4)(1), West => east_2_west(4)(3), P => Signal_priority(1), Fifo_full => Fifo_full(1), |
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183 | South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); |
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184 | |
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185 | Arbiter_5_2 : Arbiter |
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186 | |
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187 | PORT MAP (Request => Request(2), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), |
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188 | South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); |
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189 | |
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190 | Arbiter_5_3 : Arbiter |
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191 | |
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192 | PORT MAP (Request => Request(9), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), |
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193 | South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); |
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194 | |
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195 | |
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196 | --processus permettant de roter la priorité des diagonales à chaque front d'horloge |
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197 | -- rotation round robin |
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198 | round_robin : process(clk) |
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199 | begin |
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200 | if rising_edge(clk) then |
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201 | if reset ='1' then |
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202 | Signal_priority <= "11100"; |
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203 | elsif priority_rotation_en = '1' then |
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204 | case Signal_priority is |
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205 | when "11100" => Signal_priority <= "01110"; |
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206 | when "01110" => Signal_priority <= "00111"; |
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207 | when "00111" => Signal_priority <= "11100"; |
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208 | when others => Signal_priority <= "11100"; |
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209 | end case; |
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210 | end if; |
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211 | end if; |
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212 | end process; |
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213 | |
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214 | end Behavioral; |
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215 | |
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