- Timestamp:
- May 21, 2014, 11:36:19 AM (10 years ago)
- Location:
- PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0
- Files:
-
- 1 edited
- 2 copied
Legend:
- Unmodified
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PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER3_3.VHD
r101 r139 30 30 --use UNISIM.VComponents.all; 31 31 entity Scheduler3_3 is 32 Port ( Req uest: in STD_LOGIC_VECTOR (9 downto 1);32 Port ( Req : in STD_LOGIC_VECTOR (9 downto 1); 33 33 Fifo_full : in STD_LOGIC_VECTOR (3 downto 1); 34 34 clk : in STD_LOGIC; … … 39 39 40 40 architecture Behavioral of Scheduler3_3 is 41 constant NB_IO:positive:=3; 41 42 --Declaration du types 42 43 --tableau de signaux de connexion des cellules arbitres … … 46 47 PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; 47 48 Grant,East,South : out STD_LOGIC ); 48 End Component;--Signaux de connexion des cellues 49 End Component; 50 -- 51 component Def_Request is 52 generic (NB_IO :positive:=3); 53 Port ( Req : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); 54 clk : in STD_LOGIC; 55 reset : in STD_LOGIC; 56 fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1); 57 priority_rotation : in STD_LOGIC_VECTOR (NB_IO downto 1); 58 grant : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); 59 request : out STD_LOGIC_VECTOR (NB_IO**2 downto 1)); 60 end component; 61 constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S 62 --Signaux de connexion des cellues 49 63 SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north 50 64 SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west 51 65 SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité 52 66 SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation 53 SIGNAL Signal_priority : STD_LOGIC_VECTOR ( 5 DOWNTO 1);--signal pour la connection des vecteurde priorité67 SIGNAL Signal_priority : STD_LOGIC_VECTOR (2*NB_IO-1 DOWNTO 1);--signal pour la connection des vecteurs de priorité 54 68 SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest 55 signal grant_latch : std_logic_vector(9 downto 1); 69 56 70 signal priority_rotation_en : std_logic; 57 signal Grant,req_grant : std_logic_vector(9 downto 1); 71 72 signal Grant,request : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); 58 73 begin 59 74 60 75 --validation de la rotation de priorité lorsque aucun port n'emet 61 req_grant<=(request and grant_latch); 62 priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else '0'; 76 77 --priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else '0'; 78 priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; 63 79 --latch servant qui memorise le signal grant pendant a transmission 64 grant_latch_process : process(clk) 65 begin 66 if rising_edge(clk) then 67 if reset = '1' then 68 grant_latch <= (others => '0'); 69 elsif priority_rotation_en = '1' then 70 grant_latch <= Grant; 71 end if; 72 end if; 73 end process; 74 port_grant <= grant_latch; 80 --cette instance permet de déterminer le vecteur request 81 --en fonction de l'état fifo_full et de la requête initiale 82 inst_defreq: def_request generic map (NB_IO) 83 port map (clk=>clk, 84 reset=>reset, 85 req=>req, 86 fifo_full=>fifo_full, 87 priority_rotation=>priority_rotation, 88 grant=>grant, 89 request=>request 90 ); 91 port_grant <= grant; 75 92 Grant(1) <= Signal_grant(1)(1) or Signal_grant(4)(1); -- Grant(1,1) 76 93 Grant(2) <= Signal_grant(2)(2) or Signal_grant(5)(2); -- Grant(1,2)
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