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SWITCH_GEN.vhd @ 139

Last change on this file since 139 was 139, checked in by rolagamo, 10 years ago
Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
File size: 234.8 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company: ENSET 2011
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 03:40:47 11/19/2011
6	-- Design Name:
7	-- Module Name: SWITCH_GEN - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- fichier principal du switch générique; en fonction du parametre generique le
13	-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement la logique
14	-- nécessaire à l'implémentation du switch de la dimension voulue
15	-- Dependencies:
16	-- Modifié le 28/04/1975
17	-- Revision:
18	-- Revision 0.01 - File Created
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	use work.Coretypes.all ;
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity SWITCH_GEN is
33	--type portio is array(positive range) of std_logic_vector (7 downto 0);
34	generic(n_ports : positive := 8;-- :nombre de ports E/S du NoC 2 à 16
35	tot_ports: positive :=16; -- nombre total de ports
36	NET_ADR :std_logic_vector(9 downto 0):="0000000000";
37	NET_MASK:natural:=0); -- Nombre de bits à un du masque en partant de la gauche
38	port(
39	-- ports d'entree
40	Port_in : in typ_portIO(1 to n_ports) ;
41
42
43	-- port de sortie
44	Port_out : out typ_portIO(1 to n_ports);
45
46	-- signaux de controle
47	data_in_en : in std_logic_vector(n_ports downto 1);
48	cmd_in_en : in std_logic_vector(n_ports downto 1);
49	data_out_en : in std_logic_vector(n_ports downto 1);
50	fifo_in_full : out std_logic_vector(n_ports downto 1);
51	fifo_in_empty : out std_logic_vector(n_ports downto 1);
52	data_available : out std_logic_vector(n_ports downto 1);
53	clk : in STD_LOGIC;
54	reset : in STD_LOGIC);
55	end SWITCH_GEN;
56
57	architecture Behavioral of SWITCH_GEN is
58	-- declaration des modules du switch generique
59	-- le module de gestion des ports d'entrée
60
61	COMPONENT INPUT_PORT_MODULE
62	generic(number_of_ports : positive := 8;
63	Port_num: natural;
64	adr_mask : natural := NET_MASK;--le nombre de '1' en partant le la gauche de l'adresse
65	adr_len: positive:=NET_ADR'length; --la taille en bit de l'adresse 10 bits --> 1024 hotes
66	tot_ports: positive :=tot_ports; --Nomnre de ports total du réseau
67	adr_sub_net : std_logic_vector(9 downto 0) := NET_ADR;--l'adresse du sous-réseau
68	nbyte : positive:=2 -- le nombre de Byte dans chaque mot du port par défaut 2
69
70	);
71	Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
72	data_in_en : in STD_LOGIC;
73	cmd_in_en : in STD_LOGIC;
74	reset : in STD_LOGIC;
75	clk : in STD_LOGIC;
76	request : out STD_LOGIC_VECTOR (n_ports downto 1);
77	grant : in STD_LOGIC_VECTOR (n_ports downto 1);
78	fifo_full : out STD_LOGIC;
79	fifo_empty : out STD_LOGIC;
80	priority_rotation : out std_logic;
81	data_out : out STD_LOGIC_VECTOR (7 downto 0); -- le crossbar est fixé à 8 bits
82	data_out_pulse : out std_logic);
83	END COMPONENT;
84
85	-- le module des ports de sortie
86
87	COMPONENT OUTPUT_PORT_MODULE
88	PORT(
89	data_in : IN std_logic_vector(7 downto 0); -- le crossbar est fixé à 8 bits
90	reset : IN std_logic;
91	clk : IN std_logic;
92	wr_en : IN std_logic;
93	rd_out_en : IN std_logic;
94	data_out : OUT std_logic_vector(Word-1 downto 0);
95	fifo_full : OUT std_logic;
96	data_avalaible : OUT std_logic
97	);
98	END COMPONENT;
99
100	-- le module du crossbar
101	COMPONENT Crossbar
102	generic
103	(
104	number_of_crossbar_ports: positive := 4
105	);
106	Port (
107	clk : in STD_LOGIC;
108	reset : in STD_LOGIC;
109	Port1_in : in STD_LOGIC_VECTOR (7 downto 0);
110	Port2_in : in STD_LOGIC_VECTOR (7 downto 0);
111	Port3_in : in STD_LOGIC_VECTOR (7 downto 0);
112	Port4_in : in STD_LOGIC_VECTOR (7 downto 0);
113	Port5_in : in STD_LOGIC_VECTOR (7 downto 0);
114	Port6_in : in STD_LOGIC_VECTOR (7 downto 0);
115	Port7_in : in STD_LOGIC_VECTOR (7 downto 0);
116	Port8_in : in STD_LOGIC_VECTOR (7 downto 0);
117	Port9_in : in STD_LOGIC_VECTOR (7 downto 0);
118	Port10_in : in STD_LOGIC_VECTOR (7 downto 0);
119	Port11_in : in STD_LOGIC_VECTOR (7 downto 0);
120	Port12_in : in STD_LOGIC_VECTOR (7 downto 0);
121	Port13_in : in STD_LOGIC_VECTOR (7 downto 0);
122	Port14_in : in STD_LOGIC_VECTOR (7 downto 0);
123	Port15_in : in STD_LOGIC_VECTOR (7 downto 0);
124	Port16_in : in STD_LOGIC_VECTOR (7 downto 0);
125
126	--Port_pulse_in : in std_logic_vector(1 to number_of_ports);
127	Port1_pulse_in : in std_logic;
128	Port2_pulse_in : in std_logic;
129	Port3_pulse_in : in std_logic;
130	Port4_pulse_in : in std_logic;
131	Port5_pulse_in : in std_logic;
132	Port6_pulse_in : in std_logic;
133	Port7_pulse_in : in std_logic;
134	Port8_pulse_in : in std_logic;
135	Port9_pulse_in : in std_logic;
136	Port10_pulse_in : in std_logic;
137	Port11_pulse_in : in std_logic;
138	Port12_pulse_in : in std_logic;
139	Port13_pulse_in : in std_logic;
140	Port14_pulse_in : in std_logic;
141	Port15_pulse_in : in std_logic;
142	Port16_pulse_in : in std_logic;
143
144	--Port_pulse_out : in std_logic_vector(1 to number_of_ports);
145	Port1_pulse_out : out std_logic;
146	Port2_pulse_out : out std_logic;
147	Port3_pulse_out : out std_logic;
148	Port4_pulse_out : out std_logic;
149	Port5_pulse_out : out std_logic;
150	Port6_pulse_out : out std_logic;
151	Port7_pulse_out : out std_logic;
152	Port8_pulse_out : out std_logic;
153	Port9_pulse_out : out std_logic;
154	Port10_pulse_out : out std_logic;
155	Port11_pulse_out : out std_logic;
156	Port12_pulse_out : out std_logic;
157	Port13_pulse_out : out std_logic;
158	Port14_pulse_out : out std_logic;
159	Port15_pulse_out : out std_logic;
160	Port16_pulse_out : out std_logic;
161
162	--Port_out : out Typ_PortIO(1 to number_of_crossbar_ports);
163	Port1_out : out STD_LOGIC_VECTOR (7 downto 0);
164	Port2_out : out STD_LOGIC_VECTOR (7 downto 0);
165	Port3_out : out STD_LOGIC_VECTOR (7 downto 0);
166	Port4_out : out STD_LOGIC_VECTOR (7 downto 0);
167	Port5_out : out STD_LOGIC_VECTOR (7 downto 0);
168	Port6_out : out STD_LOGIC_VECTOR (7 downto 0);
169	Port7_out : out STD_LOGIC_VECTOR (7 downto 0);
170	Port8_out : out STD_LOGIC_VECTOR (7 downto 0);
171	Port9_out : out STD_LOGIC_VECTOR (7 downto 0);
172	Port10_out : out STD_LOGIC_VECTOR (7 downto 0);
173	Port11_out : out STD_LOGIC_VECTOR (7 downto 0);
174	Port12_out : out STD_LOGIC_VECTOR (7 downto 0);
175	Port13_out : out STD_LOGIC_VECTOR (7 downto 0);
176	Port14_out : out STD_LOGIC_VECTOR (7 downto 0);
177	Port15_out : out STD_LOGIC_VECTOR (7 downto 0);
178	Port16_out : out STD_LOGIC_VECTOR (7 downto 0);
179
180	Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
181	);
182	END COMPONENT;
183
184	-- déclaration du scheduler
185	COMPONENT Scheduler
186	generic(number_of_ports : positive := 4);
187	Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
188	Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
189	clk : in STD_LOGIC;
190	reset : in STD_LOGIC;
191	priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1);
192	port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
193	END COMPONENT;
194
195	--declaration des signaux de connection entre les modules du switch
196
197	Signal Request_signal : STD_LOGIC_VECTOR(n_ports*n_ports downto 1);
198	Signal grant_signal : STD_LOGIC_VECTOR(n_ports*n_ports downto 1);
199	Signal priority_rotation_signal : STD_LOGIC_VECTOR(n_ports downto 1);
200	signal fifo_out_full_signal : std_logic_vector(n_ports downto 1);
201
202	signal crossbar_in_port : Typ_PortIO8(1 to n_ports);
203
204
205
206	signal crossbar_out_port : Typ_PortIO8(1 to n_ports);
207
208
209	signal crossbar_in_pulse : std_logic_vector(n_ports downto 1);
210
211
212	signal crossbar_out_pulse : std_logic_vector(n_ports downto 1);
213
214
215
216	begin
217	-- intstanciation et connexion des modules du switch en fonction du nombre de ports
218	-- le circuit genere depend du parametre generique nombre de ports
219	-- switch 2 ports
220	switch2x2 : if n_ports = 2 generate
221
222	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
223	GENERIC MAP(number_of_ports =>2,Port_num=>1,
224	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
225	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
226	tot_ports=>tot_ports, --Nomnre de ports total du réseau
227	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
228	nbyte =>WORD/8)
229	PORT MAP(
230	data_in => Port_in(1),
231	data_in_en => data_in_en(1),
232	cmd_in_en => cmd_in_en(1),
233	reset => reset,
234	clk =>clk,
235	grant(1) => grant_signal(1),
236	grant(2) => grant_signal(2),
237	fifo_full =>fifo_in_full(1),
238	priority_rotation => priority_rotation_signal(1),
239	fifo_empty => fifo_in_empty(1),
240	data_out =>crossbar_in_port(1),
241	data_out_pulse =>crossbar_in_pulse(1),
242	request(1) =>request_signal(1),
243	request(2) =>request_signal(2)
244	);
245
246	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
247	GENERIC MAP(number_of_ports =>2,Port_num=>2,
248	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
249	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
250	tot_ports=>tot_ports, --Nomnre de ports total du réseau
251	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
252	nbyte =>WORD/8)
253	PORT MAP(
254	data_in => Port_in(2),
255	data_in_en => data_in_en(2),
256	cmd_in_en => cmd_in_en(2),
257	reset => reset,
258	clk =>clk,
259	grant(1) => grant_signal(3),
260	grant(2) => grant_signal(4),
261	fifo_full =>fifo_in_full(2),
262	priority_rotation => priority_rotation_signal(2),
263	fifo_empty => fifo_in_empty(2),
264	data_out =>crossbar_in_port(2),
265	data_out_pulse =>crossbar_in_pulse(2),
266	request(1) =>request_signal(3),
267	request(2) =>request_signal(4)
268	);
269
270	end generate switch2x2;
271
272
273	-- switch 3 ports
274	switch3x3 : if n_ports = 3 generate
275
276	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
277	GENERIC MAP(number_of_ports =>3,Port_num=>1,
278	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
279	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
280	tot_ports=>tot_ports, --Nomnre de ports total du réseau
281	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
282	nbyte =>WORD/8)
283	PORT MAP(
284	data_in => Port_in(1),
285	data_in_en => data_in_en(1),
286	cmd_in_en => cmd_in_en(1),
287	reset => reset,
288	clk =>clk,
289	grant(1) => grant_signal(1),
290	grant(2) => grant_signal(2),
291	grant(3) => grant_signal(3),
292	fifo_full =>fifo_in_full(1),
293	priority_rotation => priority_rotation_signal(1),
294	fifo_empty => fifo_in_empty(1),
295	data_out =>crossbar_in_port(1),
296	data_out_pulse =>crossbar_in_pulse(1),
297	request(1) =>request_signal(1),
298	request(2) =>request_signal(2),
299	request(3) =>request_signal(3)
300	);
301
302	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
303	GENERIC MAP(number_of_ports =>3,Port_num=>2,
304	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
305	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
306	tot_ports=>tot_ports, --Nomnre de ports total du réseau
307	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
308	nbyte =>WORD/8)
309	PORT MAP(
310	data_in => Port_in(2),
311	data_in_en => data_in_en(2),
312	cmd_in_en => cmd_in_en(2),
313	reset => reset,
314	clk =>clk,
315	grant(1) => grant_signal(4),
316	grant(2) => grant_signal(5),
317	grant(3) => grant_signal(6),
318	fifo_full =>fifo_in_full(2),
319	priority_rotation => priority_rotation_signal(2),
320	fifo_empty => fifo_in_empty(2),
321	data_out =>crossbar_in_port(2),
322	data_out_pulse =>crossbar_in_pulse(2),
323	request(1) =>request_signal(4),
324	request(2) =>request_signal(5),
325	request(3) =>request_signal(6)
326	);
327
328	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
329	GENERIC MAP(number_of_ports =>3,Port_num=>3,
330	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
331	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
332	tot_ports=>tot_ports, --Nomnre de ports total du réseau
333	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
334	nbyte =>WORD/8)
335	PORT MAP(
336	data_in => Port_in(3),
337	data_in_en => data_in_en(3),
338	cmd_in_en => cmd_in_en(3),
339	reset => reset,
340	clk =>clk,
341	grant(1) => grant_signal(7),
342	grant(2) => grant_signal(8),
343	grant(3) => grant_signal(9),
344	fifo_full =>fifo_in_full(3),
345	priority_rotation => priority_rotation_signal(3),
346	fifo_empty => fifo_in_empty(3),
347	data_out =>crossbar_in_port(3),
348	data_out_pulse =>crossbar_in_pulse(3),
349	request(1) =>request_signal(7),
350	request(2) =>request_signal(8),
351	request(3) =>request_signal(9)
352	);
353
354	end generate switch3x3;
355
356
357	-- switch 4 à 7 ports
358	switch4x4_7x7 : if n_ports >= 4 and n_ports <=7 generate
359
360	switch_4x4_7x7:for i in 1 to n_ports generate
361
362	constant j: natural:=n_ports*(i-1);
363	begin
364	--j=n_ports*(i-1);
365	PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
366	GENERIC MAP(number_of_ports =>n_ports,Port_num=>i,
367	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
368	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
369	tot_ports=>tot_ports, --Nomnre de ports total du réseau
370	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
371	nbyte =>WORD/8)
372	PORT MAP(
373	data_in => Port_in(i),
374	data_in_en => data_in_en(i),
375	cmd_in_en => cmd_in_en(i),
376	reset => reset,
377	clk =>clk,
378	grant =>grant_signal(j+n_ports downto j+1),
379
380	fifo_full =>fifo_in_full(i),
381	priority_rotation => priority_rotation_signal(i),
382	fifo_empty => fifo_in_empty(i),
383	data_out =>crossbar_in_port(i),
384	data_out_pulse =>crossbar_in_pulse(i),
385	request =>request_signal(j+n_ports downto j+1)
386
387	);
388	end generate switch_4x4_7x7;
389	end generate switch4x4_7x7;
390
391
392	---- switch 5 ports
393	--switch5x5 : if n_ports = 5 generate
394	--
395	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
396	--GENERIC MAP(n_ports =>5)
397	--PORT MAP(
398	-- data_in => Port_in(1),
399	-- data_in_en => data_in_en(1),
400	-- reset => reset,
401	-- clk =>clk,
402	-- grant(1) => grant_signal(1),
403	-- grant(2) => grant_signal(2),
404	-- grant(3) => grant_signal(3),
405	-- grant(4) => grant_signal(4),
406	-- grant(5) => grant_signal(5),
407	-- fifo_full =>fifo_in_full(1),
408	-- priority_rotation => priority_rotation_signal(1),
409	-- fifo_empty => fifo_in_empty(1),
410	-- data_out =>crossbar_in_port(1),
411	-- data_out_pulse =>crossbar_in_pulse(1),
412	-- request(1) =>request_signal(1),
413	-- request(2) =>request_signal(2),
414	-- request(3) =>request_signal(3),
415	-- request(4) =>request_signal(4),
416	-- request(5) =>request_signal(5)
417	--);
418	--
419	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
420	--GENERIC MAP(n_ports =>5)
421	--PORT MAP(
422	-- data_in => Port_in(2),
423	-- data_in_en => data_in_en(2),
424	-- reset => reset,
425	-- clk =>clk,
426	-- grant(1) => grant_signal(6),
427	-- grant(2) => grant_signal(7),
428	-- grant(3) => grant_signal(8),
429	-- grant(4) => grant_signal(9),
430	-- grant(5) => grant_signal(10),
431	-- fifo_full =>fifo_in_full(2),
432	-- priority_rotation => priority_rotation_signal(2),
433	-- fifo_empty => fifo_in_empty(2),
434	-- data_out =>crossbar_in_port(2),
435	-- data_out_pulse =>crossbar_in_pulse(2),
436	-- request(6) =>request_signal(6),
437	-- request(7) =>request_signal(7),
438	-- request(8) =>request_signal(8),
439	-- request(9) =>request_signal(9),
440	-- request(10) =>request_signal(10)
441	--);
442	--
443	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
444	--GENERIC MAP(n_ports =>5)
445	--PORT MAP(
446	-- data_in => Port_in(3),
447	-- data_in_en => data_in_en(3),
448	-- reset => reset,
449	-- clk =>clk,
450	-- grant(11) => grant_signal(11),
451	-- grant(12) => grant_signal(12),
452	-- grant(13) => grant_signal(13),
453	-- grant(14) => grant_signal(14),
454	-- grant(15) => grant_signal(15),
455	-- fifo_full =>fifo_in_full(3),
456	-- priority_rotation => priority_rotation_signal(3),
457	-- fifo_empty => fifo_in_empty(3),
458	-- data_out =>crossbar_in_port(3),
459	-- data_out_pulse =>crossbar_in_pulse(3),
460	-- request(11) =>request_signal(11),
461	-- request(12) =>request_signal(12),
462	-- request(13) =>request_signal(13),
463	-- request(14) =>request_signal(14),
464	-- request(15) =>request_signal(15)
465	--);
466	--
467	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
468	--GENERIC MAP(n_ports =>5)
469	--PORT MAP(
470	-- data_in => Port_in(4),
471	-- data_in_en => data_in_en(4),
472	-- reset => reset,
473	-- clk =>clk,
474	-- grant(16) => grant_signal(16),
475	-- grant(17) => grant_signal(17),
476	-- grant(18) => grant_signal(18),
477	-- grant(19) => grant_signal(19),
478	-- grant(20) => grant_signal(20),
479	-- fifo_full =>fifo_in_full(4),
480	-- priority_rotation => priority_rotation_signal(4),
481	-- fifo_empty => fifo_in_empty(4),
482	-- data_out =>crossbar_in_port(4),
483	-- data_out_pulse =>crossbar_in_pulse(4),
484	-- request(16) =>request_signal(16),
485	-- request(17) =>request_signal(17),
486	-- request(18) =>request_signal(18),
487	-- request(19) =>request_signal(19),
488	-- request(20) =>request_signal(20)
489	--);
490	--
491	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
492	--GENERIC MAP(n_ports =>5)
493	--PORT MAP(
494	-- data_in => Port_in(5),
495	-- data_in_en => data_in_en(5),
496	-- reset => reset,
497	-- clk =>clk,
498	-- grant(21) => grant_signal(21),
499	-- grant(22) => grant_signal(22),
500	-- grant(23) => grant_signal(23),
501	-- grant(24) => grant_signal(24),
502	-- grant(25) => grant_signal(25),
503	-- fifo_full =>fifo_in_full(5),
504	-- priority_rotation => priority_rotation_signal(5),
505	-- fifo_empty => fifo_in_empty(5),
506	-- data_out =>crossbar_in_port(5),
507	-- data_out_pulse =>crossbar_in_pulse(5),
508	-- request(21) =>request_signal(21),
509	-- request(22) =>request_signal(22),
510	-- request(23) =>request_signal(23),
511	-- request(24) =>request_signal(24),
512	-- request(25) =>request_signal(25)
513	--);
514	--
515	--end generate switch5x5;
516	--
517	--
518	---- switch 6 ports
519	--switch6x6 : if n_ports = 6 generate
520	--
521	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
522	--GENERIC MAP(n_ports =>6)
523	--PORT MAP(
524	-- data_in => Port_in(1),
525	-- data_in_en => data_in_en(1),
526	-- cmd_in_en => cmd_in_en(1),
527	-- reset => reset,
528	-- clk =>clk,
529	-- grant(1) => grant_signal(1),
530	-- grant(2) => grant_signal(2),
531	-- grant(3) => grant_signal(3),
532	-- grant(4) => grant_signal(4),
533	-- grant(5) => grant_signal(5),
534	-- grant(6) => grant_signal(6),
535	-- fifo_full =>fifo_in_full(1),
536	-- priority_rotation => priority_rotation_signal(1),
537	-- fifo_empty => fifo_in_empty(1),
538	-- data_out =>crossbar_in_port(1),
539	-- data_out_pulse =>crossbar_in_pulse(1),
540	-- request(1) =>request_signal(1),
541	-- request(2) =>request_signal(2),
542	-- request(3) =>request_signal(3),
543	-- request(4) =>request_signal(4),
544	-- request(5) =>request_signal(5),
545	-- request(6) =>request_signal(6)
546	--);
547	--
548	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
549	--GENERIC MAP(number_of_ports =>6)
550	--PORT MAP(
551	-- data_in => Port_in(2),
552	-- data_in_en => data_in_en(2),
553	-- reset => reset,
554	-- clk =>clk,
555	-- grant(1) => grant_signal(7),
556	-- grant(2) => grant_signal(8),
557	-- grant(3) => grant_signal(9),
558	-- grant(4) => grant_signal(10),
559	-- grant(5) => grant_signal(11),
560	-- grant(6) => grant_signal(12),
561	-- fifo_full =>fifo_in_full(2),
562	-- priority_rotation => priority_rotation_signal(2),
563	-- fifo_empty => fifo_in_empty(2),
564	-- data_out =>crossbar_in_port(2),
565	-- data_out_pulse =>crossbar_in_pulse(2),
566	-- request(1) =>request_signal(7),
567	-- request(2) =>request_signal(8),
568	-- request(3) =>request_signal(9),
569	-- request(4) =>request_signal(10),
570	-- request(5) =>request_signal(11),
571	-- request(6) =>request_signal(12)
572	--);
573	--
574	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
575	--GENERIC MAP(number_of_ports =>6)
576	--PORT MAP(
577	-- data_in => Port_in(3),
578	-- data_in_en => data_in_en(3),
579	-- reset => reset,
580	-- clk =>clk,
581	-- grant(13) => grant_signal(13),
582	-- grant(14) => grant_signal(14),
583	-- grant(15) => grant_signal(15),
584	-- grant(16) => grant_signal(16),
585	-- grant(17) => grant_signal(17),
586	-- grant(18) => grant_signal(18),
587	-- fifo_full =>fifo_in_full(3),
588	-- priority_rotation => priority_rotation_signal(3),
589	-- fifo_empty => fifo_in_empty(3),
590	-- data_out =>crossbar_in_port(3),
591	-- data_out_pulse =>crossbar_in_pulse(3),
592	-- request(13) =>request_signal(13),
593	-- request(14) =>request_signal(14),
594	-- request(15) =>request_signal(15),
595	-- request(16) =>request_signal(16),
596	-- request(17) =>request_signal(17),
597	-- request(18) =>request_signal(18)
598	--);
599	--
600	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
601	--GENERIC MAP(number_of_ports =>6)
602	--PORT MAP(
603	-- data_in => Port_in(4),
604	-- data_in_en => data_in_en(4),
605	-- cmd_in_en => cmd_in_en(4),
606	-- reset => reset,
607	-- clk =>clk,
608	-- grant(19) => grant_signal(19),
609	-- grant(20) => grant_signal(20),
610	-- grant(21) => grant_signal(21),
611	-- grant(22) => grant_signal(22),
612	-- grant(23) => grant_signal(23),
613	-- grant(24) => grant_signal(24),
614	-- fifo_full =>fifo_in_full(4),
615	-- priority_rotation => priority_rotation_signal(4),
616	-- fifo_empty => fifo_in_empty(4),
617	-- data_out =>crossbar_in_port(4),
618	-- data_out_pulse =>crossbar_in_pulse(4),
619	-- request(19) =>request_signal(19),
620	-- request(20) =>request_signal(20),
621	-- request(21) =>request_signal(21),
622	-- request(22) =>request_signal(22),
623	-- request(23) =>request_signal(23),
624	-- request(24) =>request_signal(24)
625	--);
626	--
627	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
628	--GENERIC MAP(number_of_ports =>6)
629	--PORT MAP(
630	-- data_in => Port_in(5),
631	-- data_in_en => data_in_en(5),
632	-- cmd_in_en => cmd_in_en(5),
633	-- reset => reset,
634	-- clk =>clk,
635	-- grant(25) => grant_signal(25),
636	-- grant(26) => grant_signal(26),
637	-- grant(27) => grant_signal(27),
638	-- grant(28) => grant_signal(28),
639	-- grant(29) => grant_signal(29),
640	-- grant(30) => grant_signal(30),
641	-- fifo_full =>fifo_in_full(5),
642	-- priority_rotation => priority_rotation_signal(5),
643	-- fifo_empty => fifo_in_empty(5),
644	-- data_out =>crossbar_in_port(5),
645	-- data_out_pulse =>crossbar_in_pulse(5),
646	-- request(25) =>request_signal(25),
647	-- request(26) =>request_signal(26),
648	-- request(27) =>request_signal(27),
649	-- request(28) =>request_signal(28),
650	-- request(29) =>request_signal(29),
651	-- request(30) =>request_signal(30)
652	--);
653	--
654	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
655	--GENERIC MAP(number_of_ports =>6)
656	--PORT MAP(
657	-- data_in => Port_in(6),
658	-- data_in_en => data_in_en(6),
659	-- reset => reset,
660	-- clk =>clk,
661	-- grant(31) => grant_signal(31),
662	-- grant(32) => grant_signal(32),
663	-- grant(33) => grant_signal(33),
664	-- grant(34) => grant_signal(34),
665	-- grant(35) => grant_signal(35),
666	-- grant(36) => grant_signal(36),
667	-- fifo_full =>fifo_in_full(6),
668	-- priority_rotation => priority_rotation_signal(6),
669	-- fifo_empty => fifo_in_empty(6),
670	-- data_out =>crossbar_in_port(6),
671	-- data_out_pulse =>crossbar_in_pulse(6),
672	-- request(31) =>request_signal(31),
673	-- request(32) =>request_signal(32),
674	-- request(33) =>request_signal(33),
675	-- request(34) =>request_signal(34),
676	-- request(35) =>request_signal(35),
677	-- request(36) =>request_signal(36)
678	--);
679	--
680	--end generate switch6x6;
681	--
682	--
683	---- switch 7 ports
684	--switch7x7 : if number_of_ports = 7 generate
685	--
686	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
687	--GENERIC MAP(number_of_ports =>7)
688	--PORT MAP(
689	-- data_in => Port_in(1),
690	-- data_in_en => data_in_en(1),
691	-- cmd_in_en => cmd_in_en(1),
692	-- reset => reset,
693	-- clk =>clk,
694	-- grant(1) => grant_signal(1),
695	-- grant(2) => grant_signal(2),
696	-- grant(3) => grant_signal(3),
697	-- grant(4) => grant_signal(4),
698	-- grant(5) => grant_signal(5),
699	-- grant(6) => grant_signal(6),
700	-- grant(7) => grant_signal(7),
701	-- fifo_full =>fifo_in_full(1),
702	-- priority_rotation => priority_rotation_signal(1),
703	-- fifo_empty => fifo_in_empty(1),
704	-- data_out =>crossbar_in_port(1),
705	-- data_out_pulse =>crossbar_in_pulse(1),
706	-- request(1) =>request_signal(1),
707	-- request(2) =>request_signal(2),
708	-- request(3) =>request_signal(3),
709	-- request(4) =>request_signal(4),
710	-- request(5) =>request_signal(5),
711	-- request(6) =>request_signal(6),
712	-- request(7) =>request_signal(7)
713	--);
714	--
715	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
716	--GENERIC MAP(number_of_ports =>7)
717	--PORT MAP(
718	-- data_in => Port_in(2),
719	-- data_in_en => data_in_en(2),
720	-- reset => reset,
721	-- clk =>clk,
722	-- grant(1) => grant_signal(8),
723	-- grant(2) => grant_signal(9),
724	-- grant(3) => grant_signal(10),
725	-- grant(4) => grant_signal(11),
726	-- grant(5) => grant_signal(12),
727	-- grant(6) => grant_signal(13),
728	-- grant(7) => grant_signal(14),
729	-- fifo_full =>fifo_in_full(2),
730	-- priority_rotation => priority_rotation_signal(2),
731	-- fifo_empty => fifo_in_empty(2),
732	-- data_out =>crossbar_in_port(2),
733	-- data_out_pulse =>crossbar_in_pulse(2),
734	-- request(8) =>request_signal(8),
735	-- request(9) =>request_signal(9),
736	-- request(10) =>request_signal(10),
737	-- request(11) =>request_signal(11),
738	-- request(12) =>request_signal(12),
739	-- request(13) =>request_signal(13),
740	-- request(14) =>request_signal(14)
741	--);
742	--
743	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
744	--GENERIC MAP(number_of_ports =>7)
745	--PORT MAP(
746	-- data_in => Port_in(3),
747	-- data_in_en => data_in_en(3),
748	-- reset => reset,
749	-- clk =>clk,
750	-- grant(15) => grant_signal(15),
751	-- grant(16) => grant_signal(16),
752	-- grant(17) => grant_signal(17),
753	-- grant(18) => grant_signal(18),
754	-- grant(19) => grant_signal(19),
755	-- grant(20) => grant_signal(20),
756	-- grant(21) => grant_signal(21),
757	-- fifo_full =>fifo_in_full(3),
758	-- priority_rotation => priority_rotation_signal(3),
759	-- fifo_empty => fifo_in_empty(3),
760	-- data_out =>crossbar_in_port(3),
761	-- data_out_pulse =>crossbar_in_pulse(3),
762	-- request(15) =>request_signal(15),
763	-- request(16) =>request_signal(16),
764	-- request(17) =>request_signal(17),
765	-- request(18) =>request_signal(18),
766	-- request(19) =>request_signal(19),
767	-- request(20) =>request_signal(20),
768	-- request(21) =>request_signal(21)
769	--);
770	--
771	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
772	--GENERIC MAP(number_of_ports =>7)
773	--PORT MAP(
774	-- data_in => Port_in(4),
775	-- data_in_en => data_in_en(4),
776	-- reset => reset,
777	-- clk =>clk,
778	-- grant(22) => grant_signal(22),
779	-- grant(23) => grant_signal(23),
780	-- grant(24) => grant_signal(24),
781	-- grant(25) => grant_signal(25),
782	-- grant(26) => grant_signal(26),
783	-- grant(27) => grant_signal(27),
784	-- grant(28) => grant_signal(28),
785	-- fifo_full =>fifo_in_full(4),
786	-- priority_rotation => priority_rotation_signal(4),
787	-- fifo_empty => fifo_in_empty(4),
788	-- data_out =>crossbar_in_port(4),
789	-- data_out_pulse =>crossbar_in_pulse(4),
790	-- request(22) =>request_signal(22),
791	-- request(23) =>request_signal(23),
792	-- request(24) =>request_signal(24),
793	-- request(25) =>request_signal(25),
794	-- request(26) =>request_signal(26),
795	-- request(27) =>request_signal(27),
796	-- request(28) =>request_signal(28)
797	--);
798	--
799	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
800	--GENERIC MAP(number_of_ports =>7)
801	--PORT MAP(
802	-- data_in => Port_in(5),
803	-- data_in_en => data_in_en(5),
804	-- reset => reset,
805	-- clk =>clk,
806	-- grant(29) => grant_signal(29),
807	-- grant(30) => grant_signal(30),
808	-- grant(31) => grant_signal(31),
809	-- grant(32) => grant_signal(32),
810	-- grant(33) => grant_signal(33),
811	-- grant(34) => grant_signal(34),
812	-- grant(35) => grant_signal(35),
813	-- fifo_full =>fifo_in_full(5),
814	-- priority_rotation => priority_rotation_signal(5),
815	-- fifo_empty => fifo_in_empty(5),
816	-- data_out =>crossbar_in_port(5),
817	-- data_out_pulse =>crossbar_in_pulse(5),
818	-- request(29) =>request_signal(29),
819	-- request(30) =>request_signal(30),
820	-- request(31) =>request_signal(31),
821	-- request(32) =>request_signal(32),
822	-- request(33) =>request_signal(33),
823	-- request(34) =>request_signal(34),
824	-- request(35) =>request_signal(35)
825	--);
826	--
827	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
828	--GENERIC MAP(number_of_ports =>7)
829	--PORT MAP(
830	-- data_in => Port_in(6),
831	-- data_in_en => data_in_en(6),
832	-- reset => reset,
833	-- clk =>clk,
834	-- grant(36) => grant_signal(36),
835	-- grant(37) => grant_signal(37),
836	-- grant(38) => grant_signal(38),
837	-- grant(39) => grant_signal(39),
838	-- grant(40) => grant_signal(40),
839	-- grant(41) => grant_signal(41),
840	-- grant(42) => grant_signal(42),
841	-- fifo_full =>fifo_in_full(6),
842	-- priority_rotation => priority_rotation_signal(6),
843	-- fifo_empty => fifo_in_empty(6),
844	-- data_out =>crossbar_in_port(6),
845	-- data_out_pulse =>crossbar_in_pulse(6),
846	-- request(36) =>request_signal(36),
847	-- request(37) =>request_signal(37),
848	-- request(38) =>request_signal(38),
849	-- request(39) =>request_signal(39),
850	-- request(40) =>request_signal(40),
851	-- request(41) =>request_signal(41),
852	-- request(42) =>request_signal(42)
853	--);
854	--
855	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
856	--GENERIC MAP(number_of_ports =>7)
857	--PORT MAP(
858	-- data_in => Port_in(7),
859	-- data_in_en => data_in_en(7),
860	-- reset => reset,
861	-- clk =>clk,
862	-- grant(43) => grant_signal(43),
863	-- grant(44) => grant_signal(44),
864	-- grant(45) => grant_signal(45),
865	-- grant(46) => grant_signal(46),
866	-- grant(47) => grant_signal(47),
867	-- grant(48) => grant_signal(48),
868	-- grant(49) => grant_signal(49),
869	-- fifo_full =>fifo_in_full(7),
870	-- priority_rotation => priority_rotation_signal(7),
871	-- fifo_empty => fifo_in_empty(7),
872	-- data_out =>crossbar_in_port(8),
873	-- data_out_pulse =>crossbar_in_pulse(7),
874	-- request(43) =>request_signal(43),
875	-- request(44) =>request_signal(44),
876	-- request(45) =>request_signal(45),
877	-- request(46) =>request_signal(46),
878	-- request(47) =>request_signal(47),
879	-- request(48) =>request_signal(48),
880	-- request(49) =>request_signal(49)
881	--);
882	--
883	--end generate switch7x7;
884
885
886	-- switch 8 ports
887	switch8x8 : if n_ports = 8 generate
888	switch_8x8:for i in 1 to n_ports generate
889	constant j: natural:=n_ports*(i-1);
890	begin
891	--j<=number_of_ports*(i-1);
892	PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
893	GENERIC MAP(number_of_ports =>8,Port_num=>i,
894	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
895	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
896	tot_ports=>tot_ports, --Nomnre de ports total du réseau
897	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
898	nbyte =>WORD/8)
899	PORT MAP(
900	data_in => Port_in(i),
901	data_in_en => data_in_en(i),
902	cmd_in_en => cmd_in_en(i),
903	reset => reset,
904	clk =>clk,
905	grant =>grant_signal(j+n_ports downto j+1),
906	fifo_full =>fifo_in_full(i),
907	priority_rotation => priority_rotation_signal(i),
908	fifo_empty => fifo_in_empty(i),
909	data_out =>crossbar_in_port(i),
910	data_out_pulse =>crossbar_in_pulse(i),
911
912	request =>request_signal(j+n_ports downto j+1)
913	);
914	end generate switch_8x8;
915	end generate switch8x8;
916
917	-- switch 9 ports
918	switch9x9_to_15 : if (n_ports >= 9)and (n_ports <= 15) generate
919
920	switch_9x9_to_15:for i in 1 to n_ports generate
921
922	constant j: natural:=n_ports*(i-1);
923	begin
924
925	PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
926	GENERIC MAP(number_of_ports =>n_ports,Port_num=>i,
927	adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
928	adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
929	tot_ports=>tot_ports, --Nomnre de ports total du réseau
930	adr_sub_net => NET_ADR,--l'adresse du sous-réseau
931	nbyte =>WORD/8)
932	PORT MAP(
933	data_in => Port_in(i),
934	data_in_en => data_in_en(i),
935	cmd_in_en => cmd_in_en(i),
936	reset => reset,
937	clk =>clk,
938	grant => grant_signal(j+n_ports downto j+1),
939	fifo_full =>fifo_in_full(i),
940	priority_rotation => priority_rotation_signal(i),
941	fifo_empty => fifo_in_empty(i),
942	data_out =>crossbar_in_port(i),
943	data_out_pulse =>crossbar_in_pulse(i),
944
945	request =>request_signal(j+n_ports downto j+1)
946	);
947	end generate switch_9x9_to_15;
948	end generate switch9x9_to_15;
949
950
951
952	-- switch 10 ports
953	--switch10x10 : if number_of_ports = 10 generate
954	--
955	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
956	--GENERIC MAP(number_of_ports =>10)
957	--PORT MAP(
958	-- data_in => Port_in(1),
959	-- data_in_en => data_in_en(1),
960	-- reset => reset,
961	-- clk =>clk,
962	-- grant(1) => grant_signal(1),
963	-- grant(2) => grant_signal(2),
964	-- grant(3) => grant_signal(3),
965	-- grant(4) => grant_signal(4),
966	-- grant(5) => grant_signal(5),
967	-- grant(6) => grant_signal(6),
968	-- grant(7) => grant_signal(7),
969	-- grant(8) => grant_signal(8),
970	-- grant(9) => grant_signal(9),
971	-- grant(10) => grant_signal(10),
972	-- fifo_full =>fifo_in_full(1),
973	-- priority_rotation => priority_rotation_signal(1),
974	-- fifo_empty => fifo_in_empty(1),
975	-- data_out =>crossbar_in_port(1),
976	-- data_out_pulse =>crossbar_in_pulse(1),
977	-- request(1) =>request_signal(1),
978	-- request(2) =>request_signal(2),
979	-- request(3) =>request_signal(3),
980	-- request(4) =>request_signal(4),
981	-- request(5) =>request_signal(5),
982	-- request(6) =>request_signal(6),
983	-- request(7) =>request_signal(7),
984	-- request(8) =>request_signal(8),
985	-- request(9) =>request_signal(9),
986	-- request(10) =>request_signal(10)
987	--);
988	--
989	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
990	--GENERIC MAP(number_of_ports =>10)
991	--PORT MAP(
992	-- data_in => Port_in(2),
993	-- data_in_en => data_in_en(2),
994	-- reset => reset,
995	-- clk =>clk,
996	-- grant(1) => grant_signal(11),
997	-- grant(2) => grant_signal(12),
998	-- grant(3) => grant_signal(13),
999	-- grant(4) => grant_signal(14),
1000	-- grant(5) => grant_signal(15),
1001	-- grant(6) => grant_signal(16),
1002	-- grant(7) => grant_signal(17),
1003	-- grant(8) => grant_signal(18),
1004	-- grant(9) => grant_signal(19),
1005	-- grant(10) => grant_signal(20),
1006	-- fifo_full =>fifo_in_full(2),
1007	-- priority_rotation => priority_rotation_signal(2),
1008	-- fifo_empty => fifo_in_empty(2),
1009	-- data_out =>crossbar_in_port(2),
1010	-- data_out_pulse =>crossbar_in_pulse(2),
1011	-- request(1) =>request_signal(11),
1012	-- request(2) =>request_signal(12),
1013	-- request(3) =>request_signal(13),
1014	-- request(4) =>request_signal(14),
1015	-- request(5) =>request_signal(15),
1016	-- request(6) =>request_signal(16),
1017	-- request(7) =>request_signal(17),
1018	-- request(8) =>request_signal(18),
1019	-- request(9) =>request_signal(19),
1020	-- request(10) =>request_signal(20)
1021	--);
1022	--
1023	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1024	--GENERIC MAP(number_of_ports =>10)
1025	--PORT MAP(
1026	-- data_in => Port_in(3),
1027	-- data_in_en => data_in_en(3),
1028	-- reset => reset,
1029	-- clk =>clk,
1030	-- grant(1) => grant_signal(21),
1031	-- grant(2) => grant_signal(22),
1032	-- grant(3) => grant_signal(23),
1033	-- grant(4) => grant_signal(24),
1034	-- grant(5) => grant_signal(25),
1035	-- grant(6) => grant_signal(26),
1036	-- grant(7) => grant_signal(27),
1037	-- grant(8) => grant_signal(28),
1038	-- grant(9) => grant_signal(29),
1039	-- grant(10) => grant_signal(30),
1040	-- fifo_full =>fifo_in_full(3),
1041	-- priority_rotation => priority_rotation_signal(3),
1042	-- fifo_empty => fifo_in_empty(3),
1043	-- data_out =>crossbar_in_port(3),
1044	-- data_out_pulse =>crossbar_in_pulse(3),
1045	-- request(1) =>request_signal(21),
1046	-- request(2) =>request_signal(22),
1047	-- request(3) =>request_signal(23),
1048	-- request(4) =>request_signal(24),
1049	-- request(5) =>request_signal(25),
1050	-- request(6) =>request_signal(26),
1051	-- request(7) =>request_signal(27),
1052	-- request(8) =>request_signal(28),
1053	-- request(9) =>request_signal(29),
1054	-- request(10) =>request_signal(30)
1055	--);
1056	--
1057	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1058	--GENERIC MAP(number_of_ports =>10)
1059	--PORT MAP(
1060	-- data_in => Port_in(4),
1061	-- data_in_en => data_in_en(4),
1062	-- reset => reset,
1063	-- clk =>clk,
1064	-- grant(1) => grant_signal(31),
1065	-- grant(2) => grant_signal(32),
1066	-- grant(3) => grant_signal(33),
1067	-- grant(4) => grant_signal(34),
1068	-- grant(5) => grant_signal(35),
1069	-- grant(6) => grant_signal(36),
1070	-- grant(7) => grant_signal(37),
1071	-- grant(8) => grant_signal(38),
1072	-- grant(9) => grant_signal(39),
1073	-- grant(10) => grant_signal(40),
1074	-- fifo_full =>fifo_in_full(4),
1075	-- priority_rotation => priority_rotation_signal(4),
1076	-- fifo_empty => fifo_in_empty(4),
1077	-- data_out =>crossbar_in_port(4),
1078	-- data_out_pulse =>crossbar_in_pulse(4),
1079	-- request(1) =>request_signal(31),
1080	-- request(2) =>request_signal(32),
1081	-- request(3) =>request_signal(33),
1082	-- request(4) =>request_signal(34),
1083	-- request(5) =>request_signal(35),
1084	-- request(6) =>request_signal(36),
1085	-- request(7) =>request_signal(37),
1086	-- request(8) =>request_signal(38),
1087	-- request(9) =>request_signal(39),
1088	-- request(10) =>request_signal(40)
1089	--);
1090	--
1091	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1092	--GENERIC MAP(number_of_ports =>10)
1093	--PORT MAP(
1094	-- data_in => Port_in(5),
1095	-- data_in_en => data_in_en(5),
1096	-- reset => reset,
1097	-- clk =>clk,
1098	-- grant(1) => grant_signal(41),
1099	-- grant(2) => grant_signal(42),
1100	-- grant(3) => grant_signal(43),
1101	-- grant(4) => grant_signal(44),
1102	-- grant(5) => grant_signal(45),
1103	-- grant(6) => grant_signal(46),
1104	-- grant(7) => grant_signal(47),
1105	-- grant(8) => grant_signal(48),
1106	-- grant(9) => grant_signal(49),
1107	-- grant(10) => grant_signal(50),
1108	-- fifo_full =>fifo_in_full(5),
1109	-- priority_rotation => priority_rotation_signal(5),
1110	-- fifo_empty => fifo_in_empty(5),
1111	-- data_out =>crossbar_in_port(5),
1112	-- data_out_pulse =>crossbar_in_pulse(5),
1113	-- request(1) =>request_signal(41),
1114	-- request(2) =>request_signal(42),
1115	-- request(3) =>request_signal(43),
1116	-- request(4) =>request_signal(44),
1117	-- request(5) =>request_signal(45),
1118	-- request(6) =>request_signal(46),
1119	-- request(7) =>request_signal(47),
1120	-- request(8) =>request_signal(48),
1121	-- request(9) =>request_signal(49),
1122	-- request(10) =>request_signal(50)
1123	--);
1124	--
1125	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1126	--GENERIC MAP(number_of_ports =>10)
1127	--PORT MAP(
1128	-- data_in => Port_in(6),
1129	-- data_in_en => data_in_en(6),
1130	-- reset => reset,
1131	-- clk =>clk,
1132	-- grant(1) => grant_signal(51),
1133	-- grant(2) => grant_signal(52),
1134	-- grant(3) => grant_signal(53),
1135	-- grant(4) => grant_signal(54),
1136	-- grant(5) => grant_signal(55),
1137	-- grant(6) => grant_signal(56),
1138	-- grant(7) => grant_signal(57),
1139	-- grant(8) => grant_signal(58),
1140	-- grant(9) => grant_signal(59),
1141	-- grant(10) => grant_signal(60),
1142	-- fifo_full =>fifo_in_full(6),
1143	-- priority_rotation => priority_rotation_signal(6),
1144	-- fifo_empty => fifo_in_empty(6),
1145	-- data_out =>crossbar_in_port(6),
1146	-- data_out_pulse =>crossbar_in_pulse(6),
1147	-- request(1) =>request_signal(51),
1148	-- request(2) =>request_signal(52),
1149	-- request(3) =>request_signal(53),
1150	-- request(4) =>request_signal(54),
1151	-- request(5) =>request_signal(55),
1152	-- request(6) =>request_signal(56),
1153	-- request(7) =>request_signal(57),
1154	-- request(8) =>request_signal(58),
1155	-- request(9) =>request_signal(59),
1156	-- request(10) =>request_signal(60)
1157	--);
1158	--
1159	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1160	--GENERIC MAP(number_of_ports =>10)
1161	--PORT MAP(
1162	-- data_in => Port_in(7),
1163	-- data_in_en => data_in_en(7),
1164	-- reset => reset,
1165	-- clk =>clk,
1166	-- grant(1) => grant_signal(61),
1167	-- grant(2) => grant_signal(62),
1168	-- grant(3) => grant_signal(63),
1169	-- grant(4) => grant_signal(64),
1170	-- grant(5) => grant_signal(65),
1171	-- grant(6) => grant_signal(66),
1172	-- grant(7) => grant_signal(67),
1173	-- grant(8) => grant_signal(68),
1174	-- grant(9) => grant_signal(69),
1175	-- grant(10) => grant_signal(70),
1176	-- fifo_full =>fifo_in_full(7),
1177	-- priority_rotation => priority_rotation_signal(7),
1178	-- fifo_empty => fifo_in_empty(7),
1179	-- data_out =>crossbar_in_port(7),
1180	-- data_out_pulse =>crossbar_in_pulse(7),
1181	-- request(1) =>request_signal(61),
1182	-- request(2) =>request_signal(62),
1183	-- request(3) =>request_signal(63),
1184	-- request(4) =>request_signal(64),
1185	-- request(5) =>request_signal(65),
1186	-- request(6) =>request_signal(66),
1187	-- request(7) =>request_signal(67),
1188	-- request(8) =>request_signal(68),
1189	-- request(9) =>request_signal(69),
1190	-- request(10) =>request_signal(70)
1191	--);
1192	--
1193	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1194	--GENERIC MAP(number_of_ports =>10)
1195	--PORT MAP(
1196	-- data_in => Port_in(8),
1197	-- data_in_en => data_in_en(8),
1198	-- reset => reset,
1199	-- clk =>clk,
1200	-- grant(1) => grant_signal(71),
1201	-- grant(2) => grant_signal(72),
1202	-- grant(3) => grant_signal(73),
1203	-- grant(4) => grant_signal(74),
1204	-- grant(5) => grant_signal(75),
1205	-- grant(6) => grant_signal(76),
1206	-- grant(7) => grant_signal(77),
1207	-- grant(8) => grant_signal(78),
1208	-- grant(9) => grant_signal(79),
1209	-- grant(10) => grant_signal(80),
1210	-- fifo_full =>fifo_in_full(8),
1211	-- priority_rotation => priority_rotation_signal(8),
1212	-- fifo_empty => fifo_in_empty(8),
1213	-- data_out =>crossbar_in_port(8),
1214	-- data_out_pulse =>crossbar_in_pulse(8),
1215	-- request(1) =>request_signal(71),
1216	-- request(2) =>request_signal(72),
1217	-- request(3) =>request_signal(73),
1218	-- request(4) =>request_signal(74),
1219	-- request(5) =>request_signal(75),
1220	-- request(6) =>request_signal(76),
1221	-- request(7) =>request_signal(77),
1222	-- request(8) =>request_signal(78),
1223	-- request(9) =>request_signal(79),
1224	-- request(10) =>request_signal(80)
1225	--);
1226	--
1227	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1228	--GENERIC MAP(number_of_ports =>10)
1229	--PORT MAP(
1230	-- data_in => Port_in(9),
1231	-- data_in_en => data_in_en(9),
1232	-- reset => reset,
1233	-- clk =>clk,
1234	-- grant(1) => grant_signal(81),
1235	-- grant(2) => grant_signal(82),
1236	-- grant(3) => grant_signal(83),
1237	-- grant(4) => grant_signal(84),
1238	-- grant(5) => grant_signal(85),
1239	-- grant(6) => grant_signal(86),
1240	-- grant(7) => grant_signal(87),
1241	-- grant(8) => grant_signal(88),
1242	-- grant(9) => grant_signal(89),
1243	-- grant(10) => grant_signal(90),
1244	-- fifo_full =>fifo_in_full(9),
1245	-- priority_rotation => priority_rotation_signal(9),
1246	-- fifo_empty => fifo_in_empty(9),
1247	-- data_out =>crossbar_in_port(9),
1248	-- data_out_pulse =>crossbar_in_pulse(9),
1249	-- request(1) =>request_signal(81),
1250	-- request(2) =>request_signal(82),
1251	-- request(3) =>request_signal(83),
1252	-- request(4) =>request_signal(84),
1253	-- request(5) =>request_signal(85),
1254	-- request(6) =>request_signal(86),
1255	-- request(7) =>request_signal(87),
1256	-- request(8) =>request_signal(88),
1257	-- request(9) =>request_signal(89),
1258	-- request(10) =>request_signal(90)
1259	--);
1260	--
1261	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1262	--GENERIC MAP(number_of_ports =>10)
1263	--PORT MAP(
1264	-- data_in => Port_in(10),
1265	-- data_in_en => data_in_en(10),
1266	-- reset => reset,
1267	-- clk =>clk,
1268	-- grant(1) => grant_signal(91),
1269	-- grant(2) => grant_signal(92),
1270	-- grant(3) => grant_signal(93),
1271	-- grant(4) => grant_signal(94),
1272	-- grant(5) => grant_signal(95),
1273	-- grant(6) => grant_signal(96),
1274	-- grant(7) => grant_signal(97),
1275	-- grant(8) => grant_signal(98),
1276	-- grant(9) => grant_signal(99),
1277	-- grant(10) => grant_signal(100),
1278	-- fifo_full =>fifo_in_full(10),
1279	-- priority_rotation => priority_rotation_signal(10),
1280	-- fifo_empty => fifo_in_empty(10),
1281	-- data_out =>crossbar_in_port(10),
1282	-- data_out_pulse =>crossbar_in_pulse(10),
1283	-- request(1) =>request_signal(91),
1284	-- request(2) =>request_signal(92),
1285	-- request(3) =>request_signal(93),
1286	-- request(4) =>request_signal(94),
1287	-- request(5) =>request_signal(95),
1288	-- request(6) =>request_signal(96),
1289	-- request(7) =>request_signal(97),
1290	-- request(8) =>request_signal(98),
1291	-- request(9) =>request_signal(99),
1292	-- request(10) =>request_signal(100)
1293	--);
1294	--
1295	--end generate switch10x10;
1296	--
1297	--
1298	---- switch 11 ports
1299	--switch11x11 : if number_of_ports = 11 generate
1300	--
1301	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1302	--GENERIC MAP(number_of_ports =>11)
1303	--PORT MAP(
1304	-- data_in => Port_in(1),
1305	-- data_in_en => data_in_en(1),
1306	-- reset => reset,
1307	-- clk =>clk,
1308	-- grant(1) => grant_signal(1),
1309	-- grant(2) => grant_signal(2),
1310	-- grant(3) => grant_signal(3),
1311	-- grant(4) => grant_signal(4),
1312	-- grant(5) => grant_signal(5),
1313	-- grant(6) => grant_signal(6),
1314	-- grant(7) => grant_signal(7),
1315	-- grant(8) => grant_signal(8),
1316	-- grant(9) => grant_signal(9),
1317	-- grant(10) => grant_signal(10),
1318	-- grant(11) => grant_signal(11),
1319	-- fifo_full =>fifo_in_full(1),
1320	-- priority_rotation => priority_rotation_signal(1),
1321	-- fifo_empty => fifo_in_empty(1),
1322	-- data_out =>crossbar_in_port(1),
1323	-- data_out_pulse =>crossbar_in_pulse(1),
1324	-- request(1) =>request_signal(1),
1325	-- request(2) =>request_signal(2),
1326	-- request(3) =>request_signal(3),
1327	-- request(4) =>request_signal(4),
1328	-- request(5) =>request_signal(5),
1329	-- request(6) =>request_signal(6),
1330	-- request(7) =>request_signal(7),
1331	-- request(8) =>request_signal(8),
1332	-- request(9) =>request_signal(9),
1333	-- request(10) =>request_signal(10),
1334	-- request(11) =>request_signal(11)
1335	--);
1336	--
1337	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1338	--GENERIC MAP(number_of_ports =>11)
1339	--PORT MAP(
1340	-- data_in => Port_in(2),
1341	-- data_in_en => data_in_en(2),
1342	-- reset => reset,
1343	-- clk =>clk,
1344	-- grant(1) => grant_signal(12),
1345	-- grant(02) => grant_signal(13),
1346	-- grant(03) => grant_signal(14),
1347	-- grant(04) => grant_signal(15),
1348	-- grant(05) => grant_signal(16),
1349	-- grant(06) => grant_signal(17),
1350	-- grant(07) => grant_signal(18),
1351	-- grant(08) => grant_signal(19),
1352	-- grant(09) => grant_signal(20),
1353	-- grant(10) => grant_signal(21),
1354	-- grant(11) => grant_signal(22),
1355	-- fifo_full =>fifo_in_full(2),
1356	-- priority_rotation => priority_rotation_signal(2),
1357	-- fifo_empty => fifo_in_empty(2),
1358	-- data_out =>crossbar_in_port(2),
1359	-- data_out_pulse =>crossbar_in_pulse(2),
1360	-- request(01) =>request_signal(12),
1361	-- request(02) =>request_signal(13),
1362	-- request(03) =>request_signal(14),
1363	-- request(04) =>request_signal(15),
1364	-- request(05) =>request_signal(16),
1365	-- request(06) =>request_signal(17),
1366	-- request(07) =>request_signal(18),
1367	-- request(08) =>request_signal(19),
1368	-- request(09) =>request_signal(20),
1369	-- request(10) =>request_signal(21),
1370	-- request(11) =>request_signal(22)
1371	--);
1372	--
1373	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1374	--GENERIC MAP(number_of_ports =>11)
1375	--PORT MAP(
1376	-- data_in => Port_in(3),
1377	-- data_in_en => data_in_en(3),
1378	-- reset => reset,
1379	-- clk =>clk,
1380	-- grant(01) => grant_signal(23),
1381	-- grant(02) => grant_signal(24),
1382	-- grant(03) => grant_signal(25),
1383	-- grant(04) => grant_signal(26),
1384	-- grant(05) => grant_signal(27),
1385	-- grant(06) => grant_signal(28),
1386	-- grant(07) => grant_signal(29),
1387	-- grant(08) => grant_signal(30),
1388	-- grant(09) => grant_signal(31),
1389	-- grant(10) => grant_signal(32),
1390	-- grant(11) => grant_signal(33),
1391	-- fifo_full =>fifo_in_full(3),
1392	-- priority_rotation => priority_rotation_signal(3),
1393	-- fifo_empty => fifo_in_empty(3),
1394	-- data_out =>crossbar_in_port(3),
1395	-- data_out_pulse =>crossbar_in_pulse(3),
1396	-- request(01) =>request_signal(23),
1397	-- request(02) =>request_signal(24),
1398	-- request(03) =>request_signal(25),
1399	-- request(04) =>request_signal(26),
1400	-- request(05) =>request_signal(27),
1401	-- request(06) =>request_signal(28),
1402	-- request(07) =>request_signal(29),
1403	-- request(08) =>request_signal(30),
1404	-- request(09) =>request_signal(31),
1405	-- request(10) =>request_signal(32),
1406	-- request(11) =>request_signal(33)
1407	--);
1408	--
1409	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1410	--GENERIC MAP(number_of_ports =>11)
1411	--PORT MAP(
1412	-- data_in => Port_in(4),
1413	-- data_in_en => data_in_en(4),
1414	-- reset => reset,
1415	-- clk =>clk,
1416	-- grant(01) => grant_signal(34),
1417	-- grant(02) => grant_signal(35),
1418	-- grant(03) => grant_signal(36),
1419	-- grant(04) => grant_signal(37),
1420	-- grant(05) => grant_signal(38),
1421	-- grant(06) => grant_signal(39),
1422	-- grant(07) => grant_signal(40),
1423	-- grant(08) => grant_signal(41),
1424	-- grant(09) => grant_signal(42),
1425	-- grant(10) => grant_signal(43),
1426	-- grant(11) => grant_signal(44),
1427	-- fifo_full =>fifo_in_full(4),
1428	-- priority_rotation => priority_rotation_signal(4),
1429	-- fifo_empty => fifo_in_empty(4),
1430	-- data_out =>crossbar_in_port(4),
1431	-- data_out_pulse =>crossbar_in_pulse(4),
1432	-- request(01) =>request_signal(34),
1433	-- request(02) =>request_signal(35),
1434	-- request(03) =>request_signal(36),
1435	-- request(04) =>request_signal(37),
1436	-- request(05) =>request_signal(38),
1437	-- request(06) =>request_signal(39),
1438	-- request(07) =>request_signal(40),
1439	-- request(08) =>request_signal(41),
1440	-- request(09) =>request_signal(42),
1441	-- request(10) =>request_signal(43),
1442	-- request(11) =>request_signal(44)
1443	--);
1444	--
1445	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1446	--GENERIC MAP(number_of_ports =>11)
1447	--PORT MAP(
1448	-- data_in => Port_in(5),
1449	-- data_in_en => data_in_en(5),
1450	-- reset => reset,
1451	-- clk =>clk,
1452	-- grant(45) => grant_signal(45),
1453	-- grant(46) => grant_signal(46),
1454	-- grant(47) => grant_signal(47),
1455	-- grant(48) => grant_signal(48),
1456	-- grant(49) => grant_signal(49),
1457	-- grant(50) => grant_signal(50),
1458	-- grant(51) => grant_signal(51),
1459	-- grant(52) => grant_signal(52),
1460	-- grant(53) => grant_signal(53),
1461	-- grant(54) => grant_signal(54),
1462	-- grant(55) => grant_signal(55),
1463	-- fifo_full =>fifo_in_full(5),
1464	-- priority_rotation => priority_rotation_signal(5),
1465	-- fifo_empty => fifo_in_empty(5),
1466	-- data_out =>crossbar_in_port(5),
1467	-- data_out_pulse =>crossbar_in_pulse(5),
1468	-- request(45) =>request_signal(45),
1469	-- request(46) =>request_signal(46),
1470	-- request(47) =>request_signal(47),
1471	-- request(48) =>request_signal(48),
1472	-- request(49) =>request_signal(49),
1473	-- request(50) =>request_signal(50),
1474	-- request(51) =>request_signal(51),
1475	-- request(52) =>request_signal(52),
1476	-- request(53) =>request_signal(53),
1477	-- request(54) =>request_signal(54),
1478	-- request(55) =>request_signal(55)
1479	--);
1480	--
1481	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1482	--GENERIC MAP(number_of_ports =>11)
1483	--PORT MAP(
1484	-- data_in => Port_in(6),
1485	-- data_in_en => data_in_en(6),
1486	-- reset => reset,
1487	-- clk =>clk,
1488	-- grant(56) => grant_signal(56),
1489	-- grant(57) => grant_signal(57),
1490	-- grant(58) => grant_signal(58),
1491	-- grant(59) => grant_signal(59),
1492	-- grant(60) => grant_signal(60),
1493	-- grant(61) => grant_signal(61),
1494	-- grant(62) => grant_signal(62),
1495	-- grant(63) => grant_signal(63),
1496	-- grant(64) => grant_signal(64),
1497	-- grant(65) => grant_signal(65),
1498	-- grant(66) => grant_signal(66),
1499	-- fifo_full =>fifo_in_full(6),
1500	-- priority_rotation => priority_rotation_signal(6),
1501	-- fifo_empty => fifo_in_empty(6),
1502	-- data_out =>crossbar_in_port(6),
1503	-- data_out_pulse =>crossbar_in_pulse(6),
1504	-- request(56) =>request_signal(56),
1505	-- request(57) =>request_signal(57),
1506	-- request(58) =>request_signal(58),
1507	-- request(59) =>request_signal(59),
1508	-- request(60) =>request_signal(60),
1509	-- request(61) =>request_signal(61),
1510	-- request(62) =>request_signal(62),
1511	-- request(63) =>request_signal(63),
1512	-- request(64) =>request_signal(64),
1513	-- request(65) =>request_signal(65),
1514	-- request(66) =>request_signal(66)
1515	--);
1516	--
1517	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1518	--GENERIC MAP(number_of_ports =>11)
1519	--PORT MAP(
1520	-- data_in => Port_in(7),
1521	-- data_in_en => data_in_en(7),
1522	-- reset => reset,
1523	-- clk =>clk,
1524	-- grant(67) => grant_signal(67),
1525	-- grant(68) => grant_signal(68),
1526	-- grant(69) => grant_signal(69),
1527	-- grant(70) => grant_signal(70),
1528	-- grant(71) => grant_signal(71),
1529	-- grant(72) => grant_signal(72),
1530	-- grant(73) => grant_signal(73),
1531	-- grant(74) => grant_signal(74),
1532	-- grant(75) => grant_signal(75),
1533	-- grant(76) => grant_signal(76),
1534	-- grant(77) => grant_signal(77),
1535	-- fifo_full =>fifo_in_full(7),
1536	-- priority_rotation => priority_rotation_signal(7),
1537	-- fifo_empty => fifo_in_empty(7),
1538	-- data_out =>crossbar_in_port(8),
1539	-- data_out_pulse =>crossbar_in_pulse(7),
1540	-- request(67) =>request_signal(67),
1541	-- request(68) =>request_signal(68),
1542	-- request(69) =>request_signal(69),
1543	-- request(70) =>request_signal(70),
1544	-- request(71) =>request_signal(71),
1545	-- request(72) =>request_signal(72),
1546	-- request(73) =>request_signal(73),
1547	-- request(74) =>request_signal(74),
1548	-- request(75) =>request_signal(75),
1549	-- request(76) =>request_signal(76),
1550	-- request(77) =>request_signal(77)
1551	--);
1552	--
1553	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1554	--GENERIC MAP(number_of_ports =>11)
1555	--PORT MAP(
1556	-- data_in => Port_in(8),
1557	-- data_in_en => data_in_en(8),
1558	-- reset => reset,
1559	-- clk =>clk,
1560	-- grant(78) => grant_signal(78),
1561	-- grant(79) => grant_signal(79),
1562	-- grant(80) => grant_signal(80),
1563	-- grant(81) => grant_signal(81),
1564	-- grant(82) => grant_signal(82),
1565	-- grant(83) => grant_signal(83),
1566	-- grant(84) => grant_signal(84),
1567	-- grant(85) => grant_signal(85),
1568	-- grant(86) => grant_signal(86),
1569	-- grant(87) => grant_signal(87),
1570	-- grant(88) => grant_signal(88),
1571	-- fifo_full =>fifo_in_full(8),
1572	-- priority_rotation => priority_rotation_signal(8),
1573	-- fifo_empty => fifo_in_empty(8),
1574	-- data_out =>crossbar_in_port(8),
1575	-- data_out_pulse =>crossbar_in_pulse(8),
1576	-- request(78) =>request_signal(78),
1577	-- request(79) =>request_signal(79),
1578	-- request(80) =>request_signal(80),
1579	-- request(81) =>request_signal(81),
1580	-- request(82) =>request_signal(82),
1581	-- request(83) =>request_signal(83),
1582	-- request(84) =>request_signal(84),
1583	-- request(85) =>request_signal(85),
1584	-- request(86) =>request_signal(86),
1585	-- request(87) =>request_signal(87),
1586	-- request(88) =>request_signal(88)
1587	--);
1588	--
1589	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1590	--GENERIC MAP(number_of_ports =>11)
1591	--PORT MAP(
1592	-- data_in => Port_in(9),
1593	-- data_in_en => data_in_en(9),
1594	-- reset => reset,
1595	-- clk =>clk,
1596	-- grant(89) => grant_signal(89),
1597	-- grant(90) => grant_signal(90),
1598	-- grant(91) => grant_signal(91),
1599	-- grant(92) => grant_signal(92),
1600	-- grant(93) => grant_signal(93),
1601	-- grant(94) => grant_signal(94),
1602	-- grant(95) => grant_signal(95),
1603	-- grant(96) => grant_signal(96),
1604	-- grant(97) => grant_signal(97),
1605	-- grant(98) => grant_signal(98),
1606	-- grant(99) => grant_signal(99),
1607	-- fifo_full =>fifo_in_full(9),
1608	-- priority_rotation => priority_rotation_signal(9),
1609	-- fifo_empty => fifo_in_empty(9),
1610	-- data_out =>crossbar_in_port(9),
1611	-- data_out_pulse =>crossbar_in_pulse(9),
1612	-- request(89) =>request_signal(89),
1613	-- request(90) =>request_signal(90),
1614	-- request(91) =>request_signal(91),
1615	-- request(92) =>request_signal(92),
1616	-- request(93) =>request_signal(93),
1617	-- request(94) =>request_signal(94),
1618	-- request(95) =>request_signal(95),
1619	-- request(96) =>request_signal(96),
1620	-- request(97) =>request_signal(97),
1621	-- request(98) =>request_signal(98),
1622	-- request(99) =>request_signal(99)
1623	--);
1624	--
1625	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1626	--GENERIC MAP(number_of_ports =>11)
1627	--PORT MAP(
1628	-- data_in => Port_in(10),
1629	-- data_in_en => data_in_en(10),
1630	-- reset => reset,
1631	-- clk =>clk,
1632	-- grant(1) => grant_signal(100),
1633	-- grant(2) => grant_signal(101),
1634	-- grant(3) => grant_signal(102),
1635	-- grant(4) => grant_signal(103),
1636	-- grant(5) => grant_signal(104),
1637	-- grant(6) => grant_signal(105),
1638	-- grant(7) => grant_signal(106),
1639	-- grant(8) => grant_signal(107),
1640	-- grant(9) => grant_signal(108),
1641	-- grant(10) => grant_signal(109),
1642	-- grant(11) => grant_signal(110),
1643	-- fifo_full =>fifo_in_full(10),
1644	-- priority_rotation => priority_rotation_signal(10),
1645	-- fifo_empty => fifo_in_empty(10),
1646	-- data_out =>crossbar_in_port(10),
1647	-- data_out_pulse =>crossbar_in_pulse(10),
1648	-- request(1) =>request_signal(100),
1649	-- request(2) =>request_signal(101),
1650	-- request(3) =>request_signal(102),
1651	-- request(4) =>request_signal(103),
1652	-- request(5) =>request_signal(104),
1653	-- request(6) =>request_signal(105),
1654	-- request(7) =>request_signal(106),
1655	-- request(8) =>request_signal(107),
1656	-- request(9) =>request_signal(108),
1657	-- request(10) =>request_signal(109),
1658	-- request(11) =>request_signal(110)
1659	--);
1660	--
1661	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1662	--GENERIC MAP(number_of_ports =>11)
1663	--PORT MAP(
1664	-- data_in => Port_in(11),
1665	-- data_in_en => data_in_en(11),
1666	-- reset => reset,
1667	-- clk =>clk,
1668	-- grant(1) => grant_signal(111),
1669	-- grant(2) => grant_signal(112),
1670	-- grant(3) => grant_signal(113),
1671	-- grant(4) => grant_signal(114),
1672	-- grant(5) => grant_signal(115),
1673	-- grant(6) => grant_signal(116),
1674	-- grant(7) => grant_signal(117),
1675	-- grant(8) => grant_signal(118),
1676	-- grant(9) => grant_signal(119),
1677	-- grant(10) => grant_signal(120),
1678	-- grant(11) => grant_signal(121),
1679	-- fifo_full =>fifo_in_full(11),
1680	-- priority_rotation => priority_rotation_signal(11),
1681	-- fifo_empty => fifo_in_empty(11),
1682	-- data_out =>crossbar_in_port(11),
1683	-- data_out_pulse =>crossbar_in_pulse(11),
1684	-- request(1) =>request_signal(111),
1685	-- request(2) =>request_signal(112),
1686	-- request(3) =>request_signal(113),
1687	-- request(4) =>request_signal(114),
1688	-- request(5) =>request_signal(115),
1689	-- request(6) =>request_signal(116),
1690	-- request(7) =>request_signal(117),
1691	-- request(8) =>request_signal(118),
1692	-- request(9) =>request_signal(119),
1693	-- request(10) =>request_signal(120),
1694	-- request(11) =>request_signal(121)
1695	--);
1696	--
1697	--end generate switch11x11;
1698	--
1699	--
1700	---- switch 12 ports
1701	--switch12x12 : if number_of_ports = 12 generate
1702	--
1703	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1704	--GENERIC MAP(number_of_ports =>12)
1705	--PORT MAP(
1706	-- data_in => Port_in(1),
1707	-- data_in_en => data_in_en(1),
1708	-- reset => reset,
1709	-- clk =>clk,
1710	-- grant(1) => grant_signal(1),
1711	-- grant(2) => grant_signal(2),
1712	-- grant(3) => grant_signal(3),
1713	-- grant(4) => grant_signal(4),
1714	-- grant(5) => grant_signal(5),
1715	-- grant(6) => grant_signal(6),
1716	-- grant(7) => grant_signal(7),
1717	-- grant(8) => grant_signal(8),
1718	-- grant(9) => grant_signal(9),
1719	-- grant(10) => grant_signal(10),
1720	-- grant(11) => grant_signal(11),
1721	-- grant(12) => grant_signal(12),
1722	-- fifo_full =>fifo_in_full(1),
1723	-- priority_rotation => priority_rotation_signal(1),
1724	-- fifo_empty => fifo_in_empty(1),
1725	-- data_out =>crossbar_in_port(1),
1726	-- data_out_pulse =>crossbar_in_pulse(1),
1727	-- request(1) =>request_signal(1),
1728	-- request(2) =>request_signal(2),
1729	-- request(3) =>request_signal(3),
1730	-- request(4) =>request_signal(4),
1731	-- request(5) =>request_signal(5),
1732	-- request(6) =>request_signal(6),
1733	-- request(7) =>request_signal(7),
1734	-- request(8) =>request_signal(8),
1735	-- request(9) =>request_signal(9),
1736	-- request(10) =>request_signal(10),
1737	-- request(11) =>request_signal(11),
1738	-- request(12) =>request_signal(12)
1739	--);
1740	--
1741	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1742	--GENERIC MAP(number_of_ports =>12)
1743	--PORT MAP(
1744	-- data_in => Port_in(2),
1745	-- data_in_en => data_in_en(2),
1746	-- reset => reset,
1747	-- clk =>clk,
1748	-- grant(13) => grant_signal(13),
1749	-- grant(14) => grant_signal(14),
1750	-- grant(15) => grant_signal(15),
1751	-- grant(16) => grant_signal(16),
1752	-- grant(17) => grant_signal(17),
1753	-- grant(18) => grant_signal(18),
1754	-- grant(19) => grant_signal(19),
1755	-- grant(20) => grant_signal(20),
1756	-- grant(21) => grant_signal(21),
1757	-- grant(22) => grant_signal(22),
1758	-- grant(23) => grant_signal(23),
1759	-- grant(24) => grant_signal(24),
1760	-- fifo_full =>fifo_in_full(2),
1761	-- priority_rotation => priority_rotation_signal(2),
1762	-- fifo_empty => fifo_in_empty(2),
1763	-- data_out =>crossbar_in_port(2),
1764	-- data_out_pulse =>crossbar_in_pulse(2),
1765	-- request(13) =>request_signal(13),
1766	-- request(14) =>request_signal(14),
1767	-- request(15) =>request_signal(15),
1768	-- request(16) =>request_signal(16),
1769	-- request(17) =>request_signal(17),
1770	-- request(18) =>request_signal(18),
1771	-- request(19) =>request_signal(19),
1772	-- request(20) =>request_signal(20),
1773	-- request(21) =>request_signal(21),
1774	-- request(22) =>request_signal(22),
1775	-- request(23) =>request_signal(23),
1776	-- request(24) =>request_signal(24)
1777	--);
1778	--
1779	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1780	--GENERIC MAP(number_of_ports =>12)
1781	--PORT MAP(
1782	-- data_in => Port_in(3),
1783	-- data_in_en => data_in_en(3),
1784	-- reset => reset,
1785	-- clk =>clk,
1786	-- grant(25) => grant_signal(25),
1787	-- grant(26) => grant_signal(26),
1788	-- grant(27) => grant_signal(27),
1789	-- grant(28) => grant_signal(28),
1790	-- grant(29) => grant_signal(29),
1791	-- grant(30) => grant_signal(30),
1792	-- grant(31) => grant_signal(31),
1793	-- grant(32) => grant_signal(32),
1794	-- grant(33) => grant_signal(33),
1795	-- grant(34) => grant_signal(34),
1796	-- grant(35) => grant_signal(35),
1797	-- grant(36) => grant_signal(36),
1798	-- fifo_full =>fifo_in_full(3),
1799	-- priority_rotation => priority_rotation_signal(3),
1800	-- fifo_empty => fifo_in_empty(3),
1801	-- data_out =>crossbar_in_port(3),
1802	-- data_out_pulse =>crossbar_in_pulse(3),
1803	-- request(25) =>request_signal(25),
1804	-- request(26) =>request_signal(26),
1805	-- request(27) =>request_signal(27),
1806	-- request(28) =>request_signal(28),
1807	-- request(29) =>request_signal(29),
1808	-- request(30) =>request_signal(30),
1809	-- request(31) =>request_signal(31),
1810	-- request(32) =>request_signal(32),
1811	-- request(33) =>request_signal(33),
1812	-- request(34) =>request_signal(34),
1813	-- request(35) =>request_signal(35),
1814	-- request(36) =>request_signal(36)
1815	--);
1816	--
1817	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1818	--GENERIC MAP(number_of_ports =>12)
1819	--PORT MAP(
1820	-- data_in => Port_in(4),
1821	-- data_in_en => data_in_en(4),
1822	-- reset => reset,
1823	-- clk =>clk,
1824	-- grant(37) => grant_signal(37),
1825	-- grant(38) => grant_signal(38),
1826	-- grant(39) => grant_signal(39),
1827	-- grant(40) => grant_signal(40),
1828	-- grant(41) => grant_signal(41),
1829	-- grant(42) => grant_signal(42),
1830	-- grant(43) => grant_signal(43),
1831	-- grant(44) => grant_signal(44),
1832	-- grant(45) => grant_signal(45),
1833	-- grant(46) => grant_signal(46),
1834	-- grant(47) => grant_signal(47),
1835	-- grant(48) => grant_signal(48),
1836	-- fifo_full =>fifo_in_full(4),
1837	-- priority_rotation => priority_rotation_signal(4),
1838	-- fifo_empty => fifo_in_empty(4),
1839	-- data_out =>crossbar_in_port(4),
1840	-- data_out_pulse =>crossbar_in_pulse(4),
1841	-- request(37) =>request_signal(37),
1842	-- request(38) =>request_signal(38),
1843	-- request(39) =>request_signal(39),
1844	-- request(40) =>request_signal(40),
1845	-- request(41) =>request_signal(41),
1846	-- request(42) =>request_signal(42),
1847	-- request(43) =>request_signal(43),
1848	-- request(44) =>request_signal(44),
1849	-- request(45) =>request_signal(45),
1850	-- request(46) =>request_signal(46),
1851	-- request(47) =>request_signal(47),
1852	-- request(48) =>request_signal(48)
1853	--);
1854	--
1855	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1856	--GENERIC MAP(number_of_ports =>12)
1857	--PORT MAP(
1858	-- data_in => Port_in(5),
1859	-- data_in_en => data_in_en(5),
1860	-- reset => reset,
1861	-- clk =>clk,
1862	-- grant(49) => grant_signal(49),
1863	-- grant(50) => grant_signal(50),
1864	-- grant(51) => grant_signal(51),
1865	-- grant(52) => grant_signal(52),
1866	-- grant(53) => grant_signal(53),
1867	-- grant(54) => grant_signal(54),
1868	-- grant(55) => grant_signal(55),
1869	-- grant(56) => grant_signal(56),
1870	-- grant(57) => grant_signal(57),
1871	-- grant(58) => grant_signal(58),
1872	-- grant(59) => grant_signal(59),
1873	-- grant(60) => grant_signal(60),
1874	-- fifo_full =>fifo_in_full(5),
1875	-- priority_rotation => priority_rotation_signal(5),
1876	-- fifo_empty => fifo_in_empty(5),
1877	-- data_out =>crossbar_in_port(5),
1878	-- data_out_pulse =>crossbar_in_pulse(5),
1879	-- request(49) =>request_signal(49),
1880	-- request(50) =>request_signal(50),
1881	-- request(51) =>request_signal(51),
1882	-- request(52) =>request_signal(52),
1883	-- request(53) =>request_signal(53),
1884	-- request(54) =>request_signal(54),
1885	-- request(55) =>request_signal(55),
1886	-- request(56) =>request_signal(56),
1887	-- request(57) =>request_signal(57),
1888	-- request(58) =>request_signal(58),
1889	-- request(59) =>request_signal(59),
1890	-- request(60) =>request_signal(60)
1891	--);
1892	--
1893	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1894	--GENERIC MAP(number_of_ports =>12)
1895	--PORT MAP(
1896	-- data_in => Port_in(6),
1897	-- data_in_en => data_in_en(6),
1898	-- reset => reset,
1899	-- clk =>clk,
1900	-- grant(61) => grant_signal(61),
1901	-- grant(62) => grant_signal(62),
1902	-- grant(63) => grant_signal(63),
1903	-- grant(64) => grant_signal(64),
1904	-- grant(65) => grant_signal(65),
1905	-- grant(66) => grant_signal(66),
1906	-- grant(67) => grant_signal(67),
1907	-- grant(68) => grant_signal(68),
1908	-- grant(69) => grant_signal(69),
1909	-- grant(70) => grant_signal(70),
1910	-- grant(71) => grant_signal(71),
1911	-- grant(72) => grant_signal(72),
1912	-- fifo_full =>fifo_in_full(6),
1913	-- priority_rotation => priority_rotation_signal(6),
1914	-- fifo_empty => fifo_in_empty(6),
1915	-- data_out =>crossbar_in_port(6),
1916	-- data_out_pulse =>crossbar_in_pulse(6),
1917	-- request(61) =>request_signal(61),
1918	-- request(62) =>request_signal(62),
1919	-- request(63) =>request_signal(63),
1920	-- request(64) =>request_signal(64),
1921	-- request(65) =>request_signal(65),
1922	-- request(66) =>request_signal(66),
1923	-- request(67) =>request_signal(67),
1924	-- request(68) =>request_signal(68),
1925	-- request(69) =>request_signal(69),
1926	-- request(70) =>request_signal(70),
1927	-- request(71) =>request_signal(71),
1928	-- request(72) =>request_signal(72)
1929	--);
1930	--
1931	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1932	--GENERIC MAP(number_of_ports =>12)
1933	--PORT MAP(
1934	-- data_in => Port_in(7),
1935	-- data_in_en => data_in_en(7),
1936	-- reset => reset,
1937	-- clk =>clk,
1938	-- grant(73) => grant_signal(73),
1939	-- grant(74) => grant_signal(74),
1940	-- grant(75) => grant_signal(75),
1941	-- grant(76) => grant_signal(76),
1942	-- grant(77) => grant_signal(77),
1943	-- grant(78) => grant_signal(78),
1944	-- grant(79) => grant_signal(79),
1945	-- grant(80) => grant_signal(80),
1946	-- grant(81) => grant_signal(81),
1947	-- grant(82) => grant_signal(82),
1948	-- grant(83) => grant_signal(83),
1949	-- grant(84) => grant_signal(84),
1950	-- fifo_full =>fifo_in_full(7),
1951	-- priority_rotation => priority_rotation_signal(7),
1952	-- fifo_empty => fifo_in_empty(7),
1953	-- data_out =>crossbar_in_port(7),
1954	-- data_out_pulse =>crossbar_in_pulse(7),
1955	-- request(73) =>request_signal(73),
1956	-- request(74) =>request_signal(74),
1957	-- request(75) =>request_signal(75),
1958	-- request(76) =>request_signal(76),
1959	-- request(77) =>request_signal(77),
1960	-- request(78) =>request_signal(78),
1961	-- request(79) =>request_signal(79),
1962	-- request(80) =>request_signal(80),
1963	-- request(81) =>request_signal(81),
1964	-- request(82) =>request_signal(82),
1965	-- request(83) =>request_signal(83),
1966	-- request(84) =>request_signal(84)
1967	--);
1968	--
1969	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1970	--GENERIC MAP(number_of_ports =>12)
1971	--PORT MAP(
1972	-- data_in => Port_in(8),
1973	-- data_in_en => data_in_en(8),
1974	-- reset => reset,
1975	-- clk =>clk,
1976	-- grant(85) => grant_signal(85),
1977	-- grant(86) => grant_signal(86),
1978	-- grant(87) => grant_signal(87),
1979	-- grant(88) => grant_signal(88),
1980	-- grant(89) => grant_signal(89),
1981	-- grant(90) => grant_signal(90),
1982	-- grant(91) => grant_signal(91),
1983	-- grant(92) => grant_signal(92),
1984	-- grant(93) => grant_signal(93),
1985	-- grant(94) => grant_signal(94),
1986	-- grant(95) => grant_signal(95),
1987	-- grant(96) => grant_signal(96),
1988	-- fifo_full =>fifo_in_full(8),
1989	-- priority_rotation => priority_rotation_signal(8),
1990	-- fifo_empty => fifo_in_empty(8),
1991	-- data_out =>crossbar_in_port(8),
1992	-- data_out_pulse =>crossbar_in_pulse(8),
1993	-- request(85) =>request_signal(85),
1994	-- request(86) =>request_signal(86),
1995	-- request(87) =>request_signal(87),
1996	-- request(88) =>request_signal(88),
1997	-- request(89) =>request_signal(89),
1998	-- request(90) =>request_signal(90),
1999	-- request(91) =>request_signal(91),
2000	-- request(92) =>request_signal(92),
2001	-- request(93) =>request_signal(93),
2002	-- request(94) =>request_signal(94),
2003	-- request(95) =>request_signal(95),
2004	-- request(96) =>request_signal(96)
2005	--);
2006	--
2007	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2008	--GENERIC MAP(number_of_ports =>12)
2009	--PORT MAP(
2010	-- data_in => Port_in(9),
2011	-- data_in_en => data_in_en(9),
2012	-- reset => reset,
2013	-- clk =>clk,
2014	-- grant(97) => grant_signal(97),
2015	-- grant(98) => grant_signal(98),
2016	-- grant(99) => grant_signal(99),
2017	-- grant(100) => grant_signal(100),
2018	-- grant(101) => grant_signal(101),
2019	-- grant(102) => grant_signal(102),
2020	-- grant(103) => grant_signal(103),
2021	-- grant(104) => grant_signal(104),
2022	-- grant(105) => grant_signal(105),
2023	-- grant(106) => grant_signal(106),
2024	-- grant(107) => grant_signal(107),
2025	-- grant(108) => grant_signal(108),
2026	-- fifo_full =>fifo_in_full(9),
2027	-- priority_rotation => priority_rotation_signal(9),
2028	-- fifo_empty => fifo_in_empty(9),
2029	-- data_out =>crossbar_in_port(9),
2030	-- data_out_pulse =>crossbar_in_pulse(9),
2031	-- request(97) =>request_signal(97),
2032	-- request(98) =>request_signal(98),
2033	-- request(99) =>request_signal(99),
2034	-- request(100) =>request_signal(100),
2035	-- request(101) =>request_signal(101),
2036	-- request(102) =>request_signal(102),
2037	-- request(103) =>request_signal(103),
2038	-- request(104) =>request_signal(104),
2039	-- request(105) =>request_signal(105),
2040	-- request(106) =>request_signal(106),
2041	-- request(107) =>request_signal(107),
2042	-- request(108) =>request_signal(108)
2043	--);
2044	--
2045	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2046	--GENERIC MAP(number_of_ports =>12)
2047	--PORT MAP(
2048	-- data_in => Port_in(10),
2049	-- data_in_en => data_in_en(10),
2050	-- reset => reset,
2051	-- clk =>clk,
2052	-- grant(1) => grant_signal(109),
2053	-- grant(2) => grant_signal(110),
2054	-- grant(3) => grant_signal(111),
2055	-- grant(4) => grant_signal(112),
2056	-- grant(5) => grant_signal(113),
2057	-- grant(6) => grant_signal(114),
2058	-- grant(7) => grant_signal(115),
2059	-- grant(8) => grant_signal(116),
2060	-- grant(9) => grant_signal(117),
2061	-- grant(10) => grant_signal(118),
2062	-- grant(11) => grant_signal(119),
2063	-- grant(12) => grant_signal(120),
2064	-- fifo_full =>fifo_in_full(10),
2065	-- priority_rotation => priority_rotation_signal(10),
2066	-- fifo_empty => fifo_in_empty(10),
2067	-- data_out =>crossbar_in_port(10),
2068	-- data_out_pulse =>crossbar_in_pulse(10),
2069	-- request(109) =>request_signal(109),
2070	-- request(110) =>request_signal(110),
2071	-- request(111) =>request_signal(111),
2072	-- request(112) =>request_signal(112),
2073	-- request(113) =>request_signal(113),
2074	-- request(114) =>request_signal(114),
2075	-- request(115) =>request_signal(115),
2076	-- request(116) =>request_signal(116),
2077	-- request(117) =>request_signal(117),
2078	-- request(118) =>request_signal(118),
2079	-- request(119) =>request_signal(119),
2080	-- request(120) =>request_signal(120)
2081	--);
2082	--
2083	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2084	--GENERIC MAP(number_of_ports =>12)
2085	--PORT MAP(
2086	-- data_in => Port_in(11),
2087	-- data_in_en => data_in_en(11),
2088	-- reset => reset,
2089	-- clk =>clk,
2090	-- grant(1) => grant_signal(121),
2091	-- grant(2) => grant_signal(122),
2092	-- grant(3) => grant_signal(123),
2093	-- grant(4) => grant_signal(124),
2094	-- grant(5) => grant_signal(125),
2095	-- grant(6) => grant_signal(126),
2096	-- grant(7) => grant_signal(127),
2097	-- grant(8) => grant_signal(128),
2098	-- grant(9) => grant_signal(129),
2099	-- grant(10) => grant_signal(130),
2100	-- grant(11) => grant_signal(131),
2101	-- grant(12) => grant_signal(132),
2102	-- fifo_full =>fifo_in_full(11),
2103	-- priority_rotation => priority_rotation_signal(11),
2104	-- fifo_empty => fifo_in_empty(11),
2105	-- data_out =>crossbar_in_port(11),
2106	-- data_out_pulse =>crossbar_in_pulse(11),
2107	-- request(121) =>request_signal(121),
2108	-- request(122) =>request_signal(122),
2109	-- request(123) =>request_signal(123),
2110	-- request(124) =>request_signal(124),
2111	-- request(125) =>request_signal(125),
2112	-- request(126) =>request_signal(126),
2113	-- request(127) =>request_signal(127),
2114	-- request(128) =>request_signal(128),
2115	-- request(129) =>request_signal(129),
2116	-- request(130) =>request_signal(130),
2117	-- request(131) =>request_signal(131),
2118	-- request(132) =>request_signal(132)
2119	--);
2120	--
2121	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2122	--GENERIC MAP(number_of_ports =>12)
2123	--PORT MAP(
2124	-- data_in => Port_in(12),
2125	-- data_in_en => data_in_en(12),
2126	-- reset => reset,
2127	-- clk =>clk,
2128	-- grant(133) => grant_signal(133),
2129	-- grant(134) => grant_signal(134),
2130	-- grant(135) => grant_signal(135),
2131	-- grant(136) => grant_signal(136),
2132	-- grant(137) => grant_signal(137),
2133	-- grant(138) => grant_signal(138),
2134	-- grant(139) => grant_signal(139),
2135	-- grant(140) => grant_signal(140),
2136	-- grant(141) => grant_signal(141),
2137	-- grant(142) => grant_signal(142),
2138	-- grant(143) => grant_signal(143),
2139	-- grant(144) => grant_signal(144),
2140	-- fifo_full =>fifo_in_full(12),
2141	-- priority_rotation => priority_rotation_signal(12),
2142	-- fifo_empty => fifo_in_empty(12),
2143	-- data_out =>crossbar_in_port(12),
2144	-- data_out_pulse =>crossbar_in_pulse(12),
2145	-- request(133) =>request_signal(133),
2146	-- request(134) =>request_signal(134),
2147	-- request(135) =>request_signal(135),
2148	-- request(136) =>request_signal(136),
2149	-- request(137) =>request_signal(137),
2150	-- request(138) =>request_signal(138),
2151	-- request(139) =>request_signal(139),
2152	-- request(140) =>request_signal(140),
2153	-- request(141) =>request_signal(141),
2154	-- request(142) =>request_signal(142),
2155	-- request(143) =>request_signal(143),
2156	-- request(144) =>request_signal(144)
2157	--);
2158	--
2159	--end generate switch12x12;
2160	--
2161	--
2162	---- switch 13 ports
2163	--switch13x13 : if number_of_ports = 13 generate
2164	--
2165	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2166	--GENERIC MAP(number_of_ports =>13)
2167	--PORT MAP(
2168	-- data_in => Port_in(1),
2169	-- data_in_en => data_in_en(1),
2170	-- reset => reset,
2171	-- clk =>clk,
2172	-- grant(1) => grant_signal(1),
2173	-- grant(2) => grant_signal(2),
2174	-- grant(3) => grant_signal(3),
2175	-- grant(4) => grant_signal(4),
2176	-- grant(5) => grant_signal(5),
2177	-- grant(6) => grant_signal(6),
2178	-- grant(7) => grant_signal(7),
2179	-- grant(8) => grant_signal(8),
2180	-- grant(9) => grant_signal(9),
2181	-- grant(10) => grant_signal(10),
2182	-- grant(11) => grant_signal(11),
2183	-- grant(12) => grant_signal(12),
2184	-- grant(13) => grant_signal(13),
2185	-- fifo_full =>fifo_in_full(1),
2186	-- priority_rotation => priority_rotation_signal(1),
2187	-- fifo_empty => fifo_in_empty(1),
2188	-- data_out =>crossbar_in_port(1),
2189	-- data_out_pulse =>crossbar_in_pulse(1),
2190	-- request(1) =>request_signal(1),
2191	-- request(2) =>request_signal(2),
2192	-- request(3) =>request_signal(3),
2193	-- request(4) =>request_signal(4),
2194	-- request(5) =>request_signal(5),
2195	-- request(6) =>request_signal(6),
2196	-- request(7) =>request_signal(7),
2197	-- request(8) =>request_signal(8),
2198	-- request(9) =>request_signal(9),
2199	-- request(10) =>request_signal(10),
2200	-- request(11) =>request_signal(11),
2201	-- request(12) =>request_signal(12),
2202	-- request(13) =>request_signal(13)
2203	--);
2204	--
2205	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2206	--GENERIC MAP(number_of_ports =>13)
2207	--PORT MAP(
2208	-- data_in => Port_in(2),
2209	-- data_in_en => data_in_en(2),
2210	-- reset => reset,
2211	-- clk =>clk,
2212	-- grant(14) => grant_signal(14),
2213	-- grant(15) => grant_signal(15),
2214	-- grant(16) => grant_signal(16),
2215	-- grant(17) => grant_signal(17),
2216	-- grant(18) => grant_signal(18),
2217	-- grant(19) => grant_signal(19),
2218	-- grant(20) => grant_signal(20),
2219	-- grant(21) => grant_signal(21),
2220	-- grant(22) => grant_signal(22),
2221	-- grant(23) => grant_signal(23),
2222	-- grant(24) => grant_signal(24),
2223	-- grant(25) => grant_signal(25),
2224	-- grant(26) => grant_signal(26),
2225	-- fifo_full =>fifo_in_full(2),
2226	-- priority_rotation => priority_rotation_signal(2),
2227	-- fifo_empty => fifo_in_empty(2),
2228	-- data_out =>crossbar_in_port(2),
2229	-- data_out_pulse =>crossbar_in_pulse(2),
2230	-- request(14) =>request_signal(14),
2231	-- request(15) =>request_signal(15),
2232	-- request(16) =>request_signal(16),
2233	-- request(17) =>request_signal(17),
2234	-- request(18) =>request_signal(18),
2235	-- request(19) =>request_signal(19),
2236	-- request(20) =>request_signal(20),
2237	-- request(21) =>request_signal(21),
2238	-- request(22) =>request_signal(22),
2239	-- request(23) =>request_signal(23),
2240	-- request(24) =>request_signal(24),
2241	-- request(25) =>request_signal(25),
2242	-- request(26) =>request_signal(26)
2243	--);
2244
2245	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2246	--GENERIC MAP(number_of_ports =>13)
2247	--PORT MAP(
2248	-- data_in => Port_in(3),
2249	-- data_in_en => data_in_en(3),
2250	-- reset => reset,
2251	-- clk =>clk,
2252	-- grant(27) => grant_signal(27),
2253	-- grant(28) => grant_signal(28),
2254	-- grant(29) => grant_signal(29),
2255	-- grant(30) => grant_signal(30),
2256	-- grant(31) => grant_signal(31),
2257	-- grant(32) => grant_signal(32),
2258	-- grant(33) => grant_signal(33),
2259	-- grant(34) => grant_signal(34),
2260	-- grant(35) => grant_signal(35),
2261	-- grant(36) => grant_signal(36),
2262	-- grant(37) => grant_signal(37),
2263	-- grant(38) => grant_signal(38),
2264	-- grant(39) => grant_signal(39),
2265	-- fifo_full =>fifo_in_full(3),
2266	-- priority_rotation => priority_rotation_signal(3),
2267	-- fifo_empty => fifo_in_empty(3),
2268	-- data_out =>crossbar_in_port(3),
2269	-- data_out_pulse =>crossbar_in_pulse(3),
2270	-- request(27) =>request_signal(27),
2271	-- request(28) =>request_signal(28),
2272	-- request(29) =>request_signal(29),
2273	-- request(30) =>request_signal(30),
2274	-- request(31) =>request_signal(31),
2275	-- request(32) =>request_signal(32),
2276	-- request(33) =>request_signal(33),
2277	-- request(34) =>request_signal(34),
2278	-- request(35) =>request_signal(35),
2279	-- request(36) =>request_signal(36),
2280	-- request(37) =>request_signal(37),
2281	-- request(38) =>request_signal(38),
2282	-- request(39) =>request_signal(39)
2283	--);
2284	--
2285	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2286	--GENERIC MAP(number_of_ports =>13)
2287	--PORT MAP(
2288	-- data_in => Port_in(4),
2289	-- data_in_en => data_in_en(4),
2290	-- reset => reset,
2291	-- clk =>clk,
2292	-- grant(40) => grant_signal(40),
2293	-- grant(41) => grant_signal(41),
2294	-- grant(42) => grant_signal(42),
2295	-- grant(43) => grant_signal(43),
2296	-- grant(44) => grant_signal(44),
2297	-- grant(45) => grant_signal(45),
2298	-- grant(46) => grant_signal(46),
2299	-- grant(47) => grant_signal(47),
2300	-- grant(48) => grant_signal(48),
2301	-- grant(49) => grant_signal(49),
2302	-- grant(50) => grant_signal(50),
2303	-- grant(51) => grant_signal(51),
2304	-- grant(52) => grant_signal(52),
2305	-- fifo_full =>fifo_in_full(4),
2306	-- priority_rotation => priority_rotation_signal(4),
2307	-- fifo_empty => fifo_in_empty(4),
2308	-- data_out =>crossbar_in_port(4),
2309	-- data_out_pulse =>crossbar_in_pulse(4),
2310	-- request(40) =>request_signal(40),
2311	-- request(41) =>request_signal(41),
2312	-- request(42) =>request_signal(42),
2313	-- request(43) =>request_signal(43),
2314	-- request(44) =>request_signal(44),
2315	-- request(45) =>request_signal(45),
2316	-- request(46) =>request_signal(46),
2317	-- request(47) =>request_signal(47),
2318	-- request(48) =>request_signal(48),
2319	-- request(49) =>request_signal(49),
2320	-- request(50) =>request_signal(50),
2321	-- request(51) =>request_signal(51),
2322	-- request(52) =>request_signal(52)
2323	--);
2324	--
2325	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2326	--GENERIC MAP(number_of_ports =>13)
2327	--PORT MAP(
2328	-- data_in => Port_in(5),
2329	-- data_in_en => data_in_en(5),
2330	-- reset => reset,
2331	-- clk =>clk,
2332	-- grant(53) => grant_signal(53),
2333	-- grant(54) => grant_signal(54),
2334	-- grant(55) => grant_signal(55),
2335	-- grant(56) => grant_signal(56),
2336	-- grant(57) => grant_signal(57),
2337	-- grant(58) => grant_signal(58),
2338	-- grant(59) => grant_signal(59),
2339	-- grant(60) => grant_signal(60),
2340	-- grant(61) => grant_signal(61),
2341	-- grant(62) => grant_signal(62),
2342	-- grant(63) => grant_signal(63),
2343	-- grant(64) => grant_signal(64),
2344	-- grant(65) => grant_signal(65),
2345	-- fifo_full =>fifo_in_full(5),
2346	-- priority_rotation => priority_rotation_signal(5),
2347	-- fifo_empty => fifo_in_empty(5),
2348	-- data_out =>crossbar_in_port(5),
2349	-- data_out_pulse =>crossbar_in_pulse(5),
2350	-- request(53) =>request_signal(53),
2351	-- request(54) =>request_signal(54),
2352	-- request(55) =>request_signal(55),
2353	-- request(56) =>request_signal(56),
2354	-- request(57) =>request_signal(57),
2355	-- request(58) =>request_signal(58),
2356	-- request(59) =>request_signal(59),
2357	-- request(60) =>request_signal(60),
2358	-- request(61) =>request_signal(61),
2359	-- request(62) =>request_signal(62),
2360	-- request(63) =>request_signal(63),
2361	-- request(64) =>request_signal(64),
2362	-- request(65) =>request_signal(65)
2363	--);
2364	--
2365	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2366	--GENERIC MAP(number_of_ports =>13)
2367	--PORT MAP(
2368	-- data_in => Port_in(6),
2369	-- data_in_en => data_in_en(6),
2370	-- reset => reset,
2371	-- clk =>clk,
2372	-- grant(66) => grant_signal(66),
2373	-- grant(67) => grant_signal(67),
2374	-- grant(68) => grant_signal(68),
2375	-- grant(69) => grant_signal(69),
2376	-- grant(70) => grant_signal(70),
2377	-- grant(71) => grant_signal(71),
2378	-- grant(72) => grant_signal(72),
2379	-- grant(73) => grant_signal(73),
2380	-- grant(74) => grant_signal(74),
2381	-- grant(75) => grant_signal(75),
2382	-- grant(76) => grant_signal(76),
2383	-- grant(77) => grant_signal(77),
2384	-- grant(78) => grant_signal(78),
2385	-- fifo_full =>fifo_in_full(6),
2386	-- priority_rotation => priority_rotation_signal(6),
2387	-- fifo_empty => fifo_in_empty(6),
2388	-- data_out =>crossbar_in_port(6),
2389	-- data_out_pulse =>crossbar_in_pulse(6),
2390	-- request(66) =>request_signal(66),
2391	-- request(67) =>request_signal(67),
2392	-- request(68) =>request_signal(68),
2393	-- request(69) =>request_signal(69),
2394	-- request(70) =>request_signal(70),
2395	-- request(71) =>request_signal(71),
2396	-- request(72) =>request_signal(72),
2397	-- request(73) =>request_signal(73),
2398	-- request(74) =>request_signal(74),
2399	-- request(75) =>request_signal(75),
2400	-- request(76) =>request_signal(76),
2401	-- request(77) =>request_signal(77),
2402	-- request(78) =>request_signal(78)
2403	--);
2404	--
2405	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2406	--GENERIC MAP(number_of_ports =>13)
2407	--PORT MAP(
2408	-- data_in => Port_in(7),
2409	-- data_in_en => data_in_en(7),
2410	-- reset => reset,
2411	-- clk =>clk,
2412	-- grant(79) => grant_signal(79),
2413	-- grant(80) => grant_signal(80),
2414	-- grant(81) => grant_signal(81),
2415	-- grant(82) => grant_signal(82),
2416	-- grant(83) => grant_signal(83),
2417	-- grant(84) => grant_signal(84),
2418	-- grant(85) => grant_signal(85),
2419	-- grant(86) => grant_signal(86),
2420	-- grant(87) => grant_signal(87),
2421	-- grant(88) => grant_signal(88),
2422	-- grant(89) => grant_signal(89),
2423	-- grant(90) => grant_signal(90),
2424	-- grant(91) => grant_signal(91),
2425	-- fifo_full =>fifo_in_full(7),
2426	-- priority_rotation => priority_rotation_signal(7),
2427	-- fifo_empty => fifo_in_empty(7),
2428	-- data_out =>crossbar_in_port(7),
2429	-- data_out_pulse =>crossbar_in_pulse(7),
2430	-- request(79) =>request_signal(79),
2431	-- request(80) =>request_signal(80),
2432	-- request(81) =>request_signal(81),
2433	-- request(82) =>request_signal(82),
2434	-- request(83) =>request_signal(83),
2435	-- request(84) =>request_signal(84),
2436	-- request(85) =>request_signal(85),
2437	-- request(86) =>request_signal(86),
2438	-- request(87) =>request_signal(87),
2439	-- request(88) =>request_signal(88),
2440	-- request(89) =>request_signal(89),
2441	-- request(90) =>request_signal(90),
2442	-- request(91) =>request_signal(91)
2443	--);
2444	--
2445	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2446	--GENERIC MAP(number_of_ports =>13)
2447	--PORT MAP(
2448	-- data_in => Port_in(8),
2449	-- data_in_en => data_in_en(8),
2450	-- reset => reset,
2451	-- clk =>clk,
2452	-- grant(92) => grant_signal(92),
2453	-- grant(93) => grant_signal(93),
2454	-- grant(94) => grant_signal(94),
2455	-- grant(95) => grant_signal(95),
2456	-- grant(96) => grant_signal(96),
2457	-- grant(97) => grant_signal(97),
2458	-- grant(98) => grant_signal(98),
2459	-- grant(99) => grant_signal(99),
2460	-- grant(100) => grant_signal(100),
2461	-- grant(101) => grant_signal(101),
2462	-- grant(102) => grant_signal(102),
2463	-- grant(103) => grant_signal(103),
2464	-- grant(104) => grant_signal(104),
2465	-- fifo_full =>fifo_in_full(8),
2466	-- priority_rotation => priority_rotation_signal(8),
2467	-- fifo_empty => fifo_in_empty(8),
2468	-- data_out =>crossbar_in_port(8),
2469	-- data_out_pulse =>crossbar_in_pulse(8),
2470	-- request(92) =>request_signal(92),
2471	-- request(93) =>request_signal(93),
2472	-- request(94) =>request_signal(94),
2473	-- request(95) =>request_signal(95),
2474	-- request(96) =>request_signal(96),
2475	-- request(97) =>request_signal(97),
2476	-- request(98) =>request_signal(98),
2477	-- request(99) =>request_signal(99),
2478	-- request(100) =>request_signal(100),
2479	-- request(101) =>request_signal(101),
2480	-- request(102) =>request_signal(102),
2481	-- request(103) =>request_signal(103),
2482	-- request(104) =>request_signal(104)
2483	--);
2484	--
2485	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2486	--GENERIC MAP(number_of_ports =>13)
2487	--PORT MAP(
2488	-- data_in => Port_in(9),
2489	-- data_in_en => data_in_en(9),
2490	-- reset => reset,
2491	-- clk =>clk,
2492	-- grant(1) => grant_signal(105),
2493	-- grant(2) => grant_signal(106),
2494	-- grant(3) => grant_signal(107),
2495	-- grant(4) => grant_signal(108),
2496	-- grant(5) => grant_signal(109),
2497	-- grant(6) => grant_signal(110),
2498	-- grant(7) => grant_signal(111),
2499	-- grant(8) => grant_signal(112),
2500	-- grant(9) => grant_signal(113),
2501	-- grant(10) => grant_signal(114),
2502	-- grant(11) => grant_signal(115),
2503	-- grant(12) => grant_signal(116),
2504	-- grant(13) => grant_signal(117),
2505	-- fifo_full =>fifo_in_full(9),
2506	-- priority_rotation => priority_rotation_signal(9),
2507	-- fifo_empty => fifo_in_empty(9),
2508	-- data_out =>crossbar_in_port(9),
2509	-- data_out_pulse =>crossbar_in_pulse(9),
2510	-- request(105) =>request_signal(105),
2511	-- request(106) =>request_signal(106),
2512	-- request(107) =>request_signal(107),
2513	-- request(108) =>request_signal(108),
2514	-- request(109) =>request_signal(109),
2515	-- request(110) =>request_signal(110),
2516	-- request(111) =>request_signal(111),
2517	-- request(112) =>request_signal(112),
2518	-- request(113) =>request_signal(113),
2519	-- request(114) =>request_signal(114),
2520	-- request(115) =>request_signal(115),
2521	-- request(116) =>request_signal(116),
2522	-- request(117) =>request_signal(117)
2523	--);
2524	--
2525	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2526	--GENERIC MAP(number_of_ports =>13)
2527	--PORT MAP(
2528	-- data_in => Port_in(10),
2529	-- data_in_en => data_in_en(10),
2530	-- reset => reset,
2531	-- clk =>clk,
2532	-- grant(1) => grant_signal(118),
2533	-- grant(2) => grant_signal(119),
2534	-- grant(3) => grant_signal(120),
2535	-- grant(4) => grant_signal(121),
2536	-- grant(5) => grant_signal(122),
2537	-- grant(6) => grant_signal(123),
2538	-- grant(7) => grant_signal(124),
2539	-- grant(8) => grant_signal(125),
2540	-- grant(9) => grant_signal(126),
2541	-- grant(10) => grant_signal(127),
2542	-- grant(11) => grant_signal(128),
2543	-- grant(12) => grant_signal(129),
2544	-- grant(13) => grant_signal(130),
2545	-- fifo_full =>fifo_in_full(10),
2546	-- priority_rotation => priority_rotation_signal(10),
2547	-- fifo_empty => fifo_in_empty(10),
2548	-- data_out =>crossbar_in_port(10),
2549	-- data_out_pulse =>crossbar_in_pulse(10),
2550	-- request(1) =>request_signal(118),
2551	-- request(2) =>request_signal(119),
2552	-- request(3) =>request_signal(120),
2553	-- request(4) =>request_signal(121),
2554	-- request(5) =>request_signal(122),
2555	-- request(6) =>request_signal(123),
2556	-- request(7) =>request_signal(124),
2557	-- request(8) =>request_signal(125),
2558	-- request(9) =>request_signal(126),
2559	-- request(10) =>request_signal(127),
2560	-- request(11) =>request_signal(128),
2561	-- request(12) =>request_signal(129),
2562	-- request(13) =>request_signal(130)
2563	--);
2564	--
2565	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2566	--GENERIC MAP(number_of_ports =>13)
2567	--PORT MAP(
2568	-- data_in => Port_in(11),
2569	-- data_in_en => data_in_en(11),
2570	-- reset => reset,
2571	-- clk =>clk,
2572	-- grant(1) => grant_signal(131),
2573	-- grant(2) => grant_signal(132),
2574	-- grant(3) => grant_signal(133),
2575	-- grant(4) => grant_signal(134),
2576	-- grant(5) => grant_signal(135),
2577	-- grant(6) => grant_signal(136),
2578	-- grant(7) => grant_signal(137),
2579	-- grant(8) => grant_signal(138),
2580	-- grant(9) => grant_signal(139),
2581	-- grant(10) => grant_signal(140),
2582	-- grant(11) => grant_signal(141),
2583	-- grant(12) => grant_signal(142),
2584	-- grant(13) => grant_signal(143),
2585	-- fifo_full =>fifo_in_full(11),
2586	-- priority_rotation => priority_rotation_signal(11),
2587	-- fifo_empty => fifo_in_empty(11),
2588	-- data_out =>crossbar_in_port(11),
2589	-- data_out_pulse =>crossbar_in_pulse(11),
2590	-- request(1) =>request_signal(131),
2591	-- request(2) =>request_signal(132),
2592	-- request(3) =>request_signal(133),
2593	-- request(4) =>request_signal(134),
2594	-- request(5) =>request_signal(135),
2595	-- request(6) =>request_signal(136),
2596	-- request(7) =>request_signal(137),
2597	-- request(8) =>request_signal(138),
2598	-- request(9) =>request_signal(139),
2599	-- request(10) =>request_signal(140),
2600	-- request(11) =>request_signal(141),
2601	-- request(12) =>request_signal(142),
2602	-- request(13) =>request_signal(143)
2603	--);
2604	--
2605	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2606	--GENERIC MAP(number_of_ports =>13)
2607	--PORT MAP(
2608	-- data_in => Port_in(12),
2609	-- data_in_en => data_in_en(12),
2610	-- reset => reset,
2611	-- clk =>clk,
2612	-- grant(1) => grant_signal(144),
2613	-- grant(2) => grant_signal(145),
2614	-- grant(3) => grant_signal(146),
2615	-- grant(4) => grant_signal(147),
2616	-- grant(5) => grant_signal(148),
2617	-- grant(6) => grant_signal(149),
2618	-- grant(7) => grant_signal(150),
2619	-- grant(8) => grant_signal(151),
2620	-- grant(9) => grant_signal(152),
2621	-- grant(10) => grant_signal(153),
2622	-- grant(11) => grant_signal(154),
2623	-- grant(12) => grant_signal(155),
2624	-- grant(13) => grant_signal(156),
2625	-- fifo_full =>fifo_in_full(12),
2626	-- priority_rotation => priority_rotation_signal(12),
2627	-- fifo_empty => fifo_in_empty(12),
2628	-- data_out =>crossbar_in_port(12),
2629	-- data_out_pulse =>crossbar_in_pulse(12),
2630	-- request(1) =>request_signal(144),
2631	-- request(2) =>request_signal(145),
2632	-- request(3) =>request_signal(146),
2633	-- request(4) =>request_signal(147),
2634	-- request(5) =>request_signal(148),
2635	-- request(6) =>request_signal(149),
2636	-- request(7) =>request_signal(150),
2637	-- request(8) =>request_signal(151),
2638	-- request(9) =>request_signal(152),
2639	-- request(10) =>request_signal(153),
2640	-- request(11) =>request_signal(154),
2641	-- request(12) =>request_signal(155),
2642	-- request(13) =>request_signal(156)
2643	--);
2644	--
2645	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2646	--GENERIC MAP(number_of_ports =>13)
2647	--PORT MAP(
2648	-- data_in => Port_in(13),
2649	-- data_in_en => data_in_en(13),
2650	-- reset => reset,
2651	-- clk =>clk,
2652	-- grant(1) => grant_signal(157),
2653	-- grant(2) => grant_signal(158),
2654	-- grant(3) => grant_signal(159),
2655	-- grant(4) => grant_signal(160),
2656	-- grant(5) => grant_signal(161),
2657	-- grant(6) => grant_signal(162),
2658	-- grant(7) => grant_signal(163),
2659	-- grant(8) => grant_signal(164),
2660	-- grant(9) => grant_signal(165),
2661	-- grant(10) => grant_signal(166),
2662	-- grant(11) => grant_signal(167),
2663	-- grant(12) => grant_signal(168),
2664	-- grant(13) => grant_signal(169),
2665	-- fifo_full =>fifo_in_full(13),
2666	-- priority_rotation => priority_rotation_signal(13),
2667	-- fifo_empty => fifo_in_empty(13),
2668	-- data_out =>crossbar_in_port(13),
2669	-- data_out_pulse =>crossbar_in_pulse(13),
2670	-- request(1) =>request_signal(157),
2671	-- request(2) =>request_signal(158),
2672	-- request(3) =>request_signal(159),
2673	-- request(4) =>request_signal(160),
2674	-- request(5) =>request_signal(161),
2675	-- request(6) =>request_signal(162),
2676	-- request(7) =>request_signal(163),
2677	-- request(8) =>request_signal(164),
2678	-- request(9) =>request_signal(165),
2679	-- request(10) =>request_signal(166),
2680	-- request(11) =>request_signal(167),
2681	-- request(12) =>request_signal(168),
2682	-- request(13) =>request_signal(169)
2683	--);
2684	--
2685	--end generate switch13x13;
2686	--
2687	--
2688	---- switch 14 ports
2689	--switch14x14 : if number_of_ports = 14 generate
2690	--
2691	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2692	--GENERIC MAP(number_of_ports =>14)
2693	--PORT MAP(
2694	-- data_in => Port_in(1),
2695	-- data_in_en => data_in_en(1),
2696	-- reset => reset,
2697	-- clk =>clk,
2698	-- grant(1) => grant_signal(1),
2699	-- grant(2) => grant_signal(2),
2700	-- grant(3) => grant_signal(3),
2701	-- grant(4) => grant_signal(4),
2702	-- grant(5) => grant_signal(5),
2703	-- grant(6) => grant_signal(6),
2704	-- grant(7) => grant_signal(7),
2705	-- grant(8) => grant_signal(8),
2706	-- grant(9) => grant_signal(9),
2707	-- grant(10) => grant_signal(10),
2708	-- grant(11) => grant_signal(11),
2709	-- grant(12) => grant_signal(12),
2710	-- grant(13) => grant_signal(13),
2711	-- grant(14) => grant_signal(14),
2712	-- fifo_full =>fifo_in_full(1),
2713	-- priority_rotation => priority_rotation_signal(1),
2714	-- fifo_empty => fifo_in_empty(1),
2715	-- data_out =>crossbar_in_port(1),
2716	-- data_out_pulse =>crossbar_in_pulse(1),
2717	-- request(1) =>request_signal(1),
2718	-- request(2) =>request_signal(2),
2719	-- request(3) =>request_signal(3),
2720	-- request(4) =>request_signal(4),
2721	-- request(5) =>request_signal(5),
2722	-- request(6) =>request_signal(6),
2723	-- request(7) =>request_signal(7),
2724	-- request(8) =>request_signal(8),
2725	-- request(9) =>request_signal(9),
2726	-- request(10) =>request_signal(10),
2727	-- request(11) =>request_signal(11),
2728	-- request(12) =>request_signal(12),
2729	-- request(13) =>request_signal(13),
2730	-- request(14) =>request_signal(14)
2731	--);
2732	--
2733	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2734	--GENERIC MAP(number_of_ports =>14)
2735	--PORT MAP(
2736	-- data_in => Port_in(2),
2737	-- data_in_en => data_in_en(2),
2738	-- reset => reset,
2739	-- clk =>clk,
2740	-- grant(1) => grant_signal(15),
2741	-- grant(2) => grant_signal(16),
2742	-- grant(3) => grant_signal(17),
2743	-- grant(4) => grant_signal(18),
2744	-- grant(5) => grant_signal(19),
2745	-- grant(6) => grant_signal(20),
2746	-- grant(7) => grant_signal(21),
2747	-- grant(8) => grant_signal(22),
2748	-- grant(9) => grant_signal(23),
2749	-- grant(10) => grant_signal(24),
2750	-- grant(11) => grant_signal(25),
2751	-- grant(12) => grant_signal(26),
2752	-- grant(13) => grant_signal(27),
2753	-- grant(14) => grant_signal(28),
2754	-- fifo_full =>fifo_in_full(2),
2755	-- priority_rotation => priority_rotation_signal(2),
2756	-- fifo_empty => fifo_in_empty(2),
2757	-- data_out =>crossbar_in_port(2),
2758	-- data_out_pulse =>crossbar_in_pulse(2),
2759	-- request(1) =>request_signal(15),
2760	-- request(2) =>request_signal(16),
2761	-- request(3) =>request_signal(17),
2762	-- request(4) =>request_signal(18),
2763	-- request(5) =>request_signal(19),
2764	-- request(6) =>request_signal(20),
2765	-- request(7) =>request_signal(21),
2766	-- request(8) =>request_signal(22),
2767	-- request(9) =>request_signal(23),
2768	-- request(10) =>request_signal(24),
2769	-- request(11) =>request_signal(25),
2770	-- request(12) =>request_signal(26),
2771	-- request(13) =>request_signal(27),
2772	-- request(14) =>request_signal(28)
2773	--);
2774	--
2775	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2776	--GENERIC MAP(number_of_ports =>14)
2777	--PORT MAP(
2778	-- data_in => Port_in(3),
2779	-- data_in_en => data_in_en(3),
2780	-- reset => reset,
2781	-- clk =>clk,
2782	-- grant(1) => grant_signal(29),
2783	-- grant(2) => grant_signal(30),
2784	-- grant(3) => grant_signal(31),
2785	-- grant(4) => grant_signal(32),
2786	-- grant(5) => grant_signal(33),
2787	-- grant(6) => grant_signal(34),
2788	-- grant(7) => grant_signal(35),
2789	-- grant(8) => grant_signal(36),
2790	-- grant(9) => grant_signal(37),
2791	-- grant(10)=> grant_signal(38),
2792	-- grant(11) => grant_signal(39),
2793	-- grant(12) => grant_signal(40),
2794	-- grant(13) => grant_signal(41),
2795	-- grant(14) => grant_signal(42),
2796	-- fifo_full =>fifo_in_full(3),
2797	-- priority_rotation => priority_rotation_signal(3),
2798	-- fifo_empty => fifo_in_empty(3),
2799	-- data_out =>crossbar_in_port(3),
2800	-- data_out_pulse =>crossbar_in_pulse(3),
2801	-- request(01) =>request_signal(29),
2802	-- request(02) =>request_signal(30),
2803	-- request(03) =>request_signal(31),
2804	-- request(04) =>request_signal(32),
2805	-- request(05) =>request_signal(33),
2806	-- request(06) =>request_signal(34),
2807	-- request(07) =>request_signal(35),
2808	-- request(08) =>request_signal(36),
2809	-- request(09) =>request_signal(37),
2810	-- request(10) =>request_signal(38),
2811	-- request(11) =>request_signal(39),
2812	-- request(12) =>request_signal(40),
2813	-- request(13) =>request_signal(41),
2814	-- request(14) =>request_signal(42)
2815	--);
2816	--
2817	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2818	--GENERIC MAP(number_of_ports =>14)
2819	--PORT MAP(
2820	-- data_in => Port_in(4),
2821	-- data_in_en => data_in_en(4),
2822	-- reset => reset,
2823	-- clk =>clk,
2824	-- grant(01) => grant_signal(43),
2825	-- grant(02) => grant_signal(44),
2826	-- grant(03) => grant_signal(45),
2827	-- grant(04) => grant_signal(46),
2828	-- grant(05) => grant_signal(47),
2829	-- grant(06) => grant_signal(48),
2830	-- grant(07) => grant_signal(49),
2831	-- grant(08) => grant_signal(50),
2832	-- grant(09) => grant_signal(51),
2833	-- grant(10) => grant_signal(52),
2834	-- grant(11) => grant_signal(53),
2835	-- grant(12) => grant_signal(54),
2836	-- grant(13) => grant_signal(55),
2837	-- grant(14) => grant_signal(56),
2838	-- fifo_full =>fifo_in_full(4),
2839	-- priority_rotation => priority_rotation_signal(4),
2840	-- fifo_empty => fifo_in_empty(4),
2841	-- data_out =>crossbar_in_port(4),
2842	-- data_out_pulse =>crossbar_in_pulse(4),
2843	-- request(01) =>request_signal(43),
2844	-- request(02) =>request_signal(44),
2845	-- request(03) =>request_signal(45),
2846	-- request(04) =>request_signal(46),
2847	-- request(05) =>request_signal(47),
2848	-- request(06) =>request_signal(48),
2849	-- request(07) =>request_signal(49),
2850	-- request(08) =>request_signal(50),
2851	-- request(09) =>request_signal(51),
2852	-- request(10) =>request_signal(52),
2853	-- request(11) =>request_signal(53),
2854	-- request(12) =>request_signal(54),
2855	-- request(13) =>request_signal(55),
2856	-- request(14) =>request_signal(56)
2857	--);
2858	--
2859	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2860	--GENERIC MAP(number_of_ports =>14)
2861	--PORT MAP(
2862	-- data_in => Port_in(5),
2863	-- data_in_en => data_in_en(5),
2864	-- reset => reset,
2865	-- clk =>clk,
2866	-- grant(01) => grant_signal(57),
2867	-- grant(02) => grant_signal(58),
2868	-- grant(03) => grant_signal(59),
2869	-- grant(04) => grant_signal(60),
2870	-- grant(05) => grant_signal(61),
2871	-- grant(06) => grant_signal(62),
2872	-- grant(07) => grant_signal(63),
2873	-- grant(08) => grant_signal(64),
2874	-- grant(09) => grant_signal(65),
2875	-- grant(10) => grant_signal(66),
2876	-- grant(11) => grant_signal(67),
2877	-- grant(12) => grant_signal(68),
2878	-- grant(13) => grant_signal(69),
2879	-- grant(14) => grant_signal(70),
2880	-- fifo_full =>fifo_in_full(5),
2881	-- priority_rotation => priority_rotation_signal(5),
2882	-- fifo_empty => fifo_in_empty(5),
2883	-- data_out =>crossbar_in_port(5),
2884	-- data_out_pulse =>crossbar_in_pulse(5),
2885	-- request(01) =>request_signal(57),
2886	-- request(02) =>request_signal(58),
2887	-- request(03) =>request_signal(59),
2888	-- request(04) =>request_signal(60),
2889	-- request(05) =>request_signal(61),
2890	-- request(06) =>request_signal(62),
2891	-- request(07) =>request_signal(63),
2892	-- request(08) =>request_signal(64),
2893	-- request(09) =>request_signal(65),
2894	-- request(10) =>request_signal(66),
2895	-- request(11) =>request_signal(67),
2896	-- request(12) =>request_signal(68),
2897	-- request(13) =>request_signal(69),
2898	-- request(14) =>request_signal(70)
2899	--);
2900	--
2901	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2902	--GENERIC MAP(number_of_ports =>14)
2903	--PORT MAP(
2904	-- data_in => Port_in(6),
2905	-- data_in_en => data_in_en(6),
2906	-- reset => reset,
2907	-- clk =>clk,
2908	-- grant(01) => grant_signal(71),
2909	-- grant(02) => grant_signal(72),
2910	-- grant(03) => grant_signal(73),
2911	-- grant(04) => grant_signal(74),
2912	-- grant(05) => grant_signal(75),
2913	-- grant(06) => grant_signal(76),
2914	-- grant(07) => grant_signal(77),
2915	-- grant(08) => grant_signal(78),
2916	-- grant(09) => grant_signal(79),
2917	-- grant(10) => grant_signal(80),
2918	-- grant(11) => grant_signal(81),
2919	-- grant(12) => grant_signal(82),
2920	-- grant(13) => grant_signal(83),
2921	-- grant(14) => grant_signal(84),
2922	-- fifo_full =>fifo_in_full(6),
2923	-- priority_rotation => priority_rotation_signal(6),
2924	-- fifo_empty => fifo_in_empty(6),
2925	-- data_out =>crossbar_in_port(6),
2926	-- data_out_pulse =>crossbar_in_pulse(6),
2927	-- request(01) =>request_signal(71),
2928	-- request(02) =>request_signal(72),
2929	-- request(03) =>request_signal(73),
2930	-- request(04) =>request_signal(74),
2931	-- request(05) =>request_signal(75),
2932	-- request(06) =>request_signal(76),
2933	-- request(07) =>request_signal(77),
2934	-- request(08) =>request_signal(78),
2935	-- request(09) =>request_signal(79),
2936	-- request(10) =>request_signal(80),
2937	-- request(11) =>request_signal(81),
2938	-- request(12) =>request_signal(82),
2939	-- request(13) =>request_signal(83),
2940	-- request(14) =>request_signal(84)
2941	--);
2942	--
2943	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2944	--GENERIC MAP(number_of_ports =>14)
2945	--PORT MAP(
2946	-- data_in => Port_in(7),
2947	-- data_in_en => data_in_en(7),
2948	-- reset => reset,
2949	-- clk =>clk,
2950	-- grant(01) => grant_signal(85),
2951	-- grant(02) => grant_signal(86),
2952	-- grant(03) => grant_signal(87),
2953	-- grant(04) => grant_signal(88),
2954	-- grant(05) => grant_signal(89),
2955	-- grant(06) => grant_signal(90),
2956	-- grant(07) => grant_signal(91),
2957	-- grant(08) => grant_signal(92),
2958	-- grant(09) => grant_signal(93),
2959	-- grant(10) => grant_signal(94),
2960	-- grant(11) => grant_signal(95),
2961	-- grant(12) => grant_signal(96),
2962	-- grant(13) => grant_signal(97),
2963	-- grant(14) => grant_signal(98),
2964	-- fifo_full =>fifo_in_full(7),
2965	-- priority_rotation => priority_rotation_signal(7),
2966	-- fifo_empty => fifo_in_empty(7),
2967	-- data_out =>crossbar_in_port(7),
2968	-- data_out_pulse =>crossbar_in_pulse(7),
2969	-- request(01) =>request_signal(85),
2970	-- request(02) =>request_signal(86),
2971	-- request(03) =>request_signal(87),
2972	-- request(04) =>request_signal(88),
2973	-- request(05) =>request_signal(89),
2974	-- request(06) =>request_signal(90),
2975	-- request(07) =>request_signal(91),
2976	-- request(08) =>request_signal(92),
2977	-- request(09) =>request_signal(93),
2978	-- request(10) =>request_signal(94),
2979	-- request(11) =>request_signal(95),
2980	-- request(12) =>request_signal(96),
2981	-- request(13) =>request_signal(97),
2982	-- request(14) =>request_signal(98)
2983	--);
2984	--
2985	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2986	--GENERIC MAP(number_of_ports =>14)
2987	--PORT MAP(
2988	-- data_in => Port_in(8),
2989	-- data_in_en => data_in_en(8),
2990	-- reset => reset,
2991	-- clk =>clk,
2992	-- grant(01) => grant_signal(99),
2993	-- grant(02) => grant_signal(100),
2994	-- grant(03) => grant_signal(101),
2995	-- grant(04) => grant_signal(102),
2996	-- grant(05) => grant_signal(103),
2997	-- grant(06) => grant_signal(104),
2998	-- grant(07) => grant_signal(105),
2999	-- grant(08) => grant_signal(106),
3000	-- grant(09) => grant_signal(107),
3001	-- grant(10) => grant_signal(108),
3002	-- grant(11) => grant_signal(109),
3003	-- grant(12) => grant_signal(110),
3004	-- grant(13) => grant_signal(111),
3005	-- grant(14) => grant_signal(112),
3006	-- fifo_full =>fifo_in_full(8),
3007	-- priority_rotation => priority_rotation_signal(8),
3008	-- fifo_empty => fifo_in_empty(8),
3009	-- data_out =>crossbar_in_port(8),
3010	-- data_out_pulse =>crossbar_in_pulse(8),
3011	-- request(1) =>request_signal(99),
3012	-- request(2) =>request_signal(100),
3013	-- request(3) =>request_signal(101),
3014	-- request(4) =>request_signal(102),
3015	-- request(5) =>request_signal(103),
3016	-- request(6) =>request_signal(104),
3017	-- request(7) =>request_signal(105),
3018	-- request(8) =>request_signal(106),
3019	-- request(9) =>request_signal(107),
3020	-- request(10) =>request_signal(108),
3021	-- request(11) =>request_signal(109),
3022	-- request(12) =>request_signal(110),
3023	-- request(13) =>request_signal(111),
3024	-- request(14) =>request_signal(112)
3025	--);
3026	--
3027	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3028	--GENERIC MAP(number_of_ports =>14)
3029	--PORT MAP(
3030	-- data_in => Port_in(9),
3031	-- data_in_en => data_in_en(9),
3032	-- reset => reset,
3033	-- clk =>clk,
3034	-- grant(1) => grant_signal(113),
3035	-- grant(2) => grant_signal(114),
3036	-- grant(3) => grant_signal(115),
3037	-- grant(4) => grant_signal(116),
3038	-- grant(5) => grant_signal(117),
3039	-- grant(6) => grant_signal(118),
3040	-- grant(7) => grant_signal(119),
3041	-- grant(8) => grant_signal(120),
3042	-- grant(9) => grant_signal(121),
3043	-- grant(10) => grant_signal(122),
3044	-- grant(11) => grant_signal(123),
3045	-- grant(12) => grant_signal(124),
3046	-- grant(13) => grant_signal(125),
3047	-- grant(14) => grant_signal(126),
3048	-- fifo_full =>fifo_in_full(9),
3049	-- priority_rotation => priority_rotation_signal(9),
3050	-- fifo_empty => fifo_in_empty(9),
3051	-- data_out =>crossbar_in_port(9),
3052	-- data_out_pulse =>crossbar_in_pulse(9),
3053	-- request(1) =>request_signal(113),
3054	-- request(2) =>request_signal(114),
3055	-- request(3) =>request_signal(115),
3056	-- request(4) =>request_signal(116),
3057	-- request(5) =>request_signal(117),
3058	-- request(6) =>request_signal(118),
3059	-- request(7) =>request_signal(119),
3060	-- request(8) =>request_signal(120),
3061	-- request(9) =>request_signal(121),
3062	-- request(10) =>request_signal(122),
3063	-- request(11) =>request_signal(123),
3064	-- request(12) =>request_signal(124),
3065	-- request(13) =>request_signal(125),
3066	-- request(14) =>request_signal(126)
3067	--);
3068	--
3069	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3070	--GENERIC MAP(number_of_ports =>14)
3071	--PORT MAP(
3072	-- data_in => Port_in(10),
3073	-- data_in_en => data_in_en(10),
3074	-- reset => reset,
3075	-- clk =>clk,
3076	-- grant(1) => grant_signal(127),
3077	-- grant(2) => grant_signal(128),
3078	-- grant(3) => grant_signal(129),
3079	-- grant(4) => grant_signal(130),
3080	-- grant(5) => grant_signal(131),
3081	-- grant(6) => grant_signal(132),
3082	-- grant(7) => grant_signal(133),
3083	-- grant(8) => grant_signal(134),
3084	-- grant(9) => grant_signal(135),
3085	-- grant(10) => grant_signal(136),
3086	-- grant(11) => grant_signal(137),
3087	-- grant(12) => grant_signal(138),
3088	-- grant(13) => grant_signal(139),
3089	-- grant(14) => grant_signal(140),
3090	-- fifo_full =>fifo_in_full(10),
3091	-- priority_rotation => priority_rotation_signal(10),
3092	-- fifo_empty => fifo_in_empty(10),
3093	-- data_out =>crossbar_in_port(10),
3094	-- data_out_pulse =>crossbar_in_pulse(10),
3095	-- request(1) =>request_signal(127),
3096	-- request(2) =>request_signal(128),
3097	-- request(3) =>request_signal(129),
3098	-- request(4) =>request_signal(130),
3099	-- request(5) =>request_signal(131),
3100	-- request(6) =>request_signal(132),
3101	-- request(7) =>request_signal(133),
3102	-- request(8) =>request_signal(134),
3103	-- request(9) =>request_signal(135),
3104	-- request(10) =>request_signal(136),
3105	-- request(11) =>request_signal(137),
3106	-- request(12) =>request_signal(138),
3107	-- request(13) =>request_signal(139),
3108	-- request(14) =>request_signal(140)
3109	--);
3110	--
3111	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3112	--GENERIC MAP(number_of_ports =>14)
3113	--PORT MAP(
3114	-- data_in => Port_in(11),
3115	-- data_in_en => data_in_en(11),
3116	-- reset => reset,
3117	-- clk =>clk,
3118	-- grant(1) => grant_signal(141),
3119	-- grant(2) => grant_signal(142),
3120	-- grant(3) => grant_signal(143),
3121	-- grant(4) => grant_signal(144),
3122	-- grant(5) => grant_signal(145),
3123	-- grant(6) => grant_signal(146),
3124	-- grant(7) => grant_signal(147),
3125	-- grant(8) => grant_signal(148),
3126	-- grant(9) => grant_signal(149),
3127	-- grant(10) => grant_signal(150),
3128	-- grant(11) => grant_signal(151),
3129	-- grant(12) => grant_signal(152),
3130	-- grant(13) => grant_signal(153),
3131	-- grant(14) => grant_signal(154),
3132	-- fifo_full =>fifo_in_full(11),
3133	-- priority_rotation => priority_rotation_signal(11),
3134	-- fifo_empty => fifo_in_empty(11),
3135	-- data_out =>crossbar_in_port(11),
3136	-- data_out_pulse =>crossbar_in_pulse(11),
3137	-- request(1) =>request_signal(141),
3138	-- request(2) =>request_signal(142),
3139	-- request(3) =>request_signal(143),
3140	-- request(4) =>request_signal(144),
3141	-- request(5) =>request_signal(145),
3142	-- request(6) =>request_signal(146),
3143	-- request(7) =>request_signal(147),
3144	-- request(8) =>request_signal(148),
3145	-- request(9) =>request_signal(149),
3146	-- request(10) =>request_signal(150),
3147	-- request(11) =>request_signal(151),
3148	-- request(12) =>request_signal(152),
3149	-- request(13) =>request_signal(153),
3150	-- request(14) =>request_signal(154)
3151	--);
3152	--
3153	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3154	--GENERIC MAP(number_of_ports =>14)
3155	--PORT MAP(
3156	-- data_in => Port_in(12),
3157	-- data_in_en => data_in_en(12),
3158	-- reset => reset,
3159	-- clk =>clk,
3160	-- grant(1) => grant_signal(155),
3161	-- grant(2) => grant_signal(156),
3162	-- grant(3) => grant_signal(157),
3163	-- grant(4) => grant_signal(158),
3164	-- grant(5) => grant_signal(159),
3165	-- grant(6) => grant_signal(160),
3166	-- grant(7) => grant_signal(161),
3167	-- grant(8) => grant_signal(162),
3168	-- grant(9) => grant_signal(163),
3169	-- grant(10) => grant_signal(164),
3170	-- grant(11) => grant_signal(165),
3171	-- grant(12) => grant_signal(166),
3172	-- grant(13) => grant_signal(167),
3173	-- grant(14) => grant_signal(168),
3174	-- fifo_full =>fifo_in_full(12),
3175	-- priority_rotation => priority_rotation_signal(12),
3176	-- fifo_empty => fifo_in_empty(12),
3177	-- data_out =>crossbar_in_port(12),
3178	-- data_out_pulse =>crossbar_in_pulse(12),
3179	-- request(1) =>request_signal(155),
3180	-- request(2) =>request_signal(156),
3181	-- request(3) =>request_signal(157),
3182	-- request(4) =>request_signal(158),
3183	-- request(5) =>request_signal(159),
3184	-- request(6) =>request_signal(160),
3185	-- request(7) =>request_signal(161),
3186	-- request(8) =>request_signal(162),
3187	-- request(9) =>request_signal(163),
3188	-- request(10) =>request_signal(164),
3189	-- request(11) =>request_signal(165),
3190	-- request(12) =>request_signal(166),
3191	-- request(13) =>request_signal(167),
3192	-- request(14) =>request_signal(168)
3193	--);
3194	--
3195	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3196	--GENERIC MAP(number_of_ports =>14)
3197	--PORT MAP(
3198	-- data_in => Port_in(13),
3199	-- data_in_en => data_in_en(13),
3200	-- reset => reset,
3201	-- clk =>clk,
3202	-- grant(1) => grant_signal(169),
3203	-- grant(2) => grant_signal(170),
3204	-- grant(3) => grant_signal(171),
3205	-- grant(4) => grant_signal(172),
3206	-- grant(5) => grant_signal(173),
3207	-- grant(6) => grant_signal(174),
3208	-- grant(7) => grant_signal(175),
3209	-- grant(8) => grant_signal(176),
3210	-- grant(9) => grant_signal(177),
3211	-- grant(10) => grant_signal(178),
3212	-- grant(11) => grant_signal(179),
3213	-- grant(12) => grant_signal(180),
3214	-- grant(13) => grant_signal(181),
3215	-- grant(14) => grant_signal(182),
3216	-- fifo_full =>fifo_in_full(13),
3217	-- priority_rotation => priority_rotation_signal(13),
3218	-- fifo_empty => fifo_in_empty(13),
3219	-- data_out =>crossbar_in_port(13),
3220	-- data_out_pulse =>crossbar_in_pulse(13),
3221	-- request(1) =>request_signal(169),
3222	-- request(2) =>request_signal(170),
3223	-- request(3) =>request_signal(171),
3224	-- request(4) =>request_signal(172),
3225	-- request(5) =>request_signal(173),
3226	-- request(6) =>request_signal(174),
3227	-- request(7) =>request_signal(175),
3228	-- request(8) =>request_signal(176),
3229	-- request(9) =>request_signal(177),
3230	-- request(10) =>request_signal(178),
3231	-- request(11) =>request_signal(179),
3232	-- request(12) =>request_signal(180),
3233	-- request(13) =>request_signal(181),
3234	-- request(14) =>request_signal(182)
3235	--);
3236	--
3237	--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3238	--GENERIC MAP(number_of_ports =>14)
3239	--PORT MAP(
3240	-- data_in => Port_in(14),
3241	-- data_in_en => data_in_en(14),
3242	-- reset => reset,
3243	-- clk =>clk,
3244	-- grant(1) => grant_signal(183),
3245	-- grant(2) => grant_signal(184),
3246	-- grant(3) => grant_signal(185),
3247	-- grant(4) => grant_signal(186),
3248	-- grant(5) => grant_signal(187),
3249	-- grant(6) => grant_signal(188),
3250	-- grant(7) => grant_signal(189),
3251	-- grant(8) => grant_signal(190),
3252	-- grant(9) => grant_signal(191),
3253	-- grant(10) => grant_signal(192),
3254	-- grant(11) => grant_signal(193),
3255	-- grant(12) => grant_signal(194),
3256	-- grant(13) => grant_signal(195),
3257	-- grant(14) => grant_signal(196),
3258	-- fifo_full =>fifo_in_full(14),
3259	-- priority_rotation => priority_rotation_signal(14),
3260	-- fifo_empty => fifo_in_empty(14),
3261	-- data_out =>crossbar_in_port(14),
3262	-- data_out_pulse =>crossbar_in_pulse(14),
3263	-- request(1) =>request_signal(183),
3264	-- request(2) =>request_signal(184),
3265	-- request(3) =>request_signal(185),
3266	-- request(4) =>request_signal(186),
3267	-- request(5) =>request_signal(187),
3268	-- request(6) =>request_signal(188),
3269	-- request(7) =>request_signal(189),
3270	-- request(8) =>request_signal(190),
3271	-- request(9) =>request_signal(191),
3272	-- request(10) =>request_signal(192),
3273	-- request(11) =>request_signal(193),
3274	-- request(12) =>request_signal(194),
3275	-- request(13) =>request_signal(195),
3276	-- request(14) =>request_signal(196)
3277	--);
3278	--
3279	--end generate switch14x14;
3280	--
3281	--
3282	---- switch 15 ports
3283	--switch15x15 : if number_of_ports = 15 generate
3284	--
3285	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3286	--GENERIC MAP(number_of_ports =>15)
3287	--PORT MAP(
3288	-- data_in => Port_in(1),
3289	-- data_in_en => data_in_en(1),
3290	-- reset => reset,
3291	-- clk =>clk,
3292	-- grant(1) => grant_signal(1),
3293	-- grant(2) => grant_signal(2),
3294	-- grant(3) => grant_signal(3),
3295	-- grant(4) => grant_signal(4),
3296	-- grant(5) => grant_signal(5),
3297	-- grant(6) => grant_signal(6),
3298	-- grant(7) => grant_signal(7),
3299	-- grant(8) => grant_signal(8),
3300	-- grant(9) => grant_signal(9),
3301	-- grant(10) => grant_signal(10),
3302	-- grant(11) => grant_signal(11),
3303	-- grant(12) => grant_signal(12),
3304	-- grant(13) => grant_signal(13),
3305	-- grant(14) => grant_signal(14),
3306	-- grant(15) => grant_signal(15),
3307	-- fifo_full =>fifo_in_full(1),
3308	-- priority_rotation => priority_rotation_signal(1),
3309	-- fifo_empty => fifo_in_empty(1),
3310	-- data_out =>crossbar_in_port(1),
3311	-- data_out_pulse =>crossbar_in_pulse(1),
3312	-- request(1) =>request_signal(1),
3313	-- request(2) =>request_signal(2),
3314	-- request(3) =>request_signal(3),
3315	-- request(4) =>request_signal(4),
3316	-- request(5) =>request_signal(5),
3317	-- request(6) =>request_signal(6),
3318	-- request(7) =>request_signal(7),
3319	-- request(8) =>request_signal(8),
3320	-- request(9) =>request_signal(9),
3321	-- request(10) =>request_signal(10),
3322	-- request(11) =>request_signal(11),
3323	-- request(12) =>request_signal(12),
3324	-- request(13) =>request_signal(13),
3325	-- request(14) =>request_signal(14),
3326	-- request(15) =>request_signal(15)
3327	--);
3328	--
3329	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3330	--GENERIC MAP(number_of_ports =>15)
3331	--PORT MAP(
3332	-- data_in => Port_in(2),
3333	-- data_in_en => data_in_en(2),
3334	-- reset => reset,
3335	-- clk =>clk,
3336	-- grant(16) => grant_signal(16),
3337	-- grant(17) => grant_signal(17),
3338	-- grant(18) => grant_signal(18),
3339	-- grant(19) => grant_signal(19),
3340	-- grant(20) => grant_signal(20),
3341	-- grant(21) => grant_signal(21),
3342	-- grant(22) => grant_signal(22),
3343	-- grant(23) => grant_signal(23),
3344	-- grant(24) => grant_signal(24),
3345	-- grant(25) => grant_signal(25),
3346	-- grant(26) => grant_signal(26),
3347	-- grant(27) => grant_signal(27),
3348	-- grant(28) => grant_signal(28),
3349	-- grant(29) => grant_signal(29),
3350	-- grant(30) => grant_signal(30),
3351	-- fifo_full =>fifo_in_full(2),
3352	-- priority_rotation => priority_rotation_signal(2),
3353	-- fifo_empty => fifo_in_empty(2),
3354	-- data_out =>crossbar_in_port(2),
3355	-- data_out_pulse =>crossbar_in_pulse(2),
3356	-- request(16) =>request_signal(16),
3357	-- request(17) =>request_signal(17),
3358	-- request(18) =>request_signal(18),
3359	-- request(19) =>request_signal(19),
3360	-- request(20) =>request_signal(20),
3361	-- request(21) =>request_signal(21),
3362	-- request(22) =>request_signal(22),
3363	-- request(23) =>request_signal(23),
3364	-- request(24) =>request_signal(24),
3365	-- request(25) =>request_signal(25),
3366	-- request(26) =>request_signal(26),
3367	-- request(27) =>request_signal(27),
3368	-- request(28) =>request_signal(28),
3369	-- request(29) =>request_signal(29),
3370	-- request(30) =>request_signal(30)
3371	--);
3372	--
3373	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3374	--GENERIC MAP(number_of_ports =>15)
3375	--PORT MAP(
3376	-- data_in => Port_in(3),
3377	-- data_in_en => data_in_en(3),
3378	-- reset => reset,
3379	-- clk =>clk,
3380	-- grant(31) => grant_signal(31),
3381	-- grant(32) => grant_signal(32),
3382	-- grant(33) => grant_signal(33),
3383	-- grant(34) => grant_signal(34),
3384	-- grant(35) => grant_signal(35),
3385	-- grant(36) => grant_signal(36),
3386	-- grant(37) => grant_signal(37),
3387	-- grant(38) => grant_signal(38),
3388	-- grant(39) => grant_signal(39),
3389	-- grant(40) => grant_signal(40),
3390	-- grant(41) => grant_signal(41),
3391	-- grant(42) => grant_signal(42),
3392	-- grant(43) => grant_signal(43),
3393	-- grant(44) => grant_signal(44),
3394	-- grant(45) => grant_signal(45),
3395	-- fifo_full =>fifo_in_full(3),
3396	-- priority_rotation => priority_rotation_signal(3),
3397	-- fifo_empty => fifo_in_empty(3),
3398	-- data_out =>crossbar_in_port(3),
3399	-- data_out_pulse =>crossbar_in_pulse(3),
3400	-- request(31) =>request_signal(31),
3401	-- request(32) =>request_signal(32),
3402	-- request(33) =>request_signal(33),
3403	-- request(34) =>request_signal(34),
3404	-- request(35) =>request_signal(35),
3405	-- request(36) =>request_signal(36),
3406	-- request(37) =>request_signal(37),
3407	-- request(38) =>request_signal(38),
3408	-- request(39) =>request_signal(39),
3409	-- request(40) =>request_signal(40),
3410	-- request(41) =>request_signal(41),
3411	-- request(42) =>request_signal(42),
3412	-- request(43) =>request_signal(43),
3413	-- request(44) =>request_signal(44),
3414	-- request(45) =>request_signal(45)
3415	--);
3416	--
3417	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3418	--GENERIC MAP(number_of_ports =>15)
3419	--PORT MAP(
3420	-- data_in => Port_in(4),
3421	-- data_in_en => data_in_en(4),
3422	-- reset => reset,
3423	-- clk =>clk,
3424	-- grant(46) => grant_signal(46),
3425	-- grant(47) => grant_signal(47),
3426	-- grant(48) => grant_signal(48),
3427	-- grant(49) => grant_signal(49),
3428	-- grant(50) => grant_signal(50),
3429	-- grant(51) => grant_signal(51),
3430	-- grant(52) => grant_signal(52),
3431	-- grant(53) => grant_signal(53),
3432	-- grant(54) => grant_signal(54),
3433	-- grant(55) => grant_signal(55),
3434	-- grant(56) => grant_signal(56),
3435	-- grant(57) => grant_signal(57),
3436	-- grant(58) => grant_signal(58),
3437	-- grant(59) => grant_signal(59),
3438	-- grant(60) => grant_signal(60),
3439	-- fifo_full =>fifo_in_full(4),
3440	-- priority_rotation => priority_rotation_signal(4),
3441	-- fifo_empty => fifo_in_empty(4),
3442	-- data_out =>crossbar_in_port(4),
3443	-- data_out_pulse =>crossbar_in_pulse(4),
3444	-- request(46) =>request_signal(46),
3445	-- request(47) =>request_signal(47),
3446	-- request(48) =>request_signal(48),
3447	-- request(49) =>request_signal(49),
3448	-- request(50) =>request_signal(50),
3449	-- request(51) =>request_signal(51),
3450	-- request(52) =>request_signal(52),
3451	-- request(53) =>request_signal(53),
3452	-- request(54) =>request_signal(54),
3453	-- request(55) =>request_signal(55),
3454	-- request(56) =>request_signal(56),
3455	-- request(57) =>request_signal(57),
3456	-- request(58) =>request_signal(58),
3457	-- request(59) =>request_signal(59),
3458	-- request(60) =>request_signal(60)
3459	--);
3460	--
3461	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3462	--GENERIC MAP(number_of_ports =>15)
3463	--PORT MAP(
3464	-- data_in => Port_in(5),
3465	-- data_in_en => data_in_en(5),
3466	-- reset => reset,
3467	-- clk =>clk,
3468	-- grant(61) => grant_signal(61),
3469	-- grant(62) => grant_signal(62),
3470	-- grant(63) => grant_signal(63),
3471	-- grant(64) => grant_signal(64),
3472	-- grant(65) => grant_signal(65),
3473	-- grant(66) => grant_signal(66),
3474	-- grant(67) => grant_signal(67),
3475	-- grant(68) => grant_signal(68),
3476	-- grant(69) => grant_signal(69),
3477	-- grant(70) => grant_signal(70),
3478	-- grant(71) => grant_signal(71),
3479	-- grant(72) => grant_signal(72),
3480	-- grant(73) => grant_signal(73),
3481	-- grant(74) => grant_signal(74),
3482	-- grant(75) => grant_signal(75),
3483	-- fifo_full =>fifo_in_full(5),
3484	-- priority_rotation => priority_rotation_signal(5),
3485	-- fifo_empty => fifo_in_empty(5),
3486	-- data_out =>crossbar_in_port(5),
3487	-- data_out_pulse =>crossbar_in_pulse(5),
3488	-- request(61) =>request_signal(61),
3489	-- request(62) =>request_signal(62),
3490	-- request(63) =>request_signal(63),
3491	-- request(64) =>request_signal(64),
3492	-- request(65) =>request_signal(65),
3493	-- request(66) =>request_signal(66),
3494	-- request(67) =>request_signal(67),
3495	-- request(68) =>request_signal(68),
3496	-- request(69) =>request_signal(69),
3497	-- request(70) =>request_signal(70),
3498	-- request(71) =>request_signal(71),
3499	-- request(72) =>request_signal(72),
3500	-- request(73) =>request_signal(73),
3501	-- request(74) =>request_signal(74),
3502	-- request(75) =>request_signal(75)
3503	--);
3504	--
3505	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3506	--GENERIC MAP(number_of_ports =>15)
3507	--PORT MAP(
3508	-- data_in => Port_in(6),
3509	-- data_in_en => data_in_en(6),
3510	-- reset => reset,
3511	-- clk =>clk,
3512	-- grant(76) => grant_signal(76),
3513	-- grant(77) => grant_signal(77),
3514	-- grant(78) => grant_signal(78),
3515	-- grant(79) => grant_signal(79),
3516	-- grant(80) => grant_signal(80),
3517	-- grant(81) => grant_signal(81),
3518	-- grant(82) => grant_signal(82),
3519	-- grant(83) => grant_signal(83),
3520	-- grant(84) => grant_signal(84),
3521	-- grant(85) => grant_signal(85),
3522	-- grant(86) => grant_signal(86),
3523	-- grant(87) => grant_signal(87),
3524	-- grant(88) => grant_signal(88),
3525	-- grant(89) => grant_signal(89),
3526	-- grant(90) => grant_signal(90),
3527	-- fifo_full =>fifo_in_full(6),
3528	-- priority_rotation => priority_rotation_signal(6),
3529	-- fifo_empty => fifo_in_empty(6),
3530	-- data_out =>crossbar_in_port(6),
3531	-- data_out_pulse =>crossbar_in_pulse(6),
3532	-- request(76) =>request_signal(76),
3533	-- request(77) =>request_signal(77),
3534	-- request(78) =>request_signal(78),
3535	-- request(79) =>request_signal(79),
3536	-- request(80) =>request_signal(80),
3537	-- request(81) =>request_signal(81),
3538	-- request(82) =>request_signal(82),
3539	-- request(83) =>request_signal(83),
3540	-- request(84) =>request_signal(84),
3541	-- request(85) =>request_signal(85),
3542	-- request(86) =>request_signal(86),
3543	-- request(87) =>request_signal(87),
3544	-- request(88) =>request_signal(88),
3545	-- request(89) =>request_signal(89),
3546	-- request(90) =>request_signal(90)
3547	--);
3548	--
3549	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3550	--GENERIC MAP(number_of_ports =>15)
3551	--PORT MAP(
3552	-- data_in => Port_in(7),
3553	-- data_in_en => data_in_en(7),
3554	-- reset => reset,
3555	-- clk =>clk,
3556	-- grant(91) => grant_signal(91),
3557	-- grant(92) => grant_signal(92),
3558	-- grant(93) => grant_signal(93),
3559	-- grant(94) => grant_signal(94),
3560	-- grant(95) => grant_signal(95),
3561	-- grant(96) => grant_signal(96),
3562	-- grant(97) => grant_signal(97),
3563	-- grant(98) => grant_signal(98),
3564	-- grant(99) => grant_signal(99),
3565	-- grant(100) => grant_signal(100),
3566	-- grant(101) => grant_signal(101),
3567	-- grant(102) => grant_signal(102),
3568	-- grant(103) => grant_signal(103),
3569	-- grant(104) => grant_signal(104),
3570	-- grant(105) => grant_signal(105),
3571	-- fifo_full =>fifo_in_full(7),
3572	-- priority_rotation => priority_rotation_signal(7),
3573	-- fifo_empty => fifo_in_empty(7),
3574	-- data_out =>crossbar_in_port(7),
3575	-- data_out_pulse =>crossbar_in_pulse(7),
3576	-- request(91) =>request_signal(91),
3577	-- request(92) =>request_signal(92),
3578	-- request(93) =>request_signal(93),
3579	-- request(94) =>request_signal(94),
3580	-- request(95) =>request_signal(95),
3581	-- request(96) =>request_signal(96),
3582	-- request(97) =>request_signal(97),
3583	-- request(98) =>request_signal(98),
3584	-- request(99) =>request_signal(99),
3585	-- request(100) =>request_signal(100),
3586	-- request(101) =>request_signal(101),
3587	-- request(102) =>request_signal(102),
3588	-- request(103) =>request_signal(103),
3589	-- request(104) =>request_signal(104),
3590	-- request(105) =>request_signal(105)
3591	--);
3592	--
3593	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3594	--GENERIC MAP(number_of_ports =>15)
3595	--PORT MAP(
3596	-- data_in => Port_in(8),
3597	-- data_in_en => data_in_en(8),
3598	-- reset => reset,
3599	-- clk =>clk,
3600	-- grant(106) => grant_signal(106),
3601	-- grant(107) => grant_signal(107),
3602	-- grant(108) => grant_signal(108),
3603	-- grant(109) => grant_signal(109),
3604	-- grant(110) => grant_signal(110),
3605	-- grant(111) => grant_signal(111),
3606	-- grant(112) => grant_signal(112),
3607	-- grant(113) => grant_signal(113),
3608	-- grant(114) => grant_signal(114),
3609	-- grant(115) => grant_signal(115),
3610	-- grant(116) => grant_signal(116),
3611	-- grant(117) => grant_signal(117),
3612	-- grant(118) => grant_signal(118),
3613	-- grant(119) => grant_signal(119),
3614	-- grant(120) => grant_signal(120),
3615	-- fifo_full =>fifo_in_full(8),
3616	-- priority_rotation => priority_rotation_signal(8),
3617	-- fifo_empty => fifo_in_empty(8),
3618	-- data_out =>crossbar_in_port(8),
3619	-- data_out_pulse =>crossbar_in_pulse(8),
3620	-- request(106) =>request_signal(106),
3621	-- request(107) =>request_signal(107),
3622	-- request(108) =>request_signal(108),
3623	-- request(109) =>request_signal(109),
3624	-- request(110) =>request_signal(110),
3625	-- request(111) =>request_signal(111),
3626	-- request(112) =>request_signal(112),
3627	-- request(113) =>request_signal(113),
3628	-- request(114) =>request_signal(114),
3629	-- request(115) =>request_signal(115),
3630	-- request(116) =>request_signal(116),
3631	-- request(117) =>request_signal(117),
3632	-- request(118) =>request_signal(118),
3633	-- request(119) =>request_signal(119),
3634	-- request(120) =>request_signal(120)
3635	--);
3636	--
3637	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3638	--GENERIC MAP(number_of_ports =>15)
3639	--PORT MAP(
3640	-- data_in => Port_in(9),
3641	-- data_in_en => data_in_en(9),
3642	-- reset => reset,
3643	-- clk =>clk,
3644	-- grant(121) => grant_signal(121),
3645	-- grant(122) => grant_signal(122),
3646	-- grant(123) => grant_signal(123),
3647	-- grant(124) => grant_signal(124),
3648	-- grant(125) => grant_signal(125),
3649	-- grant(126) => grant_signal(126),
3650	-- grant(127) => grant_signal(127),
3651	-- grant(128) => grant_signal(128),
3652	-- grant(129) => grant_signal(129),
3653	-- grant(130) => grant_signal(130),
3654	-- grant(131) => grant_signal(131),
3655	-- grant(132) => grant_signal(132),
3656	-- grant(133) => grant_signal(133),
3657	-- grant(134) => grant_signal(134),
3658	-- grant(135) => grant_signal(135),
3659	-- fifo_full =>fifo_in_full(9),
3660	-- priority_rotation => priority_rotation_signal(9),
3661	-- fifo_empty => fifo_in_empty(9),
3662	-- data_out =>crossbar_in_port(9),
3663	-- data_out_pulse =>crossbar_in_pulse(9),
3664	-- request(121) =>request_signal(121),
3665	-- request(122) =>request_signal(122),
3666	-- request(123) =>request_signal(123),
3667	-- request(124) =>request_signal(124),
3668	-- request(125) =>request_signal(125),
3669	-- request(126) =>request_signal(126),
3670	-- request(127) =>request_signal(127),
3671	-- request(128) =>request_signal(128),
3672	-- request(129) =>request_signal(129),
3673	-- request(130) =>request_signal(130),
3674	-- request(131) =>request_signal(131),
3675	-- request(132) =>request_signal(132),
3676	-- request(133) =>request_signal(133),
3677	-- request(134) =>request_signal(134),
3678	-- request(135) =>request_signal(135)
3679	--);
3680	--
3681	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3682	--GENERIC MAP(number_of_ports =>15)
3683	--PORT MAP(
3684	-- data_in => Port_in(10),
3685	-- data_in_en => data_in_en(10),
3686	-- reset => reset,
3687	-- clk =>clk,
3688	-- grant(136) => grant_signal(136),
3689	-- grant(137) => grant_signal(137),
3690	-- grant(138) => grant_signal(138),
3691	-- grant(139) => grant_signal(139),
3692	-- grant(140) => grant_signal(140),
3693	-- grant(141) => grant_signal(141),
3694	-- grant(142) => grant_signal(142),
3695	-- grant(143) => grant_signal(143),
3696	-- grant(144) => grant_signal(144),
3697	-- grant(145) => grant_signal(145),
3698	-- grant(146) => grant_signal(146),
3699	-- grant(147) => grant_signal(147),
3700	-- grant(148) => grant_signal(148),
3701	-- grant(149) => grant_signal(149),
3702	-- grant(150) => grant_signal(150),
3703	-- fifo_full =>fifo_in_full(10),
3704	-- priority_rotation => priority_rotation_signal(10),
3705	-- fifo_empty => fifo_in_empty(10),
3706	-- data_out =>crossbar_in_port(10),
3707	-- data_out_pulse =>crossbar_in_pulse(10),
3708	-- request(136) =>request_signal(136),
3709	-- request(137) =>request_signal(137),
3710	-- request(138) =>request_signal(138),
3711	-- request(139) =>request_signal(139),
3712	-- request(140) =>request_signal(140),
3713	-- request(141) =>request_signal(141),
3714	-- request(142) =>request_signal(142),
3715	-- request(143) =>request_signal(143),
3716	-- request(144) =>request_signal(144),
3717	-- request(145) =>request_signal(145),
3718	-- request(146) =>request_signal(146),
3719	-- request(147) =>request_signal(147),
3720	-- request(148) =>request_signal(148),
3721	-- request(149) =>request_signal(149),
3722	-- request(150) =>request_signal(150)
3723	--);
3724	--
3725	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3726	--GENERIC MAP(number_of_ports =>15)
3727	--PORT MAP(
3728	-- data_in => Port_in(11),
3729	-- data_in_en => data_in_en(11),
3730	-- reset => reset,
3731	-- clk =>clk,
3732	-- grant(151) => grant_signal(151),
3733	-- grant(152) => grant_signal(152),
3734	-- grant(153) => grant_signal(153),
3735	-- grant(154) => grant_signal(154),
3736	-- grant(155) => grant_signal(155),
3737	-- grant(156) => grant_signal(156),
3738	-- grant(157) => grant_signal(157),
3739	-- grant(158) => grant_signal(158),
3740	-- grant(159) => grant_signal(159),
3741	-- grant(160) => grant_signal(160),
3742	-- grant(161) => grant_signal(161),
3743	-- grant(162) => grant_signal(162),
3744	-- grant(163) => grant_signal(163),
3745	-- grant(164) => grant_signal(164),
3746	-- grant(165) => grant_signal(165),
3747	-- fifo_full =>fifo_in_full(11),
3748	-- priority_rotation => priority_rotation_signal(11),
3749	-- fifo_empty => fifo_in_empty(11),
3750	-- data_out =>crossbar_in_port(11),
3751	-- data_out_pulse =>crossbar_in_pulse(11),
3752	-- request(151) =>request_signal(151),
3753	-- request(152) =>request_signal(152),
3754	-- request(153) =>request_signal(153),
3755	-- request(154) =>request_signal(154),
3756	-- request(155) =>request_signal(155),
3757	-- request(156) =>request_signal(156),
3758	-- request(157) =>request_signal(157),
3759	-- request(158) =>request_signal(158),
3760	-- request(159) =>request_signal(159),
3761	-- request(160) =>request_signal(160),
3762	-- request(161) =>request_signal(161),
3763	-- request(162) =>request_signal(162),
3764	-- request(163) =>request_signal(163),
3765	-- request(164) =>request_signal(164),
3766	-- request(165) =>request_signal(165)
3767	--);
3768	--
3769	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3770	--GENERIC MAP(number_of_ports =>15)
3771	--PORT MAP(
3772	-- data_in => Port_in(12),
3773	-- data_in_en => data_in_en(12),
3774	-- reset => reset,
3775	-- clk =>clk,
3776	-- grant(166) => grant_signal(166),
3777	-- grant(167) => grant_signal(167),
3778	-- grant(168) => grant_signal(168),
3779	-- grant(169) => grant_signal(169),
3780	-- grant(170) => grant_signal(170),
3781	-- grant(171) => grant_signal(171),
3782	-- grant(172) => grant_signal(172),
3783	-- grant(173) => grant_signal(173),
3784	-- grant(174) => grant_signal(174),
3785	-- grant(175) => grant_signal(175),
3786	-- grant(176) => grant_signal(176),
3787	-- grant(177) => grant_signal(177),
3788	-- grant(178) => grant_signal(178),
3789	-- grant(179) => grant_signal(179),
3790	-- grant(180) => grant_signal(180),
3791	-- fifo_full =>fifo_in_full(12),
3792	-- priority_rotation => priority_rotation_signal(12),
3793	-- fifo_empty => fifo_in_empty(12),
3794	-- data_out =>crossbar_in_port(12),
3795	-- data_out_pulse =>crossbar_in_pulse(12),
3796	-- request(166) =>request_signal(166),
3797	-- request(167) =>request_signal(167),
3798	-- request(168) =>request_signal(168),
3799	-- request(169) =>request_signal(169),
3800	-- request(170) =>request_signal(170),
3801	-- request(171) =>request_signal(171),
3802	-- request(172) =>request_signal(172),
3803	-- request(173) =>request_signal(173),
3804	-- request(174) =>request_signal(174),
3805	-- request(175) =>request_signal(175),
3806	-- request(176) =>request_signal(176),
3807	-- request(177) =>request_signal(177),
3808	-- request(178) =>request_signal(178),
3809	-- request(179) =>request_signal(179),
3810	-- request(180) =>request_signal(180)
3811	--);
3812	--
3813	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3814	--GENERIC MAP(number_of_ports =>15)
3815	--PORT MAP(
3816	-- data_in => Port_in(13),
3817	-- data_in_en => data_in_en(13),
3818	-- reset => reset,
3819	-- clk =>clk,
3820	-- grant(181) => grant_signal(181),
3821	-- grant(182) => grant_signal(182),
3822	-- grant(183) => grant_signal(183),
3823	-- grant(184) => grant_signal(184),
3824	-- grant(185) => grant_signal(185),
3825	-- grant(186) => grant_signal(186),
3826	-- grant(187) => grant_signal(187),
3827	-- grant(188) => grant_signal(188),
3828	-- grant(189) => grant_signal(189),
3829	-- grant(190) => grant_signal(190),
3830	-- grant(191) => grant_signal(191),
3831	-- grant(192) => grant_signal(192),
3832	-- grant(193) => grant_signal(193),
3833	-- grant(194) => grant_signal(194),
3834	-- grant(195) => grant_signal(195),
3835	-- fifo_full =>fifo_in_full(13),
3836	-- priority_rotation => priority_rotation_signal(13),
3837	-- fifo_empty => fifo_in_empty(13),
3838	-- data_out =>crossbar_in_port(13),
3839	-- data_out_pulse =>crossbar_in_pulse(13),
3840	-- request(181) =>request_signal(181),
3841	-- request(182) =>request_signal(182),
3842	-- request(183) =>request_signal(183),
3843	-- request(184) =>request_signal(184),
3844	-- request(185) =>request_signal(185),
3845	-- request(186) =>request_signal(186),
3846	-- request(187) =>request_signal(187),
3847	-- request(188) =>request_signal(188),
3848	-- request(189) =>request_signal(189),
3849	-- request(190) =>request_signal(190),
3850	-- request(191) =>request_signal(191),
3851	-- request(192) =>request_signal(192),
3852	-- request(193) =>request_signal(193),
3853	-- request(194) =>request_signal(194),
3854	-- request(195) =>request_signal(195)
3855	--);
3856	--
3857	--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3858	--GENERIC MAP(number_of_ports =>15)
3859	--PORT MAP(
3860	-- data_in => Port_in(14),
3861	-- data_in_en => data_in_en(14),
3862	-- reset => reset,
3863	-- clk =>clk,
3864	-- grant(196) => grant_signal(196),
3865	-- grant(197) => grant_signal(197),
3866	-- grant(198) => grant_signal(198),
3867	-- grant(199) => grant_signal(199),
3868	-- grant(200) => grant_signal(200),
3869	-- grant(201) => grant_signal(201),
3870	-- grant(202) => grant_signal(202),
3871	-- grant(203) => grant_signal(203),
3872	-- grant(204) => grant_signal(204),
3873	-- grant(205) => grant_signal(205),
3874	-- grant(206) => grant_signal(206),
3875	-- grant(207) => grant_signal(207),
3876	-- grant(208) => grant_signal(208),
3877	-- grant(209) => grant_signal(209),
3878	-- grant(210) => grant_signal(210),
3879	-- fifo_full =>fifo_in_full(14),
3880	-- priority_rotation => priority_rotation_signal(14),
3881	-- fifo_empty => fifo_in_empty(14),
3882	-- data_out =>crossbar_in_port(14),
3883	-- data_out_pulse =>crossbar_in_pulse(14),
3884	-- request(196) =>request_signal(196),
3885	-- request(197) =>request_signal(197),
3886	-- request(198) =>request_signal(198),
3887	-- request(199) =>request_signal(199),
3888	-- request(200) =>request_signal(200),
3889	-- request(201) =>request_signal(201),
3890	-- request(202) =>request_signal(202),
3891	-- request(203) =>request_signal(203),
3892	-- request(204) =>request_signal(204),
3893	-- request(205) =>request_signal(205),
3894	-- request(206) =>request_signal(206),
3895	-- request(207) =>request_signal(207),
3896	-- request(208) =>request_signal(208),
3897	-- request(209) =>request_signal(209),
3898	-- request(210) =>request_signal(210)
3899	--);
3900	--
3901	--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3902	--GENERIC MAP(number_of_ports =>15)
3903	--PORT MAP(
3904	-- data_in => Port_in(15),
3905	-- data_in_en => data_in_en(15),
3906	-- reset => reset,
3907	-- clk =>clk,
3908	-- grant(211) => grant_signal(211),
3909	-- grant(212) => grant_signal(212),
3910	-- grant(213) => grant_signal(213),
3911	-- grant(214) => grant_signal(214),
3912	-- grant(215) => grant_signal(215),
3913	-- grant(216) => grant_signal(216),
3914	-- grant(217) => grant_signal(217),
3915	-- grant(218) => grant_signal(218),
3916	-- grant(219) => grant_signal(219),
3917	-- grant(220) => grant_signal(220),
3918	-- grant(221) => grant_signal(221),
3919	-- grant(222) => grant_signal(222),
3920	-- grant(223) => grant_signal(223),
3921	-- grant(224) => grant_signal(224),
3922	-- grant(225) => grant_signal(225),
3923	-- fifo_full =>fifo_in_full(15),
3924	-- priority_rotation => priority_rotation_signal(15),
3925	-- fifo_empty => fifo_in_empty(15),
3926	-- data_out =>crossbar_in_port(15),
3927	-- data_out_pulse =>crossbar_in_pulse(15),
3928	-- request(211) =>request_signal(211),
3929	-- request(212) =>request_signal(212),
3930	-- request(213) =>request_signal(213),
3931	-- request(214) =>request_signal(214),
3932	-- request(215) =>request_signal(215),
3933	-- request(216) =>request_signal(216),
3934	-- request(217) =>request_signal(217),
3935	-- request(218) =>request_signal(218),
3936	-- request(219) =>request_signal(219),
3937	-- request(220) =>request_signal(220),
3938	-- request(221) =>request_signal(221),
3939	-- request(222) =>request_signal(222),
3940	-- request(223) =>request_signal(223),
3941	-- request(224) =>request_signal(224),
3942	-- request(225) =>request_signal(225)
3943	--);
3944	--
3945	--end generate switch15x15;
3946
3947
3948	-- switch 16 ports
3949	switch16x16 : if n_ports = 16 generate
3950	switch_16x16 :for i in 1 to n_ports generate
3951	Constant j : natural:=n_ports*(i-1);
3952	begin
3953	--j<=number_of_ports*(i-1);
3954	PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3955	GENERIC MAP(number_of_ports =>16,port_num=>i)
3956	PORT MAP(
3957	data_in => Port_in(i),
3958	data_in_en => data_in_en(i),
3959	cmd_in_en => cmd_in_en(i),
3960	reset => reset,
3961	clk =>clk,
3962	grant(1) => grant_signal(j+1),
3963	grant(2) => grant_signal(j+2),
3964	grant(3) => grant_signal(j+3),
3965	grant(4) => grant_signal(j+4),
3966	grant(5) => grant_signal(j+5),
3967	grant(6) => grant_signal(j+6),
3968	grant(7) => grant_signal(j+7),
3969	grant(8) => grant_signal(j+8),
3970	grant(9) => grant_signal(j+9),
3971	grant(10) => grant_signal(j+10),
3972	grant(11) => grant_signal(j+11),
3973	grant(12) => grant_signal(j+12),
3974	grant(13) => grant_signal(j+13),
3975	grant(14) => grant_signal(j+14),
3976	grant(15) => grant_signal(j+15),
3977	grant(16) => grant_signal(j+16),
3978	fifo_full =>fifo_in_full(i),
3979	priority_rotation => priority_rotation_signal(i),
3980	fifo_empty => fifo_in_empty(i),
3981	data_out =>crossbar_in_port(i),
3982	data_out_pulse =>crossbar_in_pulse(i),
3983	request(1) =>request_signal(j+1),
3984	request(2) =>request_signal(j+2),
3985	request(3) =>request_signal(j+3),
3986	request(4) =>request_signal(j+4),
3987	request(5) =>request_signal(j+5),
3988	request(6) =>request_signal(j+6),
3989	request(7) =>request_signal(j+7),
3990	request(8) =>request_signal(j+8),
3991	request(9) =>request_signal(j+9),
3992	request(10) =>request_signal(j+10),
3993	request(11) =>request_signal(j+11),
3994	request(12) =>request_signal(j+12),
3995	request(13) =>request_signal(j+13),
3996	request(14) =>request_signal(j+14),
3997	request(15) =>request_signal(j+15),
3998	request(16) =>request_signal(j+16)
3999	);
4000	end generate switch_16x16;
4001	end generate switch16x16;
4002	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4003	--GENERIC MAP(number_of_ports =>16)
4004	--PORT MAP(
4005	-- data_in => Port_in(2),
4006	-- data_in_en => data_in_en(2),
4007	-- reset => reset,
4008	-- clk =>clk,
4009	-- grant(17) => grant_signal(17),
4010	-- grant(18) => grant_signal(18),
4011	-- grant(19) => grant_signal(19),
4012	-- grant(20) => grant_signal(20),
4013	-- grant(21) => grant_signal(21),
4014	-- grant(22) => grant_signal(22),
4015	-- grant(23) => grant_signal(23),
4016	-- grant(24) => grant_signal(24),
4017	-- grant(25) => grant_signal(25),
4018	-- grant(26) => grant_signal(26),
4019	-- grant(27) => grant_signal(27),
4020	-- grant(28) => grant_signal(28),
4021	-- grant(29) => grant_signal(29),
4022	-- grant(30) => grant_signal(30),
4023	-- grant(31) => grant_signal(31),
4024	-- grant(32) => grant_signal(32),
4025	-- fifo_full =>fifo_in_full(2),
4026	-- priority_rotation => priority_rotation_signal(2),
4027	-- fifo_empty => fifo_in_empty(2),
4028	-- data_out =>crossbar_in_port2,
4029	-- data_out_pulse =>crossbar_in_pulse(2,
4030	-- request(17) =>request_signal(17),
4031	-- request(18) =>request_signal(18),
4032	-- request(19) =>request_signal(19),
4033	-- request(20) =>request_signal(20),
4034	-- request(21) =>request_signal(21),
4035	-- request(22) =>request_signal(22),
4036	-- request(23) =>request_signal(23),
4037	-- request(24) =>request_signal(24),
4038	-- request(25) =>request_signal(25),
4039	-- request(26) =>request_signal(26),
4040	-- request(27) =>request_signal(27),
4041	-- request(28) =>request_signal(28),
4042	-- request(29) =>request_signal(29),
4043	-- request(30) =>request_signal(30),
4044	-- request(31) =>request_signal(31),
4045	-- request(32) =>request_signal(32)
4046	--);
4047	--
4048	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4049	--GENERIC MAP(number_of_ports =>16)
4050	--PORT MAP(
4051	-- data_in => Port_in(3),
4052	-- data_in_en => data_in_en(3),
4053	-- reset => reset,
4054	-- clk =>clk,
4055	-- grant(33) => grant_signal(33),
4056	-- grant(34) => grant_signal(34),
4057	-- grant(35) => grant_signal(35),
4058	-- grant(36) => grant_signal(36),
4059	-- grant(37) => grant_signal(37),
4060	-- grant(38) => grant_signal(38),
4061	-- grant(39) => grant_signal(39),
4062	-- grant(40) => grant_signal(40),
4063	-- grant(41) => grant_signal(41),
4064	-- grant(42) => grant_signal(42),
4065	-- grant(43) => grant_signal(43),
4066	-- grant(44) => grant_signal(44),
4067	-- grant(45) => grant_signal(45),
4068	-- grant(46) => grant_signal(46),
4069	-- grant(47) => grant_signal(47),
4070	-- grant(48) => grant_signal(48),
4071	-- fifo_full =>fifo_in_full(3),
4072	-- priority_rotation => priority_rotation_signal(3),
4073	-- fifo_empty => fifo_in_empty(3),
4074	-- data_out =>crossbar_in_port3,
4075	-- data_out_pulse =>crossbar_in_pulse(3,
4076	-- request(33) =>request_signal(33),
4077	-- request(34) =>request_signal(34),
4078	-- request(35) =>request_signal(35),
4079	-- request(36) =>request_signal(36),
4080	-- request(37) =>request_signal(37),
4081	-- request(38) =>request_signal(38),
4082	-- request(39) =>request_signal(39),
4083	-- request(40) =>request_signal(40),
4084	-- request(41) =>request_signal(41),
4085	-- request(42) =>request_signal(42),
4086	-- request(43) =>request_signal(43),
4087	-- request(44) =>request_signal(44),
4088	-- request(45) =>request_signal(45),
4089	-- request(46) =>request_signal(46),
4090	-- request(47) =>request_signal(47),
4091	-- request(48) =>request_signal(48)
4092	--);
4093	--
4094	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4095	--GENERIC MAP(number_of_ports =>16)
4096	--PORT MAP(
4097	-- data_in => Port_in(4),
4098	-- data_in_en => data_in_en(4),
4099	-- reset => reset,
4100	-- clk =>clk,
4101	-- grant(49) => grant_signal(49),
4102	-- grant(50) => grant_signal(50),
4103	-- grant(51) => grant_signal(51),
4104	-- grant(52) => grant_signal(52),
4105	-- grant(53) => grant_signal(53),
4106	-- grant(54) => grant_signal(54),
4107	-- grant(55) => grant_signal(55),
4108	-- grant(56) => grant_signal(56),
4109	-- grant(57) => grant_signal(57),
4110	-- grant(58) => grant_signal(58),
4111	-- grant(59) => grant_signal(59),
4112	-- grant(60) => grant_signal(60),
4113	-- grant(61) => grant_signal(61),
4114	-- grant(62) => grant_signal(62),
4115	-- grant(63) => grant_signal(63),
4116	-- grant(64) => grant_signal(64),
4117	-- fifo_full =>fifo_in_full(4),
4118	-- priority_rotation => priority_rotation_signal(4),
4119	-- fifo_empty => fifo_in_empty(4),
4120	-- data_out =>crossbar_in_port(4),
4121	-- data_out_pulse =>crossbar_in_pulse(4,
4122	-- request(49) =>request_signal(49),
4123	-- request(50) =>request_signal(50),
4124	-- request(51) =>request_signal(51),
4125	-- request(52) =>request_signal(52),
4126	-- request(53) =>request_signal(53),
4127	-- request(54) =>request_signal(54),
4128	-- request(55) =>request_signal(55),
4129	-- request(56) =>request_signal(56),
4130	-- request(57) =>request_signal(57),
4131	-- request(58) =>request_signal(58),
4132	-- request(59) =>request_signal(59),
4133	-- request(60) =>request_signal(60),
4134	-- request(61) =>request_signal(61),
4135	-- request(62) =>request_signal(62),
4136	-- request(63) =>request_signal(63),
4137	-- request(64) =>request_signal(64)
4138	--);
4139	--
4140	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4141	--GENERIC MAP(number_of_ports =>16)
4142	--PORT MAP(
4143	-- data_in => Port_in(5),
4144	-- data_in_en => data_in_en(5),
4145	-- reset => reset,
4146	-- clk =>clk,
4147	-- grant(65) => grant_signal(65),
4148	-- grant(66) => grant_signal(66),
4149	-- grant(67) => grant_signal(67),
4150	-- grant(68) => grant_signal(68),
4151	-- grant(69) => grant_signal(69),
4152	-- grant(70) => grant_signal(70),
4153	-- grant(71) => grant_signal(71),
4154	-- grant(72) => grant_signal(72),
4155	-- grant(73) => grant_signal(73),
4156	-- grant(74) => grant_signal(74),
4157	-- grant(75) => grant_signal(75),
4158	-- grant(76) => grant_signal(76),
4159	-- grant(77) => grant_signal(77),
4160	-- grant(78) => grant_signal(78),
4161	-- grant(79) => grant_signal(79),
4162	-- grant(80) => grant_signal(80),
4163	-- fifo_full =>fifo_in_full(5),
4164	-- priority_rotation => priority_rotation_signal(5),
4165	-- fifo_empty => fifo_in_empty(5),
4166	-- data_out =>crossbar_in_port(5),
4167	-- data_out_pulse =>crossbar_in_pulse(5,
4168	-- request(65) =>request_signal(65),
4169	-- request(66) =>request_signal(66),
4170	-- request(67) =>request_signal(67),
4171	-- request(68) =>request_signal(68),
4172	-- request(69) =>request_signal(69),
4173	-- request(70) =>request_signal(70),
4174	-- request(71) =>request_signal(71),
4175	-- request(72) =>request_signal(72),
4176	-- request(73) =>request_signal(73),
4177	-- request(74) =>request_signal(74),
4178	-- request(75) =>request_signal(75),
4179	-- request(76) =>request_signal(76),
4180	-- request(77) =>request_signal(77),
4181	-- request(78) =>request_signal(78),
4182	-- request(79) =>request_signal(79),
4183	-- request(80) =>request_signal(80)
4184	--);
4185	--
4186	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4187	--GENERIC MAP(number_of_ports =>16)
4188	--PORT MAP(
4189	-- data_in => Port_in(6),
4190	-- data_in_en => data_in_en(6),
4191	-- reset => reset,
4192	-- clk =>clk,
4193	-- grant(81) => grant_signal(81),
4194	-- grant(82) => grant_signal(82),
4195	-- grant(83) => grant_signal(83),
4196	-- grant(84) => grant_signal(84),
4197	-- grant(85) => grant_signal(85),
4198	-- grant(86) => grant_signal(86),
4199	-- grant(87) => grant_signal(87),
4200	-- grant(88) => grant_signal(88),
4201	-- grant(89) => grant_signal(89),
4202	-- grant(90) => grant_signal(90),
4203	-- grant(91) => grant_signal(91),
4204	-- grant(92) => grant_signal(92),
4205	-- grant(93) => grant_signal(93),
4206	-- grant(94) => grant_signal(94),
4207	-- grant(95) => grant_signal(95),
4208	-- grant(96) => grant_signal(96),
4209	-- fifo_full =>fifo_in_full(6),
4210	-- priority_rotation => priority_rotation_signal(6),
4211	-- fifo_empty => fifo_in_empty(6),
4212	-- data_out =>crossbar_in_port(6),
4213	-- data_out_pulse =>crossbar_in_pulse(6,
4214	-- request(81) =>request_signal(81),
4215	-- request(82) =>request_signal(82),
4216	-- request(83) =>request_signal(83),
4217	-- request(84) =>request_signal(84),
4218	-- request(85) =>request_signal(85),
4219	-- request(86) =>request_signal(86),
4220	-- request(87) =>request_signal(87),
4221	-- request(88) =>request_signal(88),
4222	-- request(89) =>request_signal(89),
4223	-- request(90) =>request_signal(90),
4224	-- request(91) =>request_signal(91),
4225	-- request(92) =>request_signal(92),
4226	-- request(93) =>request_signal(93),
4227	-- request(94) =>request_signal(94),
4228	-- request(95) =>request_signal(95),
4229	-- request(96) =>request_signal(96)
4230	--);
4231	--
4232	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4233	--GENERIC MAP(number_of_ports =>16)
4234	--PORT MAP(
4235	-- data_in => Port_in(7),
4236	-- data_in_en => data_in_en(7),
4237	-- reset => reset,
4238	-- clk =>clk,
4239	-- grant(97) => grant_signal(97),
4240	-- grant(98) => grant_signal(98),
4241	-- grant(99) => grant_signal(99),
4242	-- grant(0) => grant_signal(100),
4243	-- grant(1) => grant_signal(101),
4244	-- grant(2) => grant_signal(102),
4245	-- grant(3) => grant_signal(103),
4246	-- grant(4) => grant_signal(104),
4247	-- grant(5) => grant_signal(105),
4248	-- grant(6) => grant_signal(106),
4249	-- grant(7) => grant_signal(107),
4250	-- grant(8) => grant_signal(108),
4251	-- grant(9) => grant_signal(109),
4252	-- grant(110) => grant_signal(110),
4253	-- grant(111) => grant_signal(111),
4254	-- grant(112) => grant_signal(112),
4255	-- fifo_full =>fifo_in_full(7),
4256	-- priority_rotation => priority_rotation_signal(7),
4257	-- fifo_empty => fifo_in_empty(7),
4258	-- data_out =>crossbar_in_port(8),
4259	-- data_out_pulse =>crossbar_in_pulse(7,
4260	-- request(97) =>request_signal(97),
4261	-- request(98) =>request_signal(98),
4262	-- request(99) =>request_signal(99),
4263	-- request(100) =>request_signal(100),
4264	-- request(101) =>request_signal(101),
4265	-- request(102) =>request_signal(102),
4266	-- request(103) =>request_signal(103),
4267	-- request(104) =>request_signal(104),
4268	-- request(105) =>request_signal(105),
4269	-- request(106) =>request_signal(106),
4270	-- request(107) =>request_signal(107),
4271	-- request(108) =>request_signal(108),
4272	-- request(109) =>request_signal(109),
4273	-- request(110) =>request_signal(110),
4274	-- request(111) =>request_signal(111),
4275	-- request(112) =>request_signal(112)
4276	--);
4277	--
4278	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4279	--GENERIC MAP(number_of_ports =>16)
4280	--PORT MAP(
4281	-- data_in => Port_in(8),
4282	-- data_in_en => data_in_en(8),
4283	-- reset => reset,
4284	-- clk =>clk,
4285	-- grant(113) => grant_signal(113),
4286	-- grant(114) => grant_signal(114),
4287	-- grant(115) => grant_signal(115),
4288	-- grant(116) => grant_signal(116),
4289	-- grant(117) => grant_signal(117),
4290	-- grant(118) => grant_signal(118),
4291	-- grant(119) => grant_signal(119),
4292	-- grant(120) => grant_signal(120),
4293	-- grant(121) => grant_signal(121),
4294	-- grant(122) => grant_signal(122),
4295	-- grant(123) => grant_signal(123),
4296	-- grant(124) => grant_signal(124),
4297	-- grant(125) => grant_signal(125),
4298	-- grant(126) => grant_signal(126),
4299	-- grant(127) => grant_signal(127),
4300	-- grant(128) => grant_signal(128),
4301	-- fifo_full =>fifo_in_full(8),
4302	-- priority_rotation => priority_rotation_signal(8),
4303	-- fifo_empty => fifo_in_empty(8),
4304	-- data_out =>crossbar_in_port8,
4305	-- data_out_pulse =>crossbar_in_pulse(8,
4306	-- request(113) =>request_signal(113),
4307	-- request(114) =>request_signal(114),
4308	-- request(115) =>request_signal(115),
4309	-- request(116) =>request_signal(116),
4310	-- request(117) =>request_signal(117),
4311	-- request(118) =>request_signal(118),
4312	-- request(119) =>request_signal(119),
4313	-- request(120) =>request_signal(120),
4314	-- request(121) =>request_signal(121),
4315	-- request(122) =>request_signal(122),
4316	-- request(123) =>request_signal(123),
4317	-- request(124) =>request_signal(124),
4318	-- request(125) =>request_signal(125),
4319	-- request(126) =>request_signal(126),
4320	-- request(127) =>request_signal(127),
4321	-- request(128) =>request_signal(128)
4322	--);
4323	--
4324	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4325	--GENERIC MAP(number_of_ports =>16)
4326	--PORT MAP(
4327	-- data_in => Port_in(9),
4328	-- data_in_en => data_in_en(9),
4329	-- reset => reset,
4330	-- clk =>clk,
4331	-- grant(129) => grant_signal(129),
4332	-- grant(130) => grant_signal(130),
4333	-- grant(131) => grant_signal(131),
4334	-- grant(132) => grant_signal(132),
4335	-- grant(133) => grant_signal(133),
4336	-- grant(134) => grant_signal(134),
4337	-- grant(135) => grant_signal(135),
4338	-- grant(136) => grant_signal(136),
4339	-- grant(137) => grant_signal(137),
4340	-- grant(138) => grant_signal(138),
4341	-- grant(139) => grant_signal(139),
4342	-- grant(140) => grant_signal(140),
4343	-- grant(141) => grant_signal(141),
4344	-- grant(142) => grant_signal(142),
4345	-- grant(143) => grant_signal(143),
4346	-- grant(144) => grant_signal(144),
4347	-- fifo_full =>fifo_in_full(9),
4348	-- priority_rotation => priority_rotation_signal(9),
4349	-- fifo_empty => fifo_in_empty(9),
4350	-- data_out =>crossbar_in_port9,
4351	-- data_out_pulse =>crossbar_in_pulse(9),
4352	-- request(129) =>request_signal(129),
4353	-- request(130) =>request_signal(130),
4354	-- request(131) =>request_signal(131),
4355	-- request(132) =>request_signal(132),
4356	-- request(133) =>request_signal(133),
4357	-- request(134) =>request_signal(134),
4358	-- request(135) =>request_signal(135),
4359	-- request(136) =>request_signal(136),
4360	-- request(137) =>request_signal(137),
4361	-- request(138) =>request_signal(138),
4362	-- request(139) =>request_signal(139),
4363	-- request(140) =>request_signal(140),
4364	-- request(141) =>request_signal(141),
4365	-- request(142) =>request_signal(142),
4366	-- request(143) =>request_signal(143),
4367	-- request(144) =>request_signal(144)
4368	--);
4369	--
4370	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4371	--GENERIC MAP(number_of_ports =>16)
4372	--PORT MAP(
4373	-- data_in => Port_in(10),
4374	-- data_in_en => data_in_en(10),
4375	-- reset => reset,
4376	-- clk =>clk,
4377	-- grant(145) => grant_signal(145),
4378	-- grant(146) => grant_signal(146),
4379	-- grant(147) => grant_signal(147),
4380	-- grant(148) => grant_signal(148),
4381	-- grant(149) => grant_signal(149),
4382	-- grant(150) => grant_signal(150),
4383	-- grant(151) => grant_signal(151),
4384	-- grant(152) => grant_signal(152),
4385	-- grant(153) => grant_signal(153),
4386	-- grant(154) => grant_signal(154),
4387	-- grant(155) => grant_signal(155),
4388	-- grant(156) => grant_signal(156),
4389	-- grant(157) => grant_signal(157),
4390	-- grant(158) => grant_signal(158),
4391	-- grant(159) => grant_signal(159),
4392	-- grant(160) => grant_signal(160),
4393	-- fifo_full =>fifo_in_full(10),
4394	-- priority_rotation => priority_rotation_signal(10),
4395	-- fifo_empty => fifo_in_empty(10),
4396	-- data_out =>crossbar_in_port(10),
4397	-- data_out_pulse =>crossbar_in_pulse(10),
4398	-- request(145) =>request_signal(145),
4399	-- request(146) =>request_signal(146),
4400	-- request(147) =>request_signal(147),
4401	-- request(148) =>request_signal(148),
4402	-- request(149) =>request_signal(149),
4403	-- request(150) =>request_signal(150),
4404	-- request(151) =>request_signal(151),
4405	-- request(152) =>request_signal(152),
4406	-- request(153) =>request_signal(153),
4407	-- request(154) =>request_signal(154),
4408	-- request(155) =>request_signal(155),
4409	-- request(156) =>request_signal(156),
4410	-- request(157) =>request_signal(157),
4411	-- request(158) =>request_signal(158),
4412	-- request(159) =>request_signal(159),
4413	-- request(160) =>request_signal(160)
4414	--);
4415	--
4416	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4417	--GENERIC MAP(number_of_ports =>16)
4418	--PORT MAP(
4419	-- data_in => Port_in(11),
4420	-- data_in_en => data_in_en(11),
4421	-- reset => reset,
4422	-- clk =>clk,
4423	-- grant(161) => grant_signal(161),
4424	-- grant(162) => grant_signal(162),
4425	-- grant(163) => grant_signal(163),
4426	-- grant(164) => grant_signal(164),
4427	-- grant(165) => grant_signal(165),
4428	-- grant(166) => grant_signal(166),
4429	-- grant(167) => grant_signal(167),
4430	-- grant(168) => grant_signal(168),
4431	-- grant(169) => grant_signal(169),
4432	-- grant(170) => grant_signal(170),
4433	-- grant(171) => grant_signal(171),
4434	-- grant(172) => grant_signal(172),
4435	-- grant(173) => grant_signal(173),
4436	-- grant(174) => grant_signal(174),
4437	-- grant(175) => grant_signal(175),
4438	-- grant(176) => grant_signal(176),
4439	-- fifo_full =>fifo_in_full(11),
4440	-- priority_rotation => priority_rotation_signal(11),
4441	-- fifo_empty => fifo_in_empty(11),
4442	-- data_out =>crossbar_in_port(11),
4443	-- data_out_pulse =>crossbar_in_pulse(11),
4444	-- request(161) =>request_signal(161),
4445	-- request(162) =>request_signal(162),
4446	-- request(163) =>request_signal(163),
4447	-- request(164) =>request_signal(164),
4448	-- request(165) =>request_signal(165),
4449	-- request(166) =>request_signal(166),
4450	-- request(167) =>request_signal(167),
4451	-- request(168) =>request_signal(168),
4452	-- request(169) =>request_signal(169),
4453	-- request(170) =>request_signal(170),
4454	-- request(171) =>request_signal(171),
4455	-- request(172) =>request_signal(172),
4456	-- request(173) =>request_signal(173),
4457	-- request(174) =>request_signal(174),
4458	-- request(175) =>request_signal(175),
4459	-- request(176) =>request_signal(176)
4460	--);
4461	--
4462	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4463	--GENERIC MAP(number_of_ports =>16)
4464	--PORT MAP(
4465	-- data_in => Port_in(12),
4466	-- data_in_en => data_in_en(12),
4467	-- reset => reset,
4468	-- clk =>clk,
4469	-- grant(177) => grant_signal(177),
4470	-- grant(178) => grant_signal(178),
4471	-- grant(179) => grant_signal(179),
4472	-- grant(180) => grant_signal(180),
4473	-- grant(181) => grant_signal(181),
4474	-- grant(182) => grant_signal(182),
4475	-- grant(183) => grant_signal(183),
4476	-- grant(184) => grant_signal(184),
4477	-- grant(185) => grant_signal(185),
4478	-- grant(186) => grant_signal(186),
4479	-- grant(187) => grant_signal(187),
4480	-- grant(188) => grant_signal(188),
4481	-- grant(189) => grant_signal(189),
4482	-- grant(190) => grant_signal(190),
4483	-- grant(191) => grant_signal(191),
4484	-- grant(192) => grant_signal(192),
4485	-- fifo_full =>fifo_in_full(12),
4486	-- priority_rotation => priority_rotation_signal(12),
4487	-- fifo_empty => fifo_in_empty(12),
4488	-- data_out =>crossbar_in_port(12),
4489	-- data_out_pulse =>crossbar_in_pulse(12),
4490	-- request(177) =>request_signal(177),
4491	-- request(178) =>request_signal(178),
4492	-- request(179) =>request_signal(179),
4493	-- request(180) =>request_signal(180),
4494	-- request(181) =>request_signal(181),
4495	-- request(182) =>request_signal(182),
4496	-- request(183) =>request_signal(183),
4497	-- request(184) =>request_signal(184),
4498	-- request(185) =>request_signal(185),
4499	-- request(186) =>request_signal(186),
4500	-- request(187) =>request_signal(187),
4501	-- request(188) =>request_signal(188),
4502	-- request(189) =>request_signal(189),
4503	-- request(190) =>request_signal(190),
4504	-- request(191) =>request_signal(191),
4505	-- request(192) =>request_signal(192)
4506	--);
4507	--
4508	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4509	--GENERIC MAP(number_of_ports =>16)
4510	--PORT MAP(
4511	-- data_in => Port_in(13),
4512	-- data_in_en => data_in_en(13),
4513	-- reset => reset,
4514	-- clk =>clk,
4515	-- grant(193) => grant_signal(193),
4516	-- grant(194) => grant_signal(194),
4517	-- grant(195) => grant_signal(195),
4518	-- grant(196) => grant_signal(196),
4519	-- grant(197) => grant_signal(197),
4520	-- grant(198) => grant_signal(198),
4521	-- grant(199) => grant_signal(199),
4522	-- grant(200) => grant_signal(200),
4523	-- grant(201) => grant_signal(201),
4524	-- grant(202) => grant_signal(202),
4525	-- grant(203) => grant_signal(203),
4526	-- grant(204) => grant_signal(204),
4527	-- grant(205) => grant_signal(205),
4528	-- grant(206) => grant_signal(206),
4529	-- grant(207) => grant_signal(207),
4530	-- grant(208) => grant_signal(208),
4531	-- fifo_full =>fifo_in_full(13),
4532	-- priority_rotation => priority_rotation_signal(13),
4533	-- fifo_empty => fifo_in_empty(13),
4534	-- data_out =>crossbar_in_port13,
4535	-- data_out_pulse =>crossbar_in_pulse(13,
4536	-- request(193) =>request_signal(193),
4537	-- request(194) =>request_signal(194),
4538	-- request(195) =>request_signal(195),
4539	-- request(196) =>request_signal(196),
4540	-- request(197) =>request_signal(197),
4541	-- request(198) =>request_signal(198),
4542	-- request(199) =>request_signal(199),
4543	-- request(200) =>request_signal(200),
4544	-- request(201) =>request_signal(201),
4545	-- request(202) =>request_signal(202),
4546	-- request(203) =>request_signal(203),
4547	-- request(204) =>request_signal(204),
4548	-- request(205) =>request_signal(205),
4549	-- request(206) =>request_signal(206),
4550	-- request(207) =>request_signal(207),
4551	-- request(208) =>request_signal(208)
4552	--);
4553	--
4554	--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4555	--GENERIC MAP(number_of_ports =>16)
4556	--PORT MAP(
4557	-- data_in => Port_in(14),
4558	-- data_in_en => data_in_en(14),
4559	-- reset => reset,
4560	-- clk =>clk,
4561	-- grant(209) => grant_signal(209),
4562	-- grant(210) => grant_signal(210),
4563	-- grant(211) => grant_signal(211),
4564	-- grant(212) => grant_signal(212),
4565	-- grant(213) => grant_signal(213),
4566	-- grant(214) => grant_signal(214),
4567	-- grant(215) => grant_signal(215),
4568	-- grant(216) => grant_signal(216),
4569	-- grant(217) => grant_signal(217),
4570	-- grant(218) => grant_signal(218),
4571	-- grant(219) => grant_signal(219),
4572	-- grant(220) => grant_signal(220),
4573	-- grant(221) => grant_signal(221),
4574	-- grant(222) => grant_signal(222),
4575	-- grant(223) => grant_signal(223),
4576	-- grant(224) => grant_signal(224),
4577	-- fifo_full =>fifo_in_full(14),
4578	-- priority_rotation => priority_rotation_signal(14),
4579	-- fifo_empty => fifo_in_empty(14),
4580	-- data_out =>crossbar_in_port(14),
4581	-- data_out_pulse =>crossbar_in_pulse(14),
4582	-- request(209) =>request_signal(209),
4583	-- request(210) =>request_signal(210),
4584	-- request(211) =>request_signal(211),
4585	-- request(212) =>request_signal(212),
4586	-- request(213) =>request_signal(213),
4587	-- request(214) =>request_signal(214),
4588	-- request(215) =>request_signal(215),
4589	-- request(216) =>request_signal(216),
4590	-- request(217) =>request_signal(217),
4591	-- request(218) =>request_signal(218),
4592	-- request(219) =>request_signal(219),
4593	-- request(220) =>request_signal(220),
4594	-- request(221) =>request_signal(221),
4595	-- request(222) =>request_signal(222),
4596	-- request(223) =>request_signal(223),
4597	-- request(224) =>request_signal(224)
4598	--);
4599	--
4600	--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4601	--GENERIC MAP(number_of_ports =>16)
4602	--PORT MAP(
4603	-- data_in => Port_in(15),
4604	-- data_in_en => data_in_en(15),
4605	-- reset => reset,
4606	-- clk =>clk,
4607	-- grant(225) => grant_signal(225),
4608	-- grant(226) => grant_signal(226),
4609	-- grant(227) => grant_signal(227),
4610	-- grant(228) => grant_signal(228),
4611	-- grant(229) => grant_signal(229),
4612	-- grant(230) => grant_signal(230),
4613	-- grant(231) => grant_signal(231),
4614	-- grant(232) => grant_signal(232),
4615	-- grant(233) => grant_signal(233),
4616	-- grant(234) => grant_signal(234),
4617	-- grant(235) => grant_signal(235),
4618	-- grant(236) => grant_signal(236),
4619	-- grant(237) => grant_signal(237),
4620	-- grant(238) => grant_signal(238),
4621	-- grant(239) => grant_signal(239),
4622	-- grant(240) => grant_signal(240),
4623	-- fifo_full =>fifo_in_full(15),
4624	-- priority_rotation => priority_rotation_signal(15),
4625	-- fifo_empty => fifo_in_empty(15),
4626	-- data_out =>crossbar_in_port(15),
4627	-- data_out_pulse =>crossbar_in_pulse(15),
4628	-- request(225) =>request_signal(225),
4629	-- request(226) =>request_signal(226),
4630	-- request(227) =>request_signal(227),
4631	-- request(228) =>request_signal(228),
4632	-- request(229) =>request_signal(229),
4633	-- request(230) =>request_signal(230),
4634	-- request(231) =>request_signal(231),
4635	-- request(232) =>request_signal(232),
4636	-- request(233) =>request_signal(233),
4637	-- request(234) =>request_signal(234),
4638	-- request(235) =>request_signal(235),
4639	-- request(236) =>request_signal(236),
4640	-- request(237) =>request_signal(237),
4641	-- request(238) =>request_signal(238),
4642	-- request(239) =>request_signal(239),
4643	-- request(240) =>request_signal(240)
4644	--);
4645	--
4646	--PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4647	--GENERIC MAP(number_of_ports =>16)
4648	--PORT MAP(
4649	-- data_in => Port_in(16),
4650	-- data_in_en => data_in_en(16),
4651	-- reset => reset,
4652	-- clk =>clk,
4653	-- grant(241) => grant_signal(241),
4654	-- grant(242) => grant_signal(242),
4655	-- grant(243) => grant_signal(243),
4656	-- grant(244) => grant_signal(244),
4657	-- grant(245) => grant_signal(245),
4658	-- grant(246) => grant_signal(246),
4659	-- grant(247) => grant_signal(247),
4660	-- grant(248) => grant_signal(248),
4661	-- grant(249) => grant_signal(249),
4662	-- grant(250) => grant_signal(250),
4663	-- grant(251) => grant_signal(251),
4664	-- grant(252) => grant_signal(252),
4665	-- grant(253) => grant_signal(253),
4666	-- grant(254) => grant_signal(254),
4667	-- grant(255) => grant_signal(255),
4668	-- grant(256) => grant_signal(256),
4669	-- fifo_full =>fifo_in_full(16),
4670	-- priority_rotation => priority_rotation_signal(16),
4671	-- fifo_empty => fifo_in_empty(16),
4672	-- data_out =>crossbar_in_port(16),
4673	-- data_out_pulse =>crossbar_in_pulse(16),
4674	-- request(241) =>request_signal(241),
4675	-- request(242) =>request_signal(242),
4676	-- request(243) =>request_signal(243),
4677	-- request(244) =>request_signal(244),
4678	-- request(245) =>request_signal(245),
4679	-- request(246) =>request_signal(246),
4680	-- request(247) =>request_signal(247),
4681	-- request(248) =>request_signal(248),
4682	-- request(249) =>request_signal(249),
4683	-- request(250) =>request_signal(250),
4684	-- request(251) =>request_signal(251),
4685	-- request(252) =>request_signal(252),
4686	-- request(253) =>request_signal(253),
4687	-- request(254) =>request_signal(254),
4688	-- request(255) =>request_signal(255),
4689	-- request(256) =>request_signal(256)
4690	--);
4691	--
4692	--end generate switch16x16;
4693	-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
4694	-- le circuit genere depend du parametre generique nombre de ports
4695	-- switch 2 ports
4696	port_out_switch2x2 : if n_ports = 2 generate
4697
4698	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4699	PORT MAP(
4700	data_in => crossbar_out_port(1),
4701	reset => reset,
4702	clk => clk,
4703	wr_en =>crossbar_out_pulse(1),
4704	data_out =>Port_out(1),
4705	fifo_full =>fifo_out_full_signal(1),
4706	data_avalaible => data_available(1),
4707	rd_out_en => data_out_en(1)
4708	);
4709
4710	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4711	PORT MAP(
4712	data_in => crossbar_out_port(2),
4713	reset => reset,
4714	clk => clk,
4715	wr_en =>crossbar_out_pulse(2),
4716	data_out =>Port_out(2),
4717	fifo_full =>fifo_out_full_signal(2),
4718	data_avalaible => data_available(2),
4719	rd_out_en => data_out_en(2)
4720	);
4721
4722	end generate port_out_switch2x2;
4723
4724
4725	-- switch 3 ports
4726	port_out_switch3x3 : if n_ports = 3 generate
4727
4728	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4729	PORT MAP(
4730	data_in => crossbar_out_port(1),
4731	reset => reset,
4732	clk => clk,
4733	wr_en =>crossbar_out_pulse(1),
4734	data_out =>Port_out(1),
4735	fifo_full =>fifo_out_full_signal(1),
4736	data_avalaible => data_available(1),
4737	rd_out_en => data_out_en(1)
4738	);
4739
4740	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4741	PORT MAP(
4742	data_in => crossbar_out_port(2),
4743	reset => reset,
4744	clk => clk,
4745	wr_en =>crossbar_out_pulse(2),
4746	data_out =>Port_out(2),
4747	fifo_full =>fifo_out_full_signal(2),
4748	data_avalaible => data_available(2),
4749	rd_out_en => data_out_en(2)
4750	);
4751
4752	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4753	PORT MAP(
4754	data_in => crossbar_out_port(3),
4755	reset => reset,
4756	clk => clk,
4757	wr_en =>crossbar_out_pulse(3),
4758	data_out =>Port_out(3),
4759	fifo_full =>fifo_out_full_signal(3),
4760	data_avalaible => data_available(3),
4761	rd_out_en => data_out_en(3)
4762	);
4763
4764	end generate port_out_switch3x3;
4765
4766
4767	-- switch 4 ports
4768	port_out_switch4x4 : if n_ports = 4 generate
4769
4770	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4771	PORT MAP(
4772	data_in => crossbar_out_port(1),
4773	reset => reset,
4774	clk => clk,
4775	wr_en =>crossbar_out_pulse(1),
4776	data_out =>Port_out(1),
4777	fifo_full =>fifo_out_full_signal(1),
4778	data_avalaible => data_available(1),
4779	rd_out_en => data_out_en(1)
4780	);
4781
4782	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4783	PORT MAP(
4784	data_in => crossbar_out_port(2),
4785	reset => reset,
4786	clk => clk,
4787	wr_en =>crossbar_out_pulse(2),
4788	data_out =>Port_out(2),
4789	fifo_full =>fifo_out_full_signal(2),
4790	data_avalaible => data_available(2),
4791	rd_out_en => data_out_en(2)
4792	);
4793
4794	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4795	PORT MAP(
4796	data_in => crossbar_out_port(3),
4797	reset => reset,
4798	clk => clk,
4799	wr_en =>crossbar_out_pulse(3),
4800	data_out =>Port_out(3),
4801	fifo_full =>fifo_out_full_signal(3),
4802	data_avalaible => data_available(3),
4803	rd_out_en => data_out_en(3)
4804	);
4805
4806	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4807	PORT MAP(
4808	data_in => crossbar_out_port(4),
4809	reset => reset,
4810	clk => clk,
4811	wr_en =>crossbar_out_pulse(4),
4812	data_out =>Port_out(4),
4813	fifo_full =>fifo_out_full_signal(4),
4814	data_avalaible => data_available(4),
4815	rd_out_en => data_out_en(4)
4816	);
4817
4818	end generate port_out_switch4x4;
4819
4820
4821	-- switch 5 ports
4822	port_out_switch5x5 : if n_ports = 5 generate
4823
4824	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4825	PORT MAP(
4826	data_in => crossbar_out_port(1),
4827	reset => reset,
4828	clk => clk,
4829	wr_en =>crossbar_out_pulse(1),
4830	data_out =>Port_out(1),
4831	fifo_full =>fifo_out_full_signal(1),
4832	data_avalaible => data_available(1),
4833	rd_out_en => data_out_en(1)
4834	);
4835
4836	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4837	PORT MAP(
4838	data_in => crossbar_out_port(2),
4839	reset => reset,
4840	clk => clk,
4841	wr_en =>crossbar_out_pulse(2),
4842	data_out =>Port_out(2),
4843	fifo_full =>fifo_out_full_signal(2),
4844	data_avalaible => data_available(2),
4845	rd_out_en => data_out_en(2)
4846	);
4847
4848	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4849	PORT MAP(
4850	data_in => crossbar_out_port(3),
4851	reset => reset,
4852	clk => clk,
4853	wr_en =>crossbar_out_pulse(3),
4854	data_out =>Port_out(3),
4855	fifo_full =>fifo_out_full_signal(3),
4856	data_avalaible => data_available(3),
4857	rd_out_en => data_out_en(3)
4858	);
4859
4860	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4861	PORT MAP(
4862	data_in => crossbar_out_port(4),
4863	reset => reset,
4864	clk => clk,
4865	wr_en =>crossbar_out_pulse(4),
4866	data_out =>Port_out(4),
4867	fifo_full =>fifo_out_full_signal(4),
4868	data_avalaible => data_available(4),
4869	rd_out_en => data_out_en(4)
4870	);
4871
4872	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4873	PORT MAP(
4874	data_in => crossbar_out_port(5),
4875	reset => reset,
4876	clk => clk,
4877	wr_en =>crossbar_out_pulse(5),
4878	data_out =>Port_out(5),
4879	fifo_full =>fifo_out_full_signal(5),
4880	data_avalaible => data_available(5),
4881	rd_out_en => data_out_en(5)
4882	);
4883
4884	end generate port_out_switch5x5;
4885
4886
4887	-- switch 6 ports
4888	port_out_switch6x6 : if n_ports = 6 generate
4889
4890	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4891	PORT MAP(
4892	data_in => crossbar_out_port(1),
4893	reset => reset,
4894	clk => clk,
4895	wr_en =>crossbar_out_pulse(1),
4896	data_out =>Port_out(1),
4897	fifo_full =>fifo_out_full_signal(1),
4898	data_avalaible => data_available(1),
4899	rd_out_en => data_out_en(1)
4900	);
4901
4902	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4903	PORT MAP(
4904	data_in => crossbar_out_port(2),
4905	reset => reset,
4906	clk => clk,
4907	wr_en =>crossbar_out_pulse(2),
4908	data_out =>Port_out(2),
4909	fifo_full =>fifo_out_full_signal(2),
4910	data_avalaible => data_available(2),
4911	rd_out_en => data_out_en(2)
4912	);
4913
4914	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4915	PORT MAP(
4916	data_in => crossbar_out_port(3),
4917	reset => reset,
4918	clk => clk,
4919	wr_en =>crossbar_out_pulse(3),
4920	data_out =>Port_out(3),
4921	fifo_full =>fifo_out_full_signal(3),
4922	data_avalaible => data_available(3),
4923	rd_out_en => data_out_en(3)
4924	);
4925
4926	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4927	PORT MAP(
4928	data_in => crossbar_out_port(4),
4929	reset => reset,
4930	clk => clk,
4931	wr_en =>crossbar_out_pulse(4),
4932	data_out =>Port_out(4),
4933	fifo_full =>fifo_out_full_signal(4),
4934	data_avalaible => data_available(4),
4935	rd_out_en => data_out_en(4)
4936	);
4937
4938	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4939	PORT MAP(
4940	data_in => crossbar_out_port(5),
4941	reset => reset,
4942	clk => clk,
4943	wr_en =>crossbar_out_pulse(5),
4944	data_out =>Port_out(5),
4945	fifo_full =>fifo_out_full_signal(5),
4946	data_avalaible => data_available(5),
4947	rd_out_en => data_out_en(5)
4948	);
4949
4950	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4951	PORT MAP(
4952	data_in => crossbar_out_port(6),
4953	reset => reset,
4954	clk => clk,
4955	wr_en =>crossbar_out_pulse(6),
4956	data_out =>Port_out(6),
4957	fifo_full =>fifo_out_full_signal(6),
4958	data_avalaible => data_available(6),
4959	rd_out_en => data_out_en(6)
4960	);
4961
4962	end generate port_out_switch6x6;
4963
4964
4965	-- switch 7 ports
4966	port_out_switch7x7 : if n_ports = 7 generate
4967
4968	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4969	PORT MAP(
4970	data_in => crossbar_out_port(1),
4971	reset => reset,
4972	clk => clk,
4973	wr_en =>crossbar_out_pulse(1),
4974	data_out =>Port_out(1),
4975	fifo_full =>fifo_out_full_signal(1),
4976	data_avalaible => data_available(1),
4977	rd_out_en => data_out_en(1)
4978	);
4979
4980	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4981	PORT MAP(
4982	data_in => crossbar_out_port(2),
4983	reset => reset,
4984	clk => clk,
4985	wr_en =>crossbar_out_pulse(2),
4986	data_out =>Port_out(2),
4987	fifo_full =>fifo_out_full_signal(2),
4988	data_avalaible => data_available(2),
4989	rd_out_en => data_out_en(2)
4990	);
4991
4992	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4993	PORT MAP(
4994	data_in => crossbar_out_port(3),
4995	reset => reset,
4996	clk => clk,
4997	wr_en =>crossbar_out_pulse(3),
4998	data_out =>Port_out(3),
4999	fifo_full =>fifo_out_full_signal(3),
5000	data_avalaible => data_available(3),
5001	rd_out_en => data_out_en(3)
5002	);
5003
5004	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5005	PORT MAP(
5006	data_in => crossbar_out_port(4),
5007	reset => reset,
5008	clk => clk,
5009	wr_en =>crossbar_out_pulse(4),
5010	data_out =>Port_out(4),
5011	fifo_full =>fifo_out_full_signal(4),
5012	data_avalaible => data_available(4),
5013	rd_out_en => data_out_en(4)
5014	);
5015
5016	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5017	PORT MAP(
5018	data_in => crossbar_out_port(5),
5019	reset => reset,
5020	clk => clk,
5021	wr_en =>crossbar_out_pulse(5),
5022	data_out =>Port_out(5),
5023	fifo_full =>fifo_out_full_signal(5),
5024	data_avalaible => data_available(5),
5025	rd_out_en => data_out_en(5)
5026	);
5027
5028	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5029	PORT MAP(
5030	data_in => crossbar_out_port(6),
5031	reset => reset,
5032	clk => clk,
5033	wr_en =>crossbar_out_pulse(6),
5034	data_out =>Port_out(6),
5035	fifo_full =>fifo_out_full_signal(6),
5036	data_avalaible => data_available(6),
5037	rd_out_en => data_out_en(6)
5038	);
5039
5040	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5041	PORT MAP(
5042	data_in => crossbar_out_port(7),
5043	reset => reset,
5044	clk => clk,
5045	wr_en =>crossbar_out_pulse(7),
5046	data_out =>Port_out(7),
5047	fifo_full =>fifo_out_full_signal(7),
5048	data_avalaible => data_available(7),
5049	rd_out_en => data_out_en(7)
5050	);
5051
5052	end generate port_out_switch7x7;
5053
5054
5055	-- switch 8 ports
5056	port_out_switch8x8 : if n_ports = 8 generate
5057
5058	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5059	PORT MAP(
5060	data_in => crossbar_out_port(1),
5061	reset => reset,
5062	clk => clk,
5063	wr_en =>crossbar_out_pulse(1),
5064	data_out =>Port_out(1),
5065	fifo_full =>fifo_out_full_signal(1),
5066	data_avalaible => data_available(1),
5067	rd_out_en => data_out_en(1)
5068	);
5069
5070	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5071	PORT MAP(
5072	data_in => crossbar_out_port(2),
5073	reset => reset,
5074	clk => clk,
5075	wr_en =>crossbar_out_pulse(2),
5076	data_out =>Port_out(2),
5077	fifo_full =>fifo_out_full_signal(2),
5078	data_avalaible => data_available(2),
5079	rd_out_en => data_out_en(2)
5080	);
5081
5082	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5083	PORT MAP(
5084	data_in => crossbar_out_port(3),
5085	reset => reset,
5086	clk => clk,
5087	wr_en =>crossbar_out_pulse(3),
5088	data_out =>Port_out(3),
5089	fifo_full =>fifo_out_full_signal(3),
5090	data_avalaible => data_available(3),
5091	rd_out_en => data_out_en(3)
5092	);
5093
5094	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5095	PORT MAP(
5096	data_in => crossbar_out_port(4),
5097	reset => reset,
5098	clk => clk,
5099	wr_en =>crossbar_out_pulse(4),
5100	data_out =>Port_out(4),
5101	fifo_full =>fifo_out_full_signal(4),
5102	data_avalaible => data_available(4),
5103	rd_out_en => data_out_en(4)
5104	);
5105
5106	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5107	PORT MAP(
5108	data_in => crossbar_out_port(5),
5109	reset => reset,
5110	clk => clk,
5111	wr_en =>crossbar_out_pulse(5),
5112	data_out =>Port_out(5),
5113	fifo_full =>fifo_out_full_signal(5),
5114	data_avalaible => data_available(5),
5115	rd_out_en => data_out_en(5)
5116	);
5117
5118	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5119	PORT MAP(
5120	data_in => crossbar_out_port(6),
5121	reset => reset,
5122	clk => clk,
5123	wr_en =>crossbar_out_pulse(6),
5124	data_out =>Port_out(6),
5125	fifo_full =>fifo_out_full_signal(6),
5126	data_avalaible => data_available(6),
5127	rd_out_en => data_out_en(6)
5128	);
5129
5130	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5131	PORT MAP(
5132	data_in => crossbar_out_port(7),
5133	reset => reset,
5134	clk => clk,
5135	wr_en =>crossbar_out_pulse(7),
5136	data_out =>Port_out(7),
5137	fifo_full =>fifo_out_full_signal(7),
5138	data_avalaible => data_available(7),
5139	rd_out_en => data_out_en(7)
5140	);
5141
5142	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5143	PORT MAP(
5144	data_in => crossbar_out_port(8),
5145	reset => reset,
5146	clk => clk,
5147	wr_en =>crossbar_out_pulse(8),
5148	data_out =>Port_out(8),
5149	fifo_full =>fifo_out_full_signal(8),
5150	data_avalaible => data_available(8),
5151	rd_out_en => data_out_en(8)
5152	);
5153
5154	end generate port_out_switch8x8;
5155
5156
5157	-- switch 9 ports
5158	port_out_switch9x9 : if n_ports = 9 generate
5159
5160	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5161	PORT MAP(
5162	data_in => crossbar_out_port(1),
5163	reset => reset,
5164	clk => clk,
5165	wr_en =>crossbar_out_pulse(1),
5166	data_out =>Port_out(1),
5167	fifo_full =>fifo_out_full_signal(1),
5168	data_avalaible => data_available(1),
5169	rd_out_en => data_out_en(1)
5170	);
5171
5172	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5173	PORT MAP(
5174	data_in => crossbar_out_port(2),
5175	reset => reset,
5176	clk => clk,
5177	wr_en =>crossbar_out_pulse(2),
5178	data_out =>Port_out(2),
5179	fifo_full =>fifo_out_full_signal(2),
5180	data_avalaible => data_available(2),
5181	rd_out_en => data_out_en(2)
5182	);
5183
5184	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5185	PORT MAP(
5186	data_in => crossbar_out_port(3),
5187	reset => reset,
5188	clk => clk,
5189	wr_en =>crossbar_out_pulse(3),
5190	data_out =>Port_out(3),
5191	fifo_full =>fifo_out_full_signal(3),
5192	data_avalaible => data_available(3),
5193	rd_out_en => data_out_en(3)
5194	);
5195
5196	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5197	PORT MAP(
5198	data_in => crossbar_out_port(4),
5199	reset => reset,
5200	clk => clk,
5201	wr_en =>crossbar_out_pulse(4),
5202	data_out =>Port_out(4),
5203	fifo_full =>fifo_out_full_signal(4),
5204	data_avalaible => data_available(4),
5205	rd_out_en => data_out_en(4)
5206	);
5207
5208	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5209	PORT MAP(
5210	data_in => crossbar_out_port(5),
5211	reset => reset,
5212	clk => clk,
5213	wr_en =>crossbar_out_pulse(5),
5214	data_out =>Port_out(5),
5215	fifo_full =>fifo_out_full_signal(5),
5216	data_avalaible => data_available(5),
5217	rd_out_en => data_out_en(5)
5218	);
5219
5220	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5221	PORT MAP(
5222	data_in => crossbar_out_port(6),
5223	reset => reset,
5224	clk => clk,
5225	wr_en =>crossbar_out_pulse(6),
5226	data_out =>Port_out(6),
5227	fifo_full =>fifo_out_full_signal(6),
5228	data_avalaible => data_available(6),
5229	rd_out_en => data_out_en(6)
5230	);
5231
5232	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5233	PORT MAP(
5234	data_in => crossbar_out_port(7),
5235	reset => reset,
5236	clk => clk,
5237	wr_en =>crossbar_out_pulse(7),
5238	data_out =>Port_out(7),
5239	fifo_full =>fifo_out_full_signal(7),
5240	data_avalaible => data_available(7),
5241	rd_out_en => data_out_en(7)
5242	);
5243
5244	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5245	PORT MAP(
5246	data_in => crossbar_out_port(8),
5247	reset => reset,
5248	clk => clk,
5249	wr_en =>crossbar_out_pulse(8),
5250	data_out =>Port_out(8),
5251	fifo_full =>fifo_out_full_signal(8),
5252	data_avalaible => data_available(8),
5253	rd_out_en => data_out_en(8)
5254	);
5255
5256	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5257	PORT MAP(
5258	data_in => crossbar_out_port(9),
5259	reset => reset,
5260	clk => clk,
5261	wr_en =>crossbar_out_pulse(9),
5262	data_out =>Port_out(9),
5263	fifo_full =>fifo_out_full_signal(9),
5264	data_avalaible => data_available(9),
5265	rd_out_en => data_out_en(9)
5266	);
5267
5268	end generate port_out_switch9x9;
5269
5270
5271	-- switch 10 ports
5272	port_out_switch10x10 : if n_ports = 10 generate
5273
5274	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5275	PORT MAP(
5276	data_in => crossbar_out_port(1),
5277	reset => reset,
5278	clk => clk,
5279	wr_en =>crossbar_out_pulse(1),
5280	data_out =>Port_out(1),
5281	fifo_full =>fifo_out_full_signal(1),
5282	data_avalaible => data_available(1),
5283	rd_out_en => data_out_en(1)
5284	);
5285
5286	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5287	PORT MAP(
5288	data_in => crossbar_out_port(2),
5289	reset => reset,
5290	clk => clk,
5291	wr_en =>crossbar_out_pulse(2),
5292	data_out =>Port_out(2),
5293	fifo_full =>fifo_out_full_signal(2),
5294	data_avalaible => data_available(2),
5295	rd_out_en => data_out_en(2)
5296	);
5297
5298	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5299	PORT MAP(
5300	data_in => crossbar_out_port(3),
5301	reset => reset,
5302	clk => clk,
5303	wr_en =>crossbar_out_pulse(3),
5304	data_out =>Port_out(3),
5305	fifo_full =>fifo_out_full_signal(3),
5306	data_avalaible => data_available(3),
5307	rd_out_en => data_out_en(3)
5308	);
5309
5310	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5311	PORT MAP(
5312	data_in => crossbar_out_port(4),
5313	reset => reset,
5314	clk => clk,
5315	wr_en =>crossbar_out_pulse(4),
5316	data_out =>Port_out(4),
5317	fifo_full =>fifo_out_full_signal(4),
5318	data_avalaible => data_available(4),
5319	rd_out_en => data_out_en(4)
5320	);
5321
5322	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5323	PORT MAP(
5324	data_in => crossbar_out_port(5),
5325	reset => reset,
5326	clk => clk,
5327	wr_en =>crossbar_out_pulse(5),
5328	data_out =>Port_out(5),
5329	fifo_full =>fifo_out_full_signal(5),
5330	data_avalaible => data_available(5),
5331	rd_out_en => data_out_en(5)
5332	);
5333
5334	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5335	PORT MAP(
5336	data_in => crossbar_out_port(6),
5337	reset => reset,
5338	clk => clk,
5339	wr_en =>crossbar_out_pulse(6),
5340	data_out =>Port_out(6),
5341	fifo_full =>fifo_out_full_signal(6),
5342	data_avalaible => data_available(6),
5343	rd_out_en => data_out_en(6)
5344	);
5345
5346	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5347	PORT MAP(
5348	data_in => crossbar_out_port(7),
5349	reset => reset,
5350	clk => clk,
5351	wr_en =>crossbar_out_pulse(7),
5352	data_out =>Port_out(7),
5353	fifo_full =>fifo_out_full_signal(7),
5354	data_avalaible => data_available(7),
5355	rd_out_en => data_out_en(7)
5356	);
5357
5358	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5359	PORT MAP(
5360	data_in => crossbar_out_port(8),
5361	reset => reset,
5362	clk => clk,
5363	wr_en =>crossbar_out_pulse(8),
5364	data_out =>Port_out(8),
5365	fifo_full =>fifo_out_full_signal(8),
5366	data_avalaible => data_available(8),
5367	rd_out_en => data_out_en(8)
5368	);
5369
5370	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5371	PORT MAP(
5372	data_in => crossbar_out_port(9),
5373	reset => reset,
5374	clk => clk,
5375	wr_en =>crossbar_out_pulse(9),
5376	data_out =>Port_out(9),
5377	fifo_full =>fifo_out_full_signal(9),
5378	data_avalaible => data_available(9),
5379	rd_out_en => data_out_en(9)
5380	);
5381
5382	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5383	PORT MAP(
5384	data_in => crossbar_out_port(10),
5385	reset => reset,
5386	clk => clk,
5387	wr_en =>crossbar_out_pulse(10),
5388	data_out =>Port_out(10),
5389	fifo_full =>fifo_out_full_signal(10),
5390	data_avalaible => data_available(10),
5391	rd_out_en => data_out_en(10)
5392	);
5393
5394	end generate port_out_switch10x10;
5395
5396
5397	-- switch 11 ports
5398	port_out_switch11x11 : if n_ports = 11 generate
5399
5400	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5401	PORT MAP(
5402	data_in => crossbar_out_port(1),
5403	reset => reset,
5404	clk => clk,
5405	wr_en =>crossbar_out_pulse(1),
5406	data_out =>Port_out(1),
5407	fifo_full =>fifo_out_full_signal(1),
5408	data_avalaible => data_available(1),
5409	rd_out_en => data_out_en(1)
5410	);
5411
5412	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5413	PORT MAP(
5414	data_in => crossbar_out_port(2),
5415	reset => reset,
5416	clk => clk,
5417	wr_en =>crossbar_out_pulse(2),
5418	data_out =>Port_out(2),
5419	fifo_full =>fifo_out_full_signal(2),
5420	data_avalaible => data_available(2),
5421	rd_out_en => data_out_en(2)
5422	);
5423
5424	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5425	PORT MAP(
5426	data_in => crossbar_out_port(3),
5427	reset => reset,
5428	clk => clk,
5429	wr_en =>crossbar_out_pulse(3),
5430	data_out =>Port_out(3),
5431	fifo_full =>fifo_out_full_signal(3),
5432	data_avalaible => data_available(3),
5433	rd_out_en => data_out_en(3)
5434	);
5435
5436	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5437	PORT MAP(
5438	data_in => crossbar_out_port(4),
5439	reset => reset,
5440	clk => clk,
5441	wr_en =>crossbar_out_pulse(4),
5442	data_out =>Port_out(4),
5443	fifo_full =>fifo_out_full_signal(4),
5444	data_avalaible => data_available(4),
5445	rd_out_en => data_out_en(4)
5446	);
5447
5448	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5449	PORT MAP(
5450	data_in => crossbar_out_port(5),
5451	reset => reset,
5452	clk => clk,
5453	wr_en =>crossbar_out_pulse(5),
5454	data_out =>Port_out(5),
5455	fifo_full =>fifo_out_full_signal(5),
5456	data_avalaible => data_available(5),
5457	rd_out_en => data_out_en(5)
5458	);
5459
5460	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5461	PORT MAP(
5462	data_in => crossbar_out_port(6),
5463	reset => reset,
5464	clk => clk,
5465	wr_en =>crossbar_out_pulse(6),
5466	data_out =>Port_out(6),
5467	fifo_full =>fifo_out_full_signal(6),
5468	data_avalaible => data_available(6),
5469	rd_out_en => data_out_en(6)
5470	);
5471
5472	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5473	PORT MAP(
5474	data_in => crossbar_out_port(7),
5475	reset => reset,
5476	clk => clk,
5477	wr_en =>crossbar_out_pulse(7),
5478	data_out =>Port_out(7),
5479	fifo_full =>fifo_out_full_signal(7),
5480	data_avalaible => data_available(7),
5481	rd_out_en => data_out_en(7)
5482	);
5483
5484	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5485	PORT MAP(
5486	data_in => crossbar_out_port(8),
5487	reset => reset,
5488	clk => clk,
5489	wr_en =>crossbar_out_pulse(8),
5490	data_out =>Port_out(8),
5491	fifo_full =>fifo_out_full_signal(8),
5492	data_avalaible => data_available(8),
5493	rd_out_en => data_out_en(8)
5494	);
5495
5496	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5497	PORT MAP(
5498	data_in => crossbar_out_port(9),
5499	reset => reset,
5500	clk => clk,
5501	wr_en =>crossbar_out_pulse(9),
5502	data_out =>Port_out(9),
5503	fifo_full =>fifo_out_full_signal(9),
5504	data_avalaible => data_available(9),
5505	rd_out_en => data_out_en(9)
5506	);
5507
5508	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5509	PORT MAP(
5510	data_in => crossbar_out_port(10),
5511	reset => reset,
5512	clk => clk,
5513	wr_en =>crossbar_out_pulse(10),
5514	data_out =>Port_out(10),
5515	fifo_full =>fifo_out_full_signal(10),
5516	data_avalaible => data_available(10),
5517	rd_out_en => data_out_en(10)
5518	);
5519
5520	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5521	PORT MAP(
5522	data_in => crossbar_out_port(11),
5523	reset => reset,
5524	clk => clk,
5525	wr_en =>crossbar_out_pulse(11),
5526	data_out =>Port_out(11),
5527	fifo_full =>fifo_out_full_signal(11),
5528	data_avalaible => data_available(11),
5529	rd_out_en => data_out_en(11)
5530	);
5531
5532	end generate port_out_switch11x11;
5533
5534
5535	-- switch 12 ports
5536	port_out_switch12x12 : if n_ports = 12 generate
5537
5538	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5539	PORT MAP(
5540	data_in => crossbar_out_port(1),
5541	reset => reset,
5542	clk => clk,
5543	wr_en =>crossbar_out_pulse(1),
5544	data_out =>Port_out(1),
5545	fifo_full =>fifo_out_full_signal(1),
5546	data_avalaible => data_available(1),
5547	rd_out_en => data_out_en(1)
5548	);
5549
5550	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5551	PORT MAP(
5552	data_in => crossbar_out_port(2),
5553	reset => reset,
5554	clk => clk,
5555	wr_en =>crossbar_out_pulse(2),
5556	data_out =>Port_out(2),
5557	fifo_full =>fifo_out_full_signal(2),
5558	data_avalaible => data_available(2),
5559	rd_out_en => data_out_en(2)
5560	);
5561
5562	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5563	PORT MAP(
5564	data_in => crossbar_out_port(3),
5565	reset => reset,
5566	clk => clk,
5567	wr_en =>crossbar_out_pulse(3),
5568	data_out =>Port_out(3),
5569	fifo_full =>fifo_out_full_signal(3),
5570	data_avalaible => data_available(3),
5571	rd_out_en => data_out_en(3)
5572	);
5573
5574	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5575	PORT MAP(
5576	data_in => crossbar_out_port(4),
5577	reset => reset,
5578	clk => clk,
5579	wr_en =>crossbar_out_pulse(4),
5580	data_out =>Port_out(4),
5581	fifo_full =>fifo_out_full_signal(4),
5582	data_avalaible => data_available(4),
5583	rd_out_en => data_out_en(4)
5584	);
5585
5586	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5587	PORT MAP(
5588	data_in => crossbar_out_port(5),
5589	reset => reset,
5590	clk => clk,
5591	wr_en =>crossbar_out_pulse(5),
5592	data_out =>Port_out(5),
5593	fifo_full =>fifo_out_full_signal(5),
5594	data_avalaible => data_available(5),
5595	rd_out_en => data_out_en(5)
5596	);
5597
5598	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5599	PORT MAP(
5600	data_in => crossbar_out_port(6),
5601	reset => reset,
5602	clk => clk,
5603	wr_en =>crossbar_out_pulse(6),
5604	data_out =>Port_out(6),
5605	fifo_full =>fifo_out_full_signal(6),
5606	data_avalaible => data_available(6),
5607	rd_out_en => data_out_en(6)
5608	);
5609
5610	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5611	PORT MAP(
5612	data_in => crossbar_out_port(7),
5613	reset => reset,
5614	clk => clk,
5615	wr_en =>crossbar_out_pulse(7),
5616	data_out =>Port_out(7),
5617	fifo_full =>fifo_out_full_signal(7),
5618	data_avalaible => data_available(7),
5619	rd_out_en => data_out_en(7)
5620	);
5621
5622	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5623	PORT MAP(
5624	data_in => crossbar_out_port(8),
5625	reset => reset,
5626	clk => clk,
5627	wr_en =>crossbar_out_pulse(8),
5628	data_out =>Port_out(8),
5629	fifo_full =>fifo_out_full_signal(8),
5630	data_avalaible => data_available(8),
5631	rd_out_en => data_out_en(8)
5632	);
5633
5634	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5635	PORT MAP(
5636	data_in => crossbar_out_port(9),
5637	reset => reset,
5638	clk => clk,
5639	wr_en =>crossbar_out_pulse(9),
5640	data_out =>Port_out(9),
5641	fifo_full =>fifo_out_full_signal(9),
5642	data_avalaible => data_available(9),
5643	rd_out_en => data_out_en(9)
5644	);
5645
5646	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5647	PORT MAP(
5648	data_in => crossbar_out_port(10),
5649	reset => reset,
5650	clk => clk,
5651	wr_en =>crossbar_out_pulse(10),
5652	data_out =>Port_out(10),
5653	fifo_full =>fifo_out_full_signal(10),
5654	data_avalaible => data_available(10),
5655	rd_out_en => data_out_en(10)
5656	);
5657
5658	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5659	PORT MAP(
5660	data_in => crossbar_out_port(11),
5661	reset => reset,
5662	clk => clk,
5663	wr_en =>crossbar_out_pulse(11),
5664	data_out =>Port_out(11),
5665	fifo_full =>fifo_out_full_signal(11),
5666	data_avalaible => data_available(11),
5667	rd_out_en => data_out_en(11)
5668	);
5669
5670	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5671	PORT MAP(
5672	data_in => crossbar_out_port(12),
5673	reset => reset,
5674	clk => clk,
5675	wr_en =>crossbar_out_pulse(12),
5676	data_out =>Port_out(12),
5677	fifo_full =>fifo_out_full_signal(12),
5678	data_avalaible => data_available(12),
5679	rd_out_en => data_out_en(12)
5680	);
5681
5682	end generate port_out_switch12x12;
5683
5684
5685	-- switch 13 ports
5686	port_out_switch13x13 : if n_ports = 13 generate
5687
5688	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5689	PORT MAP(
5690	data_in => crossbar_out_port(1),
5691	reset => reset,
5692	clk => clk,
5693	wr_en =>crossbar_out_pulse(1),
5694	data_out =>Port_out(1),
5695	fifo_full =>fifo_out_full_signal(1),
5696	data_avalaible => data_available(1),
5697	rd_out_en => data_out_en(1)
5698	);
5699
5700	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5701	PORT MAP(
5702	data_in => crossbar_out_port(2),
5703	reset => reset,
5704	clk => clk,
5705	wr_en =>crossbar_out_pulse(2),
5706	data_out =>Port_out(2),
5707	fifo_full =>fifo_out_full_signal(2),
5708	data_avalaible => data_available(2),
5709	rd_out_en => data_out_en(2)
5710	);
5711
5712	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5713	PORT MAP(
5714	data_in => crossbar_out_port(3),
5715	reset => reset,
5716	clk => clk,
5717	wr_en =>crossbar_out_pulse(3),
5718	data_out =>Port_out(3),
5719	fifo_full =>fifo_out_full_signal(3),
5720	data_avalaible => data_available(3),
5721	rd_out_en => data_out_en(3)
5722	);
5723
5724	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5725	PORT MAP(
5726	data_in => crossbar_out_port(4),
5727	reset => reset,
5728	clk => clk,
5729	wr_en =>crossbar_out_pulse(4),
5730	data_out =>Port_out(4),
5731	fifo_full =>fifo_out_full_signal(4),
5732	data_avalaible => data_available(4),
5733	rd_out_en => data_out_en(4)
5734	);
5735
5736	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5737	PORT MAP(
5738	data_in => crossbar_out_port(5),
5739	reset => reset,
5740	clk => clk,
5741	wr_en =>crossbar_out_pulse(5),
5742	data_out =>Port_out(5),
5743	fifo_full =>fifo_out_full_signal(5),
5744	data_avalaible => data_available(5),
5745	rd_out_en => data_out_en(5)
5746	);
5747
5748	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5749	PORT MAP(
5750	data_in => crossbar_out_port(6),
5751	reset => reset,
5752	clk => clk,
5753	wr_en =>crossbar_out_pulse(6),
5754	data_out =>Port_out(6),
5755	fifo_full =>fifo_out_full_signal(6),
5756	data_avalaible => data_available(6),
5757	rd_out_en => data_out_en(6)
5758	);
5759
5760	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5761	PORT MAP(
5762	data_in => crossbar_out_port(7),
5763	reset => reset,
5764	clk => clk,
5765	wr_en =>crossbar_out_pulse(7),
5766	data_out =>Port_out(7),
5767	fifo_full =>fifo_out_full_signal(7),
5768	data_avalaible => data_available(7),
5769	rd_out_en => data_out_en(7)
5770	);
5771
5772	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5773	PORT MAP(
5774	data_in => crossbar_out_port(8),
5775	reset => reset,
5776	clk => clk,
5777	wr_en =>crossbar_out_pulse(8),
5778	data_out =>Port_out(8),
5779	fifo_full =>fifo_out_full_signal(8),
5780	data_avalaible => data_available(8),
5781	rd_out_en => data_out_en(8)
5782	);
5783
5784	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5785	PORT MAP(
5786	data_in => crossbar_out_port(9),
5787	reset => reset,
5788	clk => clk,
5789	wr_en =>crossbar_out_pulse(9),
5790	data_out =>Port_out(9),
5791	fifo_full =>fifo_out_full_signal(9),
5792	data_avalaible => data_available(9),
5793	rd_out_en => data_out_en(9)
5794	);
5795
5796	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5797	PORT MAP(
5798	data_in => crossbar_out_port(10),
5799	reset => reset,
5800	clk => clk,
5801	wr_en =>crossbar_out_pulse(10),
5802	data_out =>Port_out(10),
5803	fifo_full =>fifo_out_full_signal(10),
5804	data_avalaible => data_available(10),
5805	rd_out_en => data_out_en(10)
5806	);
5807
5808	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5809	PORT MAP(
5810	data_in => crossbar_out_port(11),
5811	reset => reset,
5812	clk => clk,
5813	wr_en =>crossbar_out_pulse(11),
5814	data_out =>Port_out(11),
5815	fifo_full =>fifo_out_full_signal(11),
5816	data_avalaible => data_available(11),
5817	rd_out_en => data_out_en(11)
5818	);
5819
5820	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5821	PORT MAP(
5822	data_in => crossbar_out_port(12),
5823	reset => reset,
5824	clk => clk,
5825	wr_en =>crossbar_out_pulse(12),
5826	data_out =>Port_out(12),
5827	fifo_full =>fifo_out_full_signal(12),
5828	data_avalaible => data_available(12),
5829	rd_out_en => data_out_en(12)
5830	);
5831
5832	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5833	PORT MAP(
5834	data_in => crossbar_out_port(13),
5835	reset => reset,
5836	clk => clk,
5837	wr_en =>crossbar_out_pulse(13),
5838	data_out =>Port_out(13),
5839	fifo_full =>fifo_out_full_signal(13),
5840	data_avalaible => data_available(13),
5841	rd_out_en => data_out_en(13)
5842	);
5843
5844	end generate port_out_switch13x13;
5845
5846
5847	-- switch 14 ports
5848	port_out_switch14x14 : if n_ports = 14 generate
5849
5850	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5851	PORT MAP(
5852	data_in => crossbar_out_port(1),
5853	reset => reset,
5854	clk => clk,
5855	wr_en =>crossbar_out_pulse(1),
5856	data_out =>Port_out(1),
5857	fifo_full =>fifo_out_full_signal(1),
5858	data_avalaible => data_available(1),
5859	rd_out_en => data_out_en(1)
5860	);
5861
5862	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5863	PORT MAP(
5864	data_in => crossbar_out_port(2),
5865	reset => reset,
5866	clk => clk,
5867	wr_en =>crossbar_out_pulse(2),
5868	data_out =>Port_out(2),
5869	fifo_full =>fifo_out_full_signal(2),
5870	data_avalaible => data_available(2),
5871	rd_out_en => data_out_en(2)
5872	);
5873
5874	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5875	PORT MAP(
5876	data_in => crossbar_out_port(3),
5877	reset => reset,
5878	clk => clk,
5879	wr_en =>crossbar_out_pulse(3),
5880	data_out =>Port_out(3),
5881	fifo_full =>fifo_out_full_signal(3),
5882	data_avalaible => data_available(3),
5883	rd_out_en => data_out_en(3)
5884	);
5885
5886	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5887	PORT MAP(
5888	data_in => crossbar_out_port(4),
5889	reset => reset,
5890	clk => clk,
5891	wr_en =>crossbar_out_pulse(4),
5892	data_out =>Port_out(4),
5893	fifo_full =>fifo_out_full_signal(4),
5894	data_avalaible => data_available(4),
5895	rd_out_en => data_out_en(4)
5896	);
5897
5898	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5899	PORT MAP(
5900	data_in => crossbar_out_port(5),
5901	reset => reset,
5902	clk => clk,
5903	wr_en =>crossbar_out_pulse(5),
5904	data_out =>Port_out(5),
5905	fifo_full =>fifo_out_full_signal(5),
5906	data_avalaible => data_available(5),
5907	rd_out_en => data_out_en(5)
5908	);
5909
5910	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5911	PORT MAP(
5912	data_in => crossbar_out_port(6),
5913	reset => reset,
5914	clk => clk,
5915	wr_en =>crossbar_out_pulse(6),
5916	data_out =>Port_out(6),
5917	fifo_full =>fifo_out_full_signal(6),
5918	data_avalaible => data_available(6),
5919	rd_out_en => data_out_en(6)
5920	);
5921
5922	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5923	PORT MAP(
5924	data_in => crossbar_out_port(7),
5925	reset => reset,
5926	clk => clk,
5927	wr_en =>crossbar_out_pulse(7),
5928	data_out =>Port_out(7),
5929	fifo_full =>fifo_out_full_signal(7),
5930	data_avalaible => data_available(7),
5931	rd_out_en => data_out_en(7)
5932	);
5933
5934	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5935	PORT MAP(
5936	data_in => crossbar_out_port(8),
5937	reset => reset,
5938	clk => clk,
5939	wr_en =>crossbar_out_pulse(8),
5940	data_out =>Port_out(8),
5941	fifo_full =>fifo_out_full_signal(8),
5942	data_avalaible => data_available(8),
5943	rd_out_en => data_out_en(8)
5944	);
5945
5946	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5947	PORT MAP(
5948	data_in => crossbar_out_port(9),
5949	reset => reset,
5950	clk => clk,
5951	wr_en =>crossbar_out_pulse(9),
5952	data_out =>Port_out(9),
5953	fifo_full =>fifo_out_full_signal(9),
5954	data_avalaible => data_available(9),
5955	rd_out_en => data_out_en(9)
5956	);
5957
5958	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5959	PORT MAP(
5960	data_in => crossbar_out_port(10),
5961	reset => reset,
5962	clk => clk,
5963	wr_en =>crossbar_out_pulse(10),
5964	data_out =>Port_out(10),
5965	fifo_full =>fifo_out_full_signal(10),
5966	data_avalaible => data_available(10),
5967	rd_out_en => data_out_en(10)
5968	);
5969
5970	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5971	PORT MAP(
5972	data_in => crossbar_out_port(11),
5973	reset => reset,
5974	clk => clk,
5975	wr_en =>crossbar_out_pulse(11),
5976	data_out =>Port_out(11),
5977	fifo_full =>fifo_out_full_signal(11),
5978	data_avalaible => data_available(11),
5979	rd_out_en => data_out_en(11)
5980	);
5981
5982	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5983	PORT MAP(
5984	data_in => crossbar_out_port(12),
5985	reset => reset,
5986	clk => clk,
5987	wr_en =>crossbar_out_pulse(12),
5988	data_out =>Port_out(12),
5989	fifo_full =>fifo_out_full_signal(12),
5990	data_avalaible => data_available(12),
5991	rd_out_en => data_out_en(12)
5992	);
5993
5994	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5995	PORT MAP(
5996	data_in => crossbar_out_port(13),
5997	reset => reset,
5998	clk => clk,
5999	wr_en =>crossbar_out_pulse(13),
6000	data_out =>Port_out(13),
6001	fifo_full =>fifo_out_full_signal(13),
6002	data_avalaible => data_available(13),
6003	rd_out_en => data_out_en(13)
6004	);
6005
6006	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6007	PORT MAP(
6008	data_in => crossbar_out_port(14),
6009	reset => reset,
6010	clk => clk,
6011	wr_en =>crossbar_out_pulse(14),
6012	data_out =>Port_out(14),
6013	fifo_full =>fifo_out_full_signal(14),
6014	data_avalaible => data_available(14),
6015	rd_out_en => data_out_en(14)
6016	);
6017
6018	end generate port_out_switch14x14;
6019
6020
6021	-- switch 15 ports
6022	port_out_switch15x15 : if n_ports = 15 generate
6023
6024	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6025	PORT MAP(
6026	data_in => crossbar_out_port(1),
6027	reset => reset,
6028	clk => clk,
6029	wr_en =>crossbar_out_pulse(1),
6030	data_out =>Port_out(1),
6031	fifo_full =>fifo_out_full_signal(1),
6032	data_avalaible => data_available(1),
6033	rd_out_en => data_out_en(1)
6034	);
6035
6036	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6037	PORT MAP(
6038	data_in => crossbar_out_port(2),
6039	reset => reset,
6040	clk => clk,
6041	wr_en =>crossbar_out_pulse(2),
6042	data_out =>Port_out(2),
6043	fifo_full =>fifo_out_full_signal(2),
6044	data_avalaible => data_available(2),
6045	rd_out_en => data_out_en(2)
6046	);
6047
6048	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6049	PORT MAP(
6050	data_in => crossbar_out_port(3),
6051	reset => reset,
6052	clk => clk,
6053	wr_en =>crossbar_out_pulse(3),
6054	data_out =>Port_out(3),
6055	fifo_full =>fifo_out_full_signal(3),
6056	data_avalaible => data_available(3),
6057	rd_out_en => data_out_en(3)
6058	);
6059
6060	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6061	PORT MAP(
6062	data_in => crossbar_out_port(4),
6063	reset => reset,
6064	clk => clk,
6065	wr_en =>crossbar_out_pulse(4),
6066	data_out =>Port_out(4),
6067	fifo_full =>fifo_out_full_signal(4),
6068	data_avalaible => data_available(4),
6069	rd_out_en => data_out_en(4)
6070	);
6071
6072	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6073	PORT MAP(
6074	data_in => crossbar_out_port(5),
6075	reset => reset,
6076	clk => clk,
6077	wr_en =>crossbar_out_pulse(5),
6078	data_out =>Port_out(5),
6079	fifo_full =>fifo_out_full_signal(5),
6080	data_avalaible => data_available(5),
6081	rd_out_en => data_out_en(5)
6082	);
6083
6084	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6085	PORT MAP(
6086	data_in => crossbar_out_port(6),
6087	reset => reset,
6088	clk => clk,
6089	wr_en =>crossbar_out_pulse(6),
6090	data_out =>Port_out(6),
6091	fifo_full =>fifo_out_full_signal(6),
6092	data_avalaible => data_available(6),
6093	rd_out_en => data_out_en(6)
6094	);
6095
6096	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6097	PORT MAP(
6098	data_in => crossbar_out_port(7),
6099	reset => reset,
6100	clk => clk,
6101	wr_en =>crossbar_out_pulse(7),
6102	data_out =>Port_out(7),
6103	fifo_full =>fifo_out_full_signal(7),
6104	data_avalaible => data_available(7),
6105	rd_out_en => data_out_en(7)
6106	);
6107
6108	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6109	PORT MAP(
6110	data_in => crossbar_out_port(8),
6111	reset => reset,
6112	clk => clk,
6113	wr_en =>crossbar_out_pulse(8),
6114	data_out =>Port_out(8),
6115	fifo_full =>fifo_out_full_signal(8),
6116	data_avalaible => data_available(8),
6117	rd_out_en => data_out_en(8)
6118	);
6119
6120	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6121	PORT MAP(
6122	data_in => crossbar_out_port(9),
6123	reset => reset,
6124	clk => clk,
6125	wr_en =>crossbar_out_pulse(9),
6126	data_out =>Port_out(9),
6127	fifo_full =>fifo_out_full_signal(9),
6128	data_avalaible => data_available(9),
6129	rd_out_en => data_out_en(9)
6130	);
6131
6132	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6133	PORT MAP(
6134	data_in => crossbar_out_port(10),
6135	reset => reset,
6136	clk => clk,
6137	wr_en =>crossbar_out_pulse(10),
6138	data_out =>Port_out(10),
6139	fifo_full =>fifo_out_full_signal(10),
6140	data_avalaible => data_available(10),
6141	rd_out_en => data_out_en(10)
6142	);
6143
6144	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6145	PORT MAP(
6146	data_in => crossbar_out_port(11),
6147	reset => reset,
6148	clk => clk,
6149	wr_en =>crossbar_out_pulse(11),
6150	data_out =>Port_out(11),
6151	fifo_full =>fifo_out_full_signal(11),
6152	data_avalaible => data_available(11),
6153	rd_out_en => data_out_en(11)
6154	);
6155
6156	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6157	PORT MAP(
6158	data_in => crossbar_out_port(12),
6159	reset => reset,
6160	clk => clk,
6161	wr_en =>crossbar_out_pulse(12),
6162	data_out =>Port_out(12),
6163	fifo_full =>fifo_out_full_signal(12),
6164	data_avalaible => data_available(12),
6165	rd_out_en => data_out_en(12)
6166	);
6167
6168	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6169	PORT MAP(
6170	data_in => crossbar_out_port(13),
6171	reset => reset,
6172	clk => clk,
6173	wr_en =>crossbar_out_pulse(13),
6174	data_out =>Port_out(13),
6175	fifo_full =>fifo_out_full_signal(13),
6176	data_avalaible => data_available(13),
6177	rd_out_en => data_out_en(13)
6178	);
6179
6180	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6181	PORT MAP(
6182	data_in => crossbar_out_port(14),
6183	reset => reset,
6184	clk => clk,
6185	wr_en =>crossbar_out_pulse(14),
6186	data_out =>Port_out(14),
6187	fifo_full =>fifo_out_full_signal(14),
6188	data_avalaible => data_available(14),
6189	rd_out_en => data_out_en(14)
6190	);
6191
6192	PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6193	PORT MAP(
6194	data_in => crossbar_out_port(15),
6195	reset => reset,
6196	clk => clk,
6197	wr_en =>crossbar_out_pulse(15),
6198	data_out =>Port_out(15),
6199	fifo_full =>fifo_out_full_signal(15),
6200	data_avalaible => data_available(15),
6201	rd_out_en => data_out_en(15)
6202	);
6203
6204	end generate port_out_switch15x15;
6205
6206
6207	-- switch 16 ports
6208	port_out_switch16x16 : if n_ports = 16 generate
6209	port_out_switch_16x16:for i in 1 to n_ports generate
6210	begin
6211	PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6212	PORT MAP(
6213	data_in => crossbar_out_port(i),
6214	reset => reset,
6215	clk => clk,
6216	wr_en =>crossbar_out_pulse(i),
6217	data_out =>Port_out(i),
6218	fifo_full =>fifo_out_full_signal(i),
6219	data_avalaible => data_available(i),
6220	rd_out_en => data_out_en(i)
6221	);
6222	end generate port_out_switch_16x16;
6223
6224	end generate port_out_switch16x16;
6225
6226	-- intstanciation et connexion des crossbars du switch en fonction du nombre de ports
6227	-- le circuit genere depend du parametre generique nombre de ports
6228	-- switch 2 ports
6229	crossbar_switch2x2 : if n_ports = 2 generate
6230
6231	Switch_Crossbar2_2: Crossbar
6232	GENERIC MAP(number_of_crossbar_ports =>2)
6233	PORT MAP(
6234	reset => reset,
6235	clk => clk,
6236	Port1_in => crossbar_in_port(1),
6237	Port2_in => crossbar_in_port(2),
6238	Port3_in => "00000000",
6239	Port4_in => "00000000",
6240	Port5_in => "00000000",
6241	Port6_in => "00000000",
6242	Port7_in => "00000000",
6243	Port8_in => "00000000",
6244	Port9_in => "00000000",
6245	Port10_in => "00000000",
6246	Port11_in => "00000000",
6247	Port12_in => "00000000",
6248	Port13_in => "00000000",
6249	Port14_in => "00000000",
6250	Port15_in => "00000000",
6251	Port16_in => "00000000",
6252	Port1_pulse_in => crossbar_in_pulse(1),
6253	Port2_pulse_in => crossbar_in_pulse(2),
6254	Port3_pulse_in =>'0' ,
6255	Port4_pulse_in =>'0' ,
6256	Port5_pulse_in =>'0' ,
6257	Port6_pulse_in =>'0' ,
6258	Port7_pulse_in =>'0' ,
6259	Port8_pulse_in =>'0' ,
6260	Port9_pulse_in =>'0' ,
6261	Port10_pulse_in =>'0' ,
6262	Port11_pulse_in =>'0' ,
6263	Port12_pulse_in =>'0' ,
6264	Port13_pulse_in =>'0' ,
6265	Port14_pulse_in =>'0' ,
6266	Port15_pulse_in =>'0' ,
6267	Port16_pulse_in =>'0' ,
6268	Port1_pulse_out => crossbar_out_pulse(1),
6269	Port2_pulse_out => crossbar_out_pulse(2),
6270	Port1_out => crossbar_out_port(1),
6271	Port2_out => crossbar_out_port(2),
6272	Ctrl => Grant_signal);
6273	end generate crossbar_switch2x2;
6274
6275
6276	-- switch 3 ports
6277	crossbar_switch3x3 : if n_ports = 3 generate
6278
6279	Switch_Crossbar3_3: Crossbar
6280	GENERIC MAP(number_of_crossbar_ports =>3)
6281	PORT MAP(
6282	reset => reset,
6283	clk => clk,
6284	Port1_in => crossbar_in_port(1),
6285	Port2_in => crossbar_in_port(2),
6286	Port3_in => crossbar_in_port(3),
6287	Port4_in => "00000000",
6288	Port5_in => "00000000",
6289	Port6_in => "00000000",
6290	Port7_in => "00000000",
6291	Port8_in => "00000000",
6292	Port9_in => "00000000",
6293	Port10_in => "00000000",
6294	Port11_in => "00000000",
6295	Port12_in => "00000000",
6296	Port13_in => "00000000",
6297	Port14_in => "00000000",
6298	Port15_in => "00000000",
6299	Port16_in => "00000000",
6300	Port1_pulse_in => crossbar_in_pulse(1),
6301	Port2_pulse_in => crossbar_in_pulse(2),
6302	Port3_pulse_in => crossbar_in_pulse(3),
6303	Port4_pulse_in =>'0' ,
6304	Port5_pulse_in =>'0' ,
6305	Port6_pulse_in =>'0' ,
6306	Port7_pulse_in =>'0' ,
6307	Port8_pulse_in =>'0' ,
6308	Port9_pulse_in =>'0' ,
6309	Port10_pulse_in =>'0' ,
6310	Port11_pulse_in =>'0' ,
6311	Port12_pulse_in =>'0' ,
6312	Port13_pulse_in =>'0' ,
6313	Port14_pulse_in =>'0' ,
6314	Port15_pulse_in =>'0' ,
6315	Port16_pulse_in =>'0' ,
6316	Port1_pulse_out => crossbar_out_pulse(1),
6317	Port2_pulse_out => crossbar_out_pulse(2),
6318	Port3_pulse_out => crossbar_out_pulse(3),
6319	Port1_out => crossbar_out_port(1),
6320	Port2_out => crossbar_out_port(2),
6321	Port3_out => crossbar_out_port(3),
6322	Ctrl => Grant_signal);
6323	end generate crossbar_switch3x3;
6324
6325
6326	-- switch 4 ports
6327	crossbar_switch4x4 : if n_ports = 4 generate
6328
6329	Switch_Crossbar4_4: Crossbar
6330	GENERIC MAP(number_of_crossbar_ports =>4)
6331	PORT MAP(
6332	reset => reset,
6333	clk => clk,
6334	Port1_in => crossbar_in_port(1),
6335	Port2_in => crossbar_in_port(2),
6336	Port3_in => crossbar_in_port(3),
6337	Port4_in => crossbar_in_port(4),
6338	Port5_in => "00000000",
6339	Port6_in => "00000000",
6340	Port7_in => "00000000",
6341	Port8_in => "00000000",
6342	Port9_in => "00000000",
6343	Port10_in => "00000000",
6344	Port11_in => "00000000",
6345	Port12_in => "00000000",
6346	Port13_in => "00000000",
6347	Port14_in => "00000000",
6348	Port15_in => "00000000",
6349	Port16_in => "00000000",
6350	Port1_pulse_in => crossbar_in_pulse(1),
6351	Port2_pulse_in => crossbar_in_pulse(2),
6352	Port3_pulse_in => crossbar_in_pulse(3),
6353	Port4_pulse_in => crossbar_in_pulse(4),
6354	Port5_pulse_in =>'0' ,
6355	Port6_pulse_in =>'0' ,
6356	Port7_pulse_in =>'0' ,
6357	Port8_pulse_in =>'0' ,
6358	Port9_pulse_in =>'0' ,
6359	Port10_pulse_in =>'0' ,
6360	Port11_pulse_in =>'0' ,
6361	Port12_pulse_in =>'0' ,
6362	Port13_pulse_in =>'0' ,
6363	Port14_pulse_in =>'0' ,
6364	Port15_pulse_in =>'0' ,
6365	Port16_pulse_in =>'0' ,
6366	Port1_pulse_out => crossbar_out_pulse(1),
6367	Port2_pulse_out => crossbar_out_pulse(2),
6368	Port3_pulse_out => crossbar_out_pulse(3),
6369	Port4_pulse_out => crossbar_out_pulse(4),
6370	Port1_out => crossbar_out_port(1),
6371	Port2_out => crossbar_out_port(2),
6372	Port3_out => crossbar_out_port(3),
6373	Port4_out => crossbar_out_port(4),
6374	Ctrl => Grant_signal);
6375	end generate crossbar_switch4x4;
6376
6377
6378	-- switch 5 ports
6379	crossbar_switch5x5 : if n_ports = 5 generate
6380
6381	Switch_Crossbar5_5: Crossbar
6382	GENERIC MAP(number_of_crossbar_ports =>5)
6383	PORT MAP(
6384	reset => reset,
6385	clk => clk,
6386	Port1_in => crossbar_in_port(1),
6387	Port2_in => crossbar_in_port(2),
6388	Port3_in => crossbar_in_port(3),
6389	Port4_in => crossbar_in_port(4),
6390	Port5_in => crossbar_in_port(5),
6391	Port6_in => "00000000",
6392	Port7_in => "00000000",
6393	Port8_in => "00000000",
6394	Port9_in => "00000000",
6395	Port10_in => "00000000",
6396	Port11_in => "00000000",
6397	Port12_in => "00000000",
6398	Port13_in => "00000000",
6399	Port14_in => "00000000",
6400	Port15_in => "00000000",
6401	Port16_in => "00000000",
6402	Port1_pulse_in => crossbar_in_pulse(1),
6403	Port2_pulse_in => crossbar_in_pulse(2),
6404	Port3_pulse_in => crossbar_in_pulse(3),
6405	Port4_pulse_in => crossbar_in_pulse(4),
6406	Port5_pulse_in => crossbar_in_pulse(5),
6407	Port6_pulse_in =>'0' ,
6408	Port7_pulse_in =>'0' ,
6409	Port8_pulse_in =>'0' ,
6410	Port9_pulse_in =>'0' ,
6411	Port10_pulse_in =>'0' ,
6412	Port11_pulse_in =>'0' ,
6413	Port12_pulse_in =>'0' ,
6414	Port13_pulse_in =>'0' ,
6415	Port14_pulse_in =>'0' ,
6416	Port15_pulse_in =>'0' ,
6417	Port16_pulse_in =>'0' ,
6418	Port1_pulse_out => crossbar_out_pulse(1),
6419	Port2_pulse_out => crossbar_out_pulse(2),
6420	Port3_pulse_out => crossbar_out_pulse(3),
6421	Port4_pulse_out => crossbar_out_pulse(4),
6422	Port5_pulse_out => crossbar_out_pulse(5),
6423	Port1_out => crossbar_out_port(1),
6424	Port2_out => crossbar_out_port(2),
6425	Port3_out => crossbar_out_port(3),
6426	Port4_out => crossbar_out_port(4),
6427	Port5_out => crossbar_out_port(5),
6428	Ctrl => Grant_signal);
6429	end generate crossbar_switch5x5;
6430
6431
6432	-- switch 6 ports
6433	crossbar_switch6x6 : if n_ports = 6 generate
6434
6435	Switch_Crossbar6_6: Crossbar
6436	GENERIC MAP(number_of_crossbar_ports =>6)
6437	PORT MAP(
6438
6439	reset => reset,
6440	clk => clk,
6441	Port1_in => crossbar_in_port(1),
6442	Port2_in => crossbar_in_port(2),
6443	Port3_in => crossbar_in_port(3),
6444	Port4_in => crossbar_in_port(4),
6445	Port5_in => crossbar_in_port(5),
6446	Port6_in => crossbar_in_port(6),
6447	Port7_in => "00000000",
6448	Port8_in => "00000000",
6449	Port9_in => "00000000",
6450	Port10_in => "00000000",
6451	Port11_in => "00000000",
6452	Port12_in => "00000000",
6453	Port13_in => "00000000",
6454	Port14_in => "00000000",
6455	Port15_in => "00000000",
6456	Port16_in => "00000000",
6457	Port1_pulse_in => crossbar_in_pulse(1),
6458	Port2_pulse_in => crossbar_in_pulse(2),
6459	Port3_pulse_in => crossbar_in_pulse(3),
6460	Port4_pulse_in => crossbar_in_pulse(4),
6461	Port5_pulse_in => crossbar_in_pulse(5),
6462	Port6_pulse_in => crossbar_in_pulse(6),
6463	Port7_pulse_in =>'0' ,
6464	Port8_pulse_in =>'0' ,
6465	Port9_pulse_in =>'0' ,
6466	Port10_pulse_in =>'0' ,
6467	Port11_pulse_in =>'0' ,
6468	Port12_pulse_in =>'0' ,
6469	Port13_pulse_in =>'0' ,
6470	Port14_pulse_in =>'0' ,
6471	Port15_pulse_in =>'0' ,
6472	Port16_pulse_in =>'0' ,
6473	Port1_pulse_out => crossbar_out_pulse(1),
6474	Port2_pulse_out => crossbar_out_pulse(2),
6475	Port3_pulse_out => crossbar_out_pulse(3),
6476	Port4_pulse_out => crossbar_out_pulse(4),
6477	Port5_pulse_out => crossbar_out_pulse(5),
6478	Port6_pulse_out => crossbar_out_pulse(6),
6479	Port1_out => crossbar_out_port(1),
6480	Port2_out => crossbar_out_port(2),
6481	Port3_out => crossbar_out_port(3),
6482	Port4_out => crossbar_out_port(4),
6483	Port5_out => crossbar_out_port(5),
6484	Port6_out => crossbar_out_port(6),
6485	Ctrl => Grant_signal);
6486	end generate crossbar_switch6x6;
6487
6488
6489	-- switch 7 ports
6490	crossbar_switch7x7 : if n_ports = 7 generate
6491
6492	Switch_Crossbar7_7: Crossbar
6493	GENERIC MAP(number_of_crossbar_ports =>7)
6494	PORT MAP(
6495	reset => reset,
6496	clk => clk,
6497	Port1_in => crossbar_in_port(1),
6498	Port2_in => crossbar_in_port(2),
6499	Port3_in => crossbar_in_port(3),
6500	Port4_in => crossbar_in_port(4),
6501	Port5_in => crossbar_in_port(5),
6502	Port6_in => crossbar_in_port(6),
6503	Port7_in => crossbar_in_port(7),
6504	Port8_in => "00000000",
6505	Port9_in => "00000000",
6506	Port10_in => "00000000",
6507	Port11_in => "00000000",
6508	Port12_in => "00000000",
6509	Port13_in => "00000000",
6510	Port14_in => "00000000",
6511	Port15_in => "00000000",
6512	Port16_in => "00000000",
6513	Port1_pulse_in => crossbar_in_pulse(1),
6514	Port2_pulse_in => crossbar_in_pulse(2),
6515	Port3_pulse_in => crossbar_in_pulse(3),
6516	Port4_pulse_in => crossbar_in_pulse(4),
6517	Port5_pulse_in => crossbar_in_pulse(5),
6518	Port6_pulse_in => crossbar_in_pulse(6),
6519	Port7_pulse_in => crossbar_in_pulse(7),
6520	Port8_pulse_in =>'0' ,
6521	Port9_pulse_in =>'0' ,
6522	Port10_pulse_in =>'0' ,
6523	Port11_pulse_in =>'0' ,
6524	Port12_pulse_in =>'0' ,
6525	Port13_pulse_in =>'0' ,
6526	Port14_pulse_in =>'0' ,
6527	Port15_pulse_in =>'0' ,
6528	Port16_pulse_in =>'0' ,
6529	Port1_pulse_out => crossbar_out_pulse(1),
6530	Port2_pulse_out => crossbar_out_pulse(2),
6531	Port3_pulse_out => crossbar_out_pulse(3),
6532	Port4_pulse_out => crossbar_out_pulse(4),
6533	Port5_pulse_out => crossbar_out_pulse(5),
6534	Port6_pulse_out => crossbar_out_pulse(6),
6535	Port7_pulse_out => crossbar_out_pulse(7),
6536	Port1_out => crossbar_out_port(1),
6537	Port2_out => crossbar_out_port(2),
6538	Port3_out => crossbar_out_port(3),
6539	Port4_out => crossbar_out_port(4),
6540	Port5_out => crossbar_out_port(5),
6541	Port6_out => crossbar_out_port(6),
6542	Port7_out => crossbar_out_port(7),
6543	Ctrl => Grant_signal);
6544	end generate crossbar_switch7x7;
6545
6546
6547	-- switch 8 ports
6548	crossbar_switch8x8 : if n_ports = 8 generate
6549
6550	Switch_Crossbar8_8: Crossbar
6551	GENERIC MAP(number_of_crossbar_ports =>8)
6552	PORT MAP(
6553	reset => reset,
6554	clk =>clk,
6555	Port1_in => crossbar_in_port(1),
6556	Port2_in => crossbar_in_port(2),
6557	Port3_in => crossbar_in_port(3),
6558	Port4_in => crossbar_in_port(4),
6559	Port5_in => crossbar_in_port(5),
6560	Port6_in => crossbar_in_port(6),
6561	Port7_in => crossbar_in_port(7),
6562	Port8_in => crossbar_in_port(8),
6563	Port9_in => "00000000",
6564	Port10_in => "00000000",
6565	Port11_in => "00000000",
6566	Port12_in => "00000000",
6567	Port13_in => "00000000",
6568	Port14_in => "00000000",
6569	Port15_in => "00000000",
6570	Port16_in => "00000000",
6571	Port1_pulse_in => crossbar_in_pulse(1),
6572	Port2_pulse_in => crossbar_in_pulse(2),
6573	Port3_pulse_in => crossbar_in_pulse(3),
6574	Port4_pulse_in => crossbar_in_pulse(4),
6575	Port5_pulse_in => crossbar_in_pulse(5),
6576	Port6_pulse_in => crossbar_in_pulse(6),
6577	Port7_pulse_in => crossbar_in_pulse(7),
6578	Port8_pulse_in => crossbar_in_pulse(8),
6579	Port9_pulse_in =>'0' ,
6580	Port10_pulse_in =>'0' ,
6581	Port11_pulse_in =>'0' ,
6582	Port12_pulse_in =>'0' ,
6583	Port13_pulse_in =>'0' ,
6584	Port14_pulse_in =>'0' ,
6585	Port15_pulse_in =>'0' ,
6586	Port16_pulse_in =>'0' ,
6587	Port1_pulse_out => crossbar_out_pulse(1),
6588	Port2_pulse_out => crossbar_out_pulse(2),
6589	Port3_pulse_out => crossbar_out_pulse(3),
6590	Port4_pulse_out => crossbar_out_pulse(4),
6591	Port5_pulse_out => crossbar_out_pulse(5),
6592	Port6_pulse_out => crossbar_out_pulse(6),
6593	Port7_pulse_out => crossbar_out_pulse(7),
6594	Port8_pulse_out => crossbar_out_pulse(8),
6595	Port1_out => crossbar_out_port(1),
6596	Port2_out => crossbar_out_port(2),
6597	Port3_out => crossbar_out_port(3),
6598	Port4_out => crossbar_out_port(4),
6599	Port5_out => crossbar_out_port(5),
6600	Port6_out => crossbar_out_port(6),
6601	Port7_out => crossbar_out_port(7),
6602	Port8_out => crossbar_out_port(8),
6603	Ctrl => Grant_signal);
6604	end generate crossbar_switch8x8;
6605
6606
6607	-- switch 9 ports
6608	crossbar_switch9x9 : if n_ports = 9 generate
6609
6610	Switch_Crossbar9_9: Crossbar
6611	GENERIC MAP(number_of_crossbar_ports =>9)
6612	PORT MAP(
6613	reset => reset,
6614	clk => clk,
6615	Port1_in => crossbar_in_port(1),
6616	Port2_in => crossbar_in_port(2),
6617	Port3_in => crossbar_in_port(3),
6618	Port4_in => crossbar_in_port(4),
6619	Port5_in => crossbar_in_port(5),
6620	Port6_in => crossbar_in_port(6),
6621	Port7_in => crossbar_in_port(7),
6622	Port8_in => crossbar_in_port(8),
6623	Port9_in => crossbar_in_port(9),
6624	Port10_in => "00000000",
6625	Port11_in => "00000000",
6626	Port12_in => "00000000",
6627	Port13_in => "00000000",
6628	Port14_in => "00000000",
6629	Port15_in => "00000000",
6630	Port16_in => "00000000",
6631	Port1_pulse_in => crossbar_in_pulse(1),
6632	Port2_pulse_in => crossbar_in_pulse(2),
6633	Port3_pulse_in => crossbar_in_pulse(3),
6634	Port4_pulse_in => crossbar_in_pulse(4),
6635	Port5_pulse_in => crossbar_in_pulse(5),
6636	Port6_pulse_in => crossbar_in_pulse(6),
6637	Port7_pulse_in => crossbar_in_pulse(7),
6638	Port8_pulse_in => crossbar_in_pulse(8),
6639	Port9_pulse_in => crossbar_in_pulse(9),
6640	Port10_pulse_in =>'0' ,
6641	Port11_pulse_in =>'0' ,
6642	Port12_pulse_in =>'0' ,
6643	Port13_pulse_in =>'0' ,
6644	Port14_pulse_in =>'0' ,
6645	Port15_pulse_in =>'0' ,
6646	Port16_pulse_in =>'0' ,
6647	Port1_pulse_out => crossbar_out_pulse(1),
6648	Port2_pulse_out => crossbar_out_pulse(2),
6649	Port3_pulse_out => crossbar_out_pulse(3),
6650	Port4_pulse_out => crossbar_out_pulse(4),
6651	Port5_pulse_out => crossbar_out_pulse(5),
6652	Port6_pulse_out => crossbar_out_pulse(6),
6653	Port7_pulse_out => crossbar_out_pulse(7),
6654	Port8_pulse_out => crossbar_out_pulse(8),
6655	Port9_pulse_out => crossbar_out_pulse(9),
6656	Port1_out => crossbar_out_port(1),
6657	Port2_out => crossbar_out_port(2),
6658	Port3_out => crossbar_out_port(3),
6659	Port4_out => crossbar_out_port(4),
6660	Port5_out => crossbar_out_port(5),
6661	Port6_out => crossbar_out_port(6),
6662	Port7_out => crossbar_out_port(7),
6663	Port8_out => crossbar_out_port(8),
6664	Port9_out => crossbar_out_port(9),
6665	Ctrl => Grant_signal);
6666	end generate crossbar_switch9x9;
6667
6668
6669	-- switch 10 ports
6670	crossbar_switch10x10 : if n_ports = 10 generate
6671
6672	Switch_Crossbar10_10: Crossbar
6673	GENERIC MAP(number_of_crossbar_ports =>10)
6674	PORT MAP(
6675	reset => reset,
6676	clk => clk,
6677	Port1_in => crossbar_in_port(1),
6678	Port2_in => crossbar_in_port(2),
6679	Port3_in => crossbar_in_port(3),
6680	Port4_in => crossbar_in_port(4),
6681	Port5_in => crossbar_in_port(5),
6682	Port6_in => crossbar_in_port(6),
6683	Port7_in => crossbar_in_port(7),
6684	Port8_in => crossbar_in_port(8),
6685	Port9_in => crossbar_in_port(9),
6686	Port10_in => crossbar_in_port(10),
6687	Port11_in => "00000000",
6688	Port12_in => "00000000",
6689	Port13_in => "00000000",
6690	Port14_in => "00000000",
6691	Port15_in => "00000000",
6692	Port16_in => "00000000",
6693	Port1_pulse_in => crossbar_in_pulse(1),
6694	Port2_pulse_in => crossbar_in_pulse(2),
6695	Port3_pulse_in => crossbar_in_pulse(3),
6696	Port4_pulse_in => crossbar_in_pulse(4),
6697	Port5_pulse_in => crossbar_in_pulse(5),
6698	Port6_pulse_in => crossbar_in_pulse(6),
6699	Port7_pulse_in => crossbar_in_pulse(7),
6700	Port8_pulse_in => crossbar_in_pulse(8),
6701	Port9_pulse_in => crossbar_in_pulse(9),
6702	Port10_pulse_in => crossbar_in_pulse(10),
6703	Port11_pulse_in =>'0' ,
6704	Port12_pulse_in =>'0' ,
6705	Port13_pulse_in =>'0' ,
6706	Port14_pulse_in =>'0' ,
6707	Port15_pulse_in =>'0' ,
6708	Port16_pulse_in =>'0' ,
6709	Port1_pulse_out => crossbar_out_pulse(1),
6710	Port2_pulse_out => crossbar_out_pulse(2),
6711	Port3_pulse_out => crossbar_out_pulse(3),
6712	Port4_pulse_out => crossbar_out_pulse(4),
6713	Port5_pulse_out => crossbar_out_pulse(5),
6714	Port6_pulse_out => crossbar_out_pulse(6),
6715	Port7_pulse_out => crossbar_out_pulse(7),
6716	Port8_pulse_out => crossbar_out_pulse(8),
6717	Port9_pulse_out => crossbar_out_pulse(9),
6718	Port10_pulse_out => crossbar_out_pulse(10),
6719	Port1_out => crossbar_out_port(1),
6720	Port2_out => crossbar_out_port(2),
6721	Port3_out => crossbar_out_port(3),
6722	Port4_out => crossbar_out_port(4),
6723	Port5_out => crossbar_out_port(5),
6724	Port6_out => crossbar_out_port(6),
6725	Port7_out => crossbar_out_port(7),
6726	Port8_out => crossbar_out_port(8),
6727	Port9_out => crossbar_out_port(9),
6728	Port10_out => crossbar_out_port(10),
6729	Ctrl => Grant_signal);
6730	end generate crossbar_switch10x10;
6731
6732
6733	-- switch 11 ports
6734	crossbar_switch11x11 : if n_ports = 11 generate
6735
6736	Switch_Crossbar11_11: Crossbar
6737	GENERIC MAP(number_of_crossbar_ports =>11)
6738	PORT MAP(
6739	reset => reset,
6740	clk => clk,
6741	Port1_in => crossbar_in_port(1),
6742	Port2_in => crossbar_in_port(2),
6743	Port3_in => crossbar_in_port(3),
6744	Port4_in => crossbar_in_port(4),
6745	Port5_in => crossbar_in_port(5),
6746	Port6_in => crossbar_in_port(6),
6747	Port7_in => crossbar_in_port(7),
6748	Port8_in => crossbar_in_port(8),
6749	Port9_in => crossbar_in_port(9),
6750	Port10_in => crossbar_in_port(10),
6751	Port11_in => crossbar_in_port(11),
6752	Port12_in => "00000000",
6753	Port13_in => "00000000",
6754	Port14_in => "00000000",
6755	Port15_in => "00000000",
6756	Port16_in => "00000000",
6757	Port1_pulse_in => crossbar_in_pulse(1),
6758	Port2_pulse_in => crossbar_in_pulse(2),
6759	Port3_pulse_in => crossbar_in_pulse(3),
6760	Port4_pulse_in => crossbar_in_pulse(4),
6761	Port5_pulse_in => crossbar_in_pulse(5),
6762	Port6_pulse_in => crossbar_in_pulse(6),
6763	Port7_pulse_in => crossbar_in_pulse(7),
6764	Port8_pulse_in => crossbar_in_pulse(8),
6765	Port9_pulse_in => crossbar_in_pulse(9),
6766	Port10_pulse_in => crossbar_in_pulse(10),
6767	Port11_pulse_in => crossbar_in_pulse(11),
6768	Port12_pulse_in =>'0' ,
6769	Port13_pulse_in =>'0' ,
6770	Port14_pulse_in =>'0' ,
6771	Port15_pulse_in =>'0' ,
6772	Port16_pulse_in =>'0' ,
6773	Port1_pulse_out => crossbar_out_pulse(1),
6774	Port2_pulse_out => crossbar_out_pulse(2),
6775	Port3_pulse_out => crossbar_out_pulse(3),
6776	Port4_pulse_out => crossbar_out_pulse(4),
6777	Port5_pulse_out => crossbar_out_pulse(5),
6778	Port6_pulse_out => crossbar_out_pulse(6),
6779	Port7_pulse_out => crossbar_out_pulse(7),
6780	Port8_pulse_out => crossbar_out_pulse(8),
6781	Port9_pulse_out => crossbar_out_pulse(9),
6782	Port10_pulse_out => crossbar_out_pulse(10),
6783	Port11_pulse_out => crossbar_out_pulse(11),
6784	Port1_out => crossbar_out_port(1),
6785	Port2_out => crossbar_out_port(2),
6786	Port3_out => crossbar_out_port(3),
6787	Port4_out => crossbar_out_port(4),
6788	Port5_out => crossbar_out_port(5),
6789	Port6_out => crossbar_out_port(6),
6790	Port7_out => crossbar_out_port(7),
6791	Port8_out => crossbar_out_port(8),
6792	Port9_out => crossbar_out_port(9),
6793	Port10_out => crossbar_out_port(10),
6794	Port11_out => crossbar_out_port(11),
6795	Ctrl => Grant_signal);
6796	end generate crossbar_switch11x11;
6797
6798
6799	-- switch 12 ports
6800	crossbar_switch12x12 : if n_ports = 12 generate
6801
6802	Switch_Crossbar12_12: Crossbar
6803	GENERIC MAP(number_of_crossbar_ports =>12)
6804	PORT MAP(
6805	reset => reset,
6806	clk => clk,
6807	Port1_in => crossbar_in_port(1),
6808	Port2_in => crossbar_in_port(2),
6809	Port3_in => crossbar_in_port(3),
6810	Port4_in => crossbar_in_port(4),
6811	Port5_in => crossbar_in_port(5),
6812	Port6_in => crossbar_in_port(6),
6813	Port7_in => crossbar_in_port(7),
6814	Port8_in => crossbar_in_port(8),
6815	Port9_in => crossbar_in_port(9),
6816	Port10_in => crossbar_in_port(10),
6817	Port11_in => crossbar_in_port(11),
6818	Port12_in => crossbar_in_port(12),
6819	Port13_in => "00000000",
6820	Port14_in => "00000000",
6821	Port15_in => "00000000",
6822	Port16_in => "00000000",
6823	Port1_pulse_in => crossbar_in_pulse(1),
6824	Port2_pulse_in => crossbar_in_pulse(2),
6825	Port3_pulse_in => crossbar_in_pulse(3),
6826	Port4_pulse_in => crossbar_in_pulse(4),
6827	Port5_pulse_in => crossbar_in_pulse(5),
6828	Port6_pulse_in => crossbar_in_pulse(6),
6829	Port7_pulse_in => crossbar_in_pulse(7),
6830	Port8_pulse_in => crossbar_in_pulse(8),
6831	Port9_pulse_in => crossbar_in_pulse(9),
6832	Port10_pulse_in => crossbar_in_pulse(10),
6833	Port11_pulse_in => crossbar_in_pulse(11),
6834	Port12_pulse_in => crossbar_in_pulse(12),
6835	Port13_pulse_in =>'0' ,
6836	Port14_pulse_in =>'0' ,
6837	Port15_pulse_in =>'0' ,
6838	Port16_pulse_in =>'0' ,
6839	Port1_pulse_out => crossbar_out_pulse(1),
6840	Port2_pulse_out => crossbar_out_pulse(2),
6841	Port3_pulse_out => crossbar_out_pulse(3),
6842	Port4_pulse_out => crossbar_out_pulse(4),
6843	Port5_pulse_out => crossbar_out_pulse(5),
6844	Port6_pulse_out => crossbar_out_pulse(6),
6845	Port7_pulse_out => crossbar_out_pulse(7),
6846	Port8_pulse_out => crossbar_out_pulse(8),
6847	Port9_pulse_out => crossbar_out_pulse(9),
6848	Port10_pulse_out => crossbar_out_pulse(10),
6849	Port11_pulse_out => crossbar_out_pulse(11),
6850	Port12_pulse_out => crossbar_out_pulse(12),
6851	Port1_out => crossbar_out_port(1),
6852	Port2_out => crossbar_out_port(2),
6853	Port3_out => crossbar_out_port(3),
6854	Port4_out => crossbar_out_port(4),
6855	Port5_out => crossbar_out_port(5),
6856	Port6_out => crossbar_out_port(6),
6857	Port7_out => crossbar_out_port(7),
6858	Port8_out => crossbar_out_port(8),
6859	Port9_out => crossbar_out_port(9),
6860	Port10_out => crossbar_out_port(10),
6861	Port11_out => crossbar_out_port(11),
6862	Port12_out => crossbar_out_port(12),
6863	Ctrl => Grant_signal);
6864	end generate crossbar_switch12x12;
6865
6866
6867	-- switch 13 ports
6868	crossbar_switch13x13 : if n_ports = 13 generate
6869
6870	Switch_Crossbar13_13: Crossbar
6871	GENERIC MAP(number_of_crossbar_ports =>13)
6872	PORT MAP(
6873	reset => reset,
6874	clk => clk,
6875	Port1_in => crossbar_in_port(1),
6876	Port2_in => crossbar_in_port(2),
6877	Port3_in => crossbar_in_port(3),
6878	Port4_in => crossbar_in_port(4),
6879	Port5_in => crossbar_in_port(5),
6880	Port6_in => crossbar_in_port(6),
6881	Port7_in => crossbar_in_port(7),
6882	Port8_in => crossbar_in_port(8),
6883	Port9_in => crossbar_in_port(9),
6884	Port10_in => crossbar_in_port(10),
6885	Port11_in => crossbar_in_port(11),
6886	Port12_in => crossbar_in_port(12),
6887	Port13_in => crossbar_in_port(13),
6888	Port14_in => "00000000",
6889	Port15_in => "00000000",
6890	Port16_in => "00000000",
6891	Port1_pulse_in => crossbar_in_pulse(1),
6892	Port2_pulse_in => crossbar_in_pulse(2),
6893	Port3_pulse_in => crossbar_in_pulse(3),
6894	Port4_pulse_in => crossbar_in_pulse(4),
6895	Port5_pulse_in => crossbar_in_pulse(5),
6896	Port6_pulse_in => crossbar_in_pulse(6),
6897	Port7_pulse_in => crossbar_in_pulse(7),
6898	Port8_pulse_in => crossbar_in_pulse(8),
6899	Port9_pulse_in => crossbar_in_pulse(9),
6900	Port10_pulse_in => crossbar_in_pulse(10),
6901	Port11_pulse_in => crossbar_in_pulse(11),
6902	Port12_pulse_in => crossbar_in_pulse(12),
6903	Port13_pulse_in => crossbar_in_pulse(13),
6904	Port14_pulse_in =>'0' ,
6905	Port15_pulse_in =>'0' ,
6906	Port16_pulse_in =>'0' ,
6907	Port1_pulse_out => crossbar_out_pulse(1),
6908	Port2_pulse_out => crossbar_out_pulse(2),
6909	Port3_pulse_out => crossbar_out_pulse(3),
6910	Port4_pulse_out => crossbar_out_pulse(4),
6911	Port5_pulse_out => crossbar_out_pulse(5),
6912	Port6_pulse_out => crossbar_out_pulse(6),
6913	Port7_pulse_out => crossbar_out_pulse(7),
6914	Port8_pulse_out => crossbar_out_pulse(8),
6915	Port9_pulse_out => crossbar_out_pulse(9),
6916	Port10_pulse_out => crossbar_out_pulse(10),
6917	Port11_pulse_out => crossbar_out_pulse(11),
6918	Port12_pulse_out => crossbar_out_pulse(12),
6919	Port13_pulse_out => crossbar_out_pulse(13),
6920	Port1_out => crossbar_out_port(1),
6921	Port2_out => crossbar_out_port(2),
6922	Port3_out => crossbar_out_port(3),
6923	Port4_out => crossbar_out_port(4),
6924	Port5_out => crossbar_out_port(5),
6925	Port6_out => crossbar_out_port(6),
6926	Port7_out => crossbar_out_port(7),
6927	Port8_out => crossbar_out_port(8),
6928	Port9_out => crossbar_out_port(9),
6929	Port10_out => crossbar_out_port(10),
6930	Port11_out => crossbar_out_port(11),
6931	Port12_out => crossbar_out_port(12),
6932	Port13_out => crossbar_out_port(13),
6933	Ctrl => Grant_signal);
6934	end generate crossbar_switch13x13;
6935
6936
6937	-- switch 14 ports
6938	crossbar_switch14x14 : if n_ports = 14 generate
6939
6940	Switch_Crossbar14_14: Crossbar
6941	GENERIC MAP(number_of_crossbar_ports =>14)
6942	PORT MAP(
6943	reset => reset,
6944	clk => clk,
6945	Port1_in => crossbar_in_port(1),
6946	Port2_in => crossbar_in_port(2),
6947	Port3_in => crossbar_in_port(3),
6948	Port4_in => crossbar_in_port(4),
6949	Port5_in => crossbar_in_port(5),
6950	Port6_in => crossbar_in_port(6),
6951	Port7_in => crossbar_in_port(7),
6952	Port8_in => crossbar_in_port(8),
6953	Port9_in => crossbar_in_port(9),
6954	Port10_in => crossbar_in_port(10),
6955	Port11_in => crossbar_in_port(11),
6956	Port12_in => crossbar_in_port(12),
6957	Port13_in => crossbar_in_port(13),
6958	Port14_in => crossbar_in_port(14),
6959	Port15_in => "00000000",
6960	Port16_in => "00000000",
6961	Port1_pulse_in => crossbar_in_pulse(1),
6962	Port2_pulse_in => crossbar_in_pulse(2),
6963	Port3_pulse_in => crossbar_in_pulse(3),
6964	Port4_pulse_in => crossbar_in_pulse(4),
6965	Port5_pulse_in => crossbar_in_pulse(5),
6966	Port6_pulse_in => crossbar_in_pulse(6),
6967	Port7_pulse_in => crossbar_in_pulse(7),
6968	Port8_pulse_in => crossbar_in_pulse(8),
6969	Port9_pulse_in => crossbar_in_pulse(9),
6970	Port10_pulse_in => crossbar_in_pulse(10),
6971	Port11_pulse_in => crossbar_in_pulse(11),
6972	Port12_pulse_in => crossbar_in_pulse(12),
6973	Port13_pulse_in => crossbar_in_pulse(13),
6974	Port14_pulse_in => crossbar_in_pulse(14),
6975	Port15_pulse_in =>'0' ,
6976	Port16_pulse_in =>'0' ,
6977	Port1_pulse_out => crossbar_out_pulse(1),
6978	Port2_pulse_out => crossbar_out_pulse(2),
6979	Port3_pulse_out => crossbar_out_pulse(3),
6980	Port4_pulse_out => crossbar_out_pulse(4),
6981	Port5_pulse_out => crossbar_out_pulse(5),
6982	Port6_pulse_out => crossbar_out_pulse(6),
6983	Port7_pulse_out => crossbar_out_pulse(7),
6984	Port8_pulse_out => crossbar_out_pulse(8),
6985	Port9_pulse_out => crossbar_out_pulse(9),
6986	Port10_pulse_out => crossbar_out_pulse(10),
6987	Port11_pulse_out => crossbar_out_pulse(11),
6988	Port12_pulse_out => crossbar_out_pulse(12),
6989	Port13_pulse_out => crossbar_out_pulse(13),
6990	Port14_pulse_out => crossbar_out_pulse(14),
6991	Port1_out => crossbar_out_port(1),
6992	Port2_out => crossbar_out_port(2),
6993	Port3_out => crossbar_out_port(3),
6994	Port4_out => crossbar_out_port(4),
6995	Port5_out => crossbar_out_port(5),
6996	Port6_out => crossbar_out_port(6),
6997	Port7_out => crossbar_out_port(7),
6998	Port8_out => crossbar_out_port(8),
6999	Port9_out => crossbar_out_port(9),
7000	Port10_out => crossbar_out_port(10),
7001	Port11_out => crossbar_out_port(11),
7002	Port12_out => crossbar_out_port(12),
7003	Port13_out => crossbar_out_port(13),
7004	Port14_out => crossbar_out_port(14),
7005	Ctrl => Grant_signal);
7006	end generate crossbar_switch14x14;
7007
7008
7009	-- switch 15 ports
7010	crossbar_switch15x15 : if n_ports = 15 generate
7011
7012	Switch_Crossbar15_15: Crossbar
7013	GENERIC MAP(number_of_crossbar_ports =>15)
7014	PORT MAP(
7015	reset => reset,
7016	clk => clk,
7017	Port1_in => crossbar_in_port(1),
7018	Port2_in => crossbar_in_port(2),
7019	Port3_in => crossbar_in_port(3),
7020	Port4_in => crossbar_in_port(4),
7021	Port5_in => crossbar_in_port(5),
7022	Port6_in => crossbar_in_port(6),
7023	Port7_in => crossbar_in_port(7),
7024	Port8_in => crossbar_in_port(8),
7025	Port9_in => crossbar_in_port(9),
7026	Port10_in => crossbar_in_port(10),
7027	Port11_in => crossbar_in_port(11),
7028	Port12_in => crossbar_in_port(12),
7029	Port13_in => crossbar_in_port(13),
7030	Port14_in => crossbar_in_port(14),
7031	Port15_in => crossbar_in_port(15),
7032	Port16_in => "00000000",
7033	Port1_pulse_in => crossbar_in_pulse(1),
7034	Port2_pulse_in => crossbar_in_pulse(2),
7035	Port3_pulse_in => crossbar_in_pulse(3),
7036	Port4_pulse_in => crossbar_in_pulse(4),
7037	Port5_pulse_in => crossbar_in_pulse(5),
7038	Port6_pulse_in => crossbar_in_pulse(6),
7039	Port7_pulse_in => crossbar_in_pulse(7),
7040	Port8_pulse_in => crossbar_in_pulse(8),
7041	Port9_pulse_in => crossbar_in_pulse(9),
7042	Port10_pulse_in => crossbar_in_pulse(10),
7043	Port11_pulse_in => crossbar_in_pulse(11),
7044	Port12_pulse_in => crossbar_in_pulse(12),
7045	Port13_pulse_in => crossbar_in_pulse(13),
7046	Port14_pulse_in => crossbar_in_pulse(14),
7047	Port15_pulse_in => crossbar_in_pulse(15),
7048	Port16_pulse_in =>'0' ,
7049	Port1_pulse_out => crossbar_out_pulse(1),
7050	Port2_pulse_out => crossbar_out_pulse(2),
7051	Port3_pulse_out => crossbar_out_pulse(3),
7052	Port4_pulse_out => crossbar_out_pulse(4),
7053	Port5_pulse_out => crossbar_out_pulse(5),
7054	Port6_pulse_out => crossbar_out_pulse(6),
7055	Port7_pulse_out => crossbar_out_pulse(7),
7056	Port8_pulse_out => crossbar_out_pulse(8),
7057	Port9_pulse_out => crossbar_out_pulse(9),
7058	Port10_pulse_out => crossbar_out_pulse(10),
7059	Port11_pulse_out => crossbar_out_pulse(11),
7060	Port12_pulse_out => crossbar_out_pulse(12),
7061	Port13_pulse_out => crossbar_out_pulse(13),
7062	Port14_pulse_out => crossbar_out_pulse(14),
7063	Port15_pulse_out => crossbar_out_pulse(15),
7064	Port1_out => crossbar_out_port(1),
7065	Port2_out => crossbar_out_port(2),
7066	Port3_out => crossbar_out_port(3),
7067	Port4_out => crossbar_out_port(4),
7068	Port5_out => crossbar_out_port(5),
7069	Port6_out => crossbar_out_port(6),
7070	Port7_out => crossbar_out_port(7),
7071	Port8_out => crossbar_out_port(8),
7072	Port9_out => crossbar_out_port(9),
7073	Port10_out => crossbar_out_port(10),
7074	Port11_out => crossbar_out_port(11),
7075	Port12_out => crossbar_out_port(12),
7076	Port13_out => crossbar_out_port(13),
7077	Port14_out => crossbar_out_port(14),
7078	Port15_out => crossbar_out_port(15),
7079	Ctrl => Grant_signal);
7080	end generate crossbar_switch15x15;
7081
7082
7083	-- switch 16 ports
7084	crossbar_switch16x16 : if n_ports = 16 generate
7085
7086	Switch_Crossbar16_16: Crossbar
7087	GENERIC MAP(number_of_crossbar_ports =>16)
7088	PORT MAP(
7089	reset => reset,
7090	clk => clk,
7091	Port1_in => crossbar_in_port(1),
7092	Port2_in => crossbar_in_port(2),
7093	Port3_in => crossbar_in_port(3),
7094	Port4_in => crossbar_in_port(4),
7095	Port5_in => crossbar_in_port(5),
7096	Port6_in => crossbar_in_port(6),
7097	Port7_in => crossbar_in_port(7),
7098	Port8_in => crossbar_in_port(8),
7099	Port9_in => crossbar_in_port(9),
7100	Port10_in => crossbar_in_port(10),
7101	Port11_in => crossbar_in_port(11),
7102	Port12_in => crossbar_in_port(12),
7103	Port13_in => crossbar_in_port(13),
7104	Port14_in => crossbar_in_port(14),
7105	Port15_in => crossbar_in_port(15),
7106	Port16_in => crossbar_in_port(16),
7107	Port1_pulse_in => crossbar_in_pulse(1),
7108	Port2_pulse_in => crossbar_in_pulse(2),
7109	Port3_pulse_in => crossbar_in_pulse(3),
7110	Port4_pulse_in => crossbar_in_pulse(4),
7111	Port5_pulse_in => crossbar_in_pulse(5),
7112	Port6_pulse_in => crossbar_in_pulse(6),
7113	Port7_pulse_in => crossbar_in_pulse(7),
7114	Port8_pulse_in => crossbar_in_pulse(8),
7115	Port9_pulse_in => crossbar_in_pulse(9),
7116	Port10_pulse_in => crossbar_in_pulse(10),
7117	Port11_pulse_in => crossbar_in_pulse(11),
7118	Port12_pulse_in => crossbar_in_pulse(12),
7119	Port13_pulse_in => crossbar_in_pulse(13),
7120	Port14_pulse_in => crossbar_in_pulse(14),
7121	Port15_pulse_in => crossbar_in_pulse(15),
7122	Port16_pulse_in => crossbar_in_pulse(16),
7123	Port1_pulse_out => crossbar_out_pulse(1),
7124	Port2_pulse_out => crossbar_out_pulse(2),
7125	Port3_pulse_out => crossbar_out_pulse(3),
7126	Port4_pulse_out => crossbar_out_pulse(4),
7127	Port5_pulse_out => crossbar_out_pulse(5),
7128	Port6_pulse_out => crossbar_out_pulse(6),
7129	Port7_pulse_out => crossbar_out_pulse(7),
7130	Port8_pulse_out => crossbar_out_pulse(8),
7131	Port9_pulse_out => crossbar_out_pulse(9),
7132	Port10_pulse_out => crossbar_out_pulse(10),
7133	Port11_pulse_out => crossbar_out_pulse(11),
7134	Port12_pulse_out => crossbar_out_pulse(12),
7135	Port13_pulse_out => crossbar_out_pulse(13),
7136	Port14_pulse_out => crossbar_out_pulse(14),
7137	Port15_pulse_out => crossbar_out_pulse(15),
7138	Port16_pulse_out => crossbar_out_pulse(16),
7139	Port1_out => crossbar_out_port(1),
7140	Port2_out => crossbar_out_port(2),
7141	Port3_out => crossbar_out_port(3),
7142	Port4_out => crossbar_out_port(4),
7143	Port5_out => crossbar_out_port(5),
7144	Port6_out => crossbar_out_port(6),
7145	Port7_out => crossbar_out_port(7),
7146	Port8_out => crossbar_out_port(8),
7147	Port9_out => crossbar_out_port(9),
7148	Port10_out => crossbar_out_port(10),
7149	Port11_out => crossbar_out_port(11),
7150	Port12_out => crossbar_out_port(12),
7151	Port13_out => crossbar_out_port(13),
7152	Port14_out => crossbar_out_port(14),
7153	Port15_out => crossbar_out_port(15),
7154	Port16_out => crossbar_out_port(16),
7155	Ctrl => Grant_signal);
7156	end generate crossbar_switch16x16;
7157	-- intstanciation et connexion du scheduler en fonction du nombre de ports
7158	-- le circuit genere depend du parametre generique nombre de ports
7159	-- switch 2 ports
7160	scheduler_switch2x2 : if n_ports = 2 generate
7161
7162	Scheduler2_2: Scheduler
7163	GENERIC MAP(number_of_ports => 2 )
7164	PORT MAP(
7165	Request => Request_signal,
7166	Fifo_full => fifo_out_full_signal,
7167	clk => clk,
7168	priority_rotation =>priority_rotation_signal,
7169	reset => reset,
7170	port_grant => grant_signal
7171	);
7172
7173	end generate scheduler_switch2x2;
7174
7175
7176	-- switch 3 ports
7177	scheduler_switch3x3 : if n_ports = 3 generate
7178
7179	Scheduler3_3: Scheduler
7180	GENERIC MAP(number_of_ports => 3 )
7181	PORT MAP(
7182	Request => Request_signal,
7183	Fifo_full => fifo_out_full_signal,
7184	clk => clk,
7185	priority_rotation =>priority_rotation_signal,
7186	reset => reset,
7187	port_grant => grant_signal
7188	);
7189
7190	end generate scheduler_switch3x3;
7191
7192
7193	-- switch 4 ports
7194	scheduler_switch4x4 : if n_ports = 4 generate
7195
7196	Scheduler4_4: Scheduler
7197	GENERIC MAP(number_of_ports => 4 )
7198	PORT MAP(
7199	Request => Request_signal,
7200	Fifo_full => fifo_out_full_signal,
7201	clk => clk,
7202	priority_rotation =>priority_rotation_signal,
7203	reset => reset,
7204	port_grant => grant_signal
7205	);
7206
7207	end generate scheduler_switch4x4;
7208
7209
7210	-- switch 5 ports
7211	scheduler_switch5x5 : if n_ports = 5 generate
7212
7213	Scheduler5_5: Scheduler
7214	GENERIC MAP(number_of_ports => 5 )
7215	PORT MAP(
7216	Request => Request_signal,
7217	Fifo_full => fifo_out_full_signal,
7218	clk => clk,
7219	priority_rotation =>priority_rotation_signal,
7220	reset => reset,
7221	port_grant => grant_signal
7222	);
7223
7224	end generate scheduler_switch5x5;
7225
7226
7227	-- switch 6 ports
7228	scheduler_switch6x6 : if n_ports = 6 generate
7229
7230	Scheduler6_6: Scheduler
7231	GENERIC MAP(number_of_ports => 6 )
7232	PORT MAP(
7233	Request => Request_signal,
7234	Fifo_full => fifo_out_full_signal,
7235	clk => clk,
7236	priority_rotation =>priority_rotation_signal,
7237	reset => reset,
7238	port_grant => grant_signal
7239	);
7240
7241	end generate scheduler_switch6x6;
7242
7243
7244	-- switch 7 ports
7245	scheduler_switch7x7 : if n_ports = 7 generate
7246
7247	Scheduler7_7: Scheduler
7248	GENERIC MAP(number_of_ports => 7 )
7249	PORT MAP(
7250	Request => Request_signal,
7251	Fifo_full => fifo_out_full_signal,
7252	clk => clk,
7253	priority_rotation =>priority_rotation_signal,
7254	reset => reset,
7255	port_grant => grant_signal
7256	);
7257
7258	end generate scheduler_switch7x7;
7259
7260
7261	-- switch 8 ports
7262	scheduler_switch8x8 : if n_ports = 8 generate
7263
7264	Scheduler8_8: Scheduler
7265	GENERIC MAP(number_of_ports => 8 )
7266	PORT MAP(
7267	Request => Request_signal,
7268	Fifo_full => fifo_out_full_signal,
7269	clk => clk,
7270	priority_rotation =>priority_rotation_signal,
7271	reset => reset,
7272	port_grant => grant_signal
7273	);
7274
7275	end generate scheduler_switch8x8;
7276
7277
7278	-- switch 9 ports
7279	scheduler_switch9x9 : if n_ports = 9 generate
7280
7281	Scheduler9_9: Scheduler
7282	GENERIC MAP(number_of_ports => 9 )
7283	PORT MAP(
7284	Request => Request_signal,
7285	Fifo_full => fifo_out_full_signal,
7286	clk => clk,
7287	priority_rotation =>priority_rotation_signal,
7288	reset => reset,
7289	port_grant => grant_signal
7290	);
7291
7292	end generate scheduler_switch9x9;
7293
7294
7295	-- switch 10 ports
7296	scheduler_switch10x10 : if n_ports = 10 generate
7297
7298	Scheduler10_10: Scheduler
7299	GENERIC MAP(number_of_ports => 10 )
7300	PORT MAP(
7301	Request => Request_signal,
7302	Fifo_full => fifo_out_full_signal,
7303	clk => clk,
7304	priority_rotation =>priority_rotation_signal,
7305	reset => reset,
7306	port_grant => grant_signal
7307	);
7308
7309	end generate scheduler_switch10x10;
7310
7311
7312	-- switch 11 ports
7313	scheduler_switch11x11 : if n_ports = 11 generate
7314
7315	Scheduler11_11: Scheduler
7316	GENERIC MAP(number_of_ports => 11 )
7317	PORT MAP(
7318	Request => Request_signal,
7319	Fifo_full => fifo_out_full_signal,
7320	clk => clk,
7321	priority_rotation =>priority_rotation_signal,
7322	reset => reset,
7323	port_grant => grant_signal
7324	);
7325
7326	end generate scheduler_switch11x11;
7327
7328
7329	-- switch 12 ports
7330	scheduler_switch12x12 : if n_ports = 12 generate
7331
7332	Scheduler12_12: Scheduler
7333	GENERIC MAP(number_of_ports => 12 )
7334	PORT MAP(
7335	Request => Request_signal,
7336	Fifo_full => fifo_out_full_signal,
7337	clk => clk,
7338	priority_rotation =>priority_rotation_signal,
7339	reset => reset,
7340	port_grant => grant_signal
7341	);
7342
7343	end generate scheduler_switch12x12;
7344
7345
7346	-- switch 13 ports
7347	scheduler_switch13x13 : if n_ports = 13 generate
7348
7349	Scheduler13_13: Scheduler
7350	GENERIC MAP(number_of_ports => 13 )
7351	PORT MAP(
7352	Request => Request_signal,
7353	Fifo_full => fifo_out_full_signal,
7354	clk => clk,
7355	priority_rotation =>priority_rotation_signal,
7356	reset => reset,
7357	port_grant => grant_signal
7358	);
7359
7360	end generate scheduler_switch13x13;
7361
7362
7363	-- switch 14 ports
7364	scheduler_switch14x14 : if n_ports = 14 generate
7365
7366	Scheduler14_14: Scheduler
7367	GENERIC MAP(number_of_ports => 14 )
7368	PORT MAP(
7369	Request => Request_signal,
7370	Fifo_full => fifo_out_full_signal,
7371	clk => clk,
7372	priority_rotation =>priority_rotation_signal,
7373	reset => reset,
7374	port_grant => grant_signal
7375	);
7376
7377	end generate scheduler_switch14x14;
7378
7379
7380	-- switch 15 ports
7381	scheduler_switch15x15 : if n_ports = 15 generate
7382
7383	Scheduler15_15: Scheduler
7384	GENERIC MAP(number_of_ports => 15 )
7385	PORT MAP(
7386	Request => Request_signal,
7387	Fifo_full => fifo_out_full_signal,
7388	clk => clk,
7389	priority_rotation =>priority_rotation_signal,
7390	reset => reset,
7391	port_grant => grant_signal
7392	);
7393
7394	end generate scheduler_switch15x15;
7395
7396
7397	-- switch 16 ports
7398	scheduler_switch16x16 : if n_ports = 16 generate
7399
7400	Scheduler16_16: Scheduler
7401	GENERIC MAP(number_of_ports => 16 )
7402	PORT MAP(
7403	Request => Request_signal,
7404	Fifo_full => fifo_out_full_signal,
7405	clk => clk,
7406	priority_rotation =>priority_rotation_signal,
7407	reset => reset,
7408	port_grant => grant_signal
7409	);
7410
7411	end generate scheduler_switch16x16;
7412
7413
7414	end Behavioral;

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SWITCH_GEN.vhd @ 139

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