Ignore:
Timestamp:
May 21, 2014, 11:36:19 AM (10 years ago)
Author:
rolagamo
Message:

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

Location:
PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0
Files:
1 edited
2 copied

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  • PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SWITCH_GEN.vhd

    r101 r139  
    1414-- nécessaire à l'implémentation  du switch de la dimension voulue
    1515-- Dependencies:
    16 --
     16-- Modifié le 28/04/1975
    1717-- Revision:
    1818-- Revision 0.01 - File Created
    … …  
    3232entity SWITCH_GEN is
    3333 --type portio is array(positive range) of std_logic_vector (7 downto 0);   
    34  generic(number_of_ports : positive := 8);
     34 generic(n_ports : positive := 8;-- :nombre de ports E/S du NoC 2 à 16
     35        tot_ports: positive :=16; -- nombre total de ports
     36         NET_ADR :std_logic_vector(9 downto 0):="0000000000";
     37         NET_MASK:natural:=0); -- Nombre de bits à un du masque en partant de la gauche
    3538     port(
    3639                -- ports d'entree
    37            Port_in : in typ_portIO(1 to number_of_ports) ;
     40           Port_in : in typ_portIO(1 to n_ports) ;
    3841
    3942                         
    4043                          -- port de sortie
    41                           Port_out : out  typ_portIO(1 to number_of_ports);
     44                          Port_out : out  typ_portIO(1 to n_ports);
    4245
    4346                          -- signaux de controle
    44                           data_in_en : in std_logic_vector(number_of_ports downto 1);
    45                           cmd_in_en :  in std_logic_vector(number_of_ports downto 1);
    46                           data_out_en : in std_logic_vector(number_of_ports downto 1);
    47                           fifo_in_full : out std_logic_vector(number_of_ports downto 1);
    48                           fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
    49                           data_available : out std_logic_vector(number_of_ports downto 1);
     47                          data_in_en : in std_logic_vector(n_ports downto 1);
     48                          cmd_in_en :  in std_logic_vector(n_ports downto 1);
     49                          data_out_en : in std_logic_vector(n_ports downto 1);
     50                          fifo_in_full : out std_logic_vector(n_ports downto 1);
     51                          fifo_in_empty : out std_logic_vector(n_ports downto 1);
     52                          data_available : out std_logic_vector(n_ports downto 1);
    5053                          clk       : in   STD_LOGIC;
    5154                          reset     : in   STD_LOGIC);
    … …  
    5861COMPONENT INPUT_PORT_MODULE
    5962  generic(number_of_ports : positive := 8;
    60                         Port_num: natural);
    61     Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
     63                        Port_num: natural;
     64                        adr_mask : natural := NET_MASK;--le nombre de '1' en partant le la gauche de l'adresse
     65                        adr_len: positive:=NET_ADR'length; --la taille en bit de l'adresse 10 bits --> 1024 hotes
     66                        tot_ports: positive :=tot_ports; --Nomnre de ports total du réseau
     67                        adr_sub_net : std_logic_vector(9 downto 0) := NET_ADR;--l'adresse du sous-réseau
     68      nbyte : positive:=2 -- le nombre de Byte dans chaque mot du port par défaut 2
     69                       
     70                        );
     71    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
    6272           data_in_en : in  STD_LOGIC;
    6373                          cmd_in_en : in  STD_LOGIC;
    6474           reset : in  STD_LOGIC;
    6575                          clk   : in  STD_LOGIC;
    66                           request : out  STD_LOGIC_VECTOR (number_of_ports downto 1);
    67            grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);                     
     76                          request : out  STD_LOGIC_VECTOR (n_ports downto 1);
     77           grant : in  STD_LOGIC_VECTOR (n_ports  downto 1);                     
    6878           fifo_full : out  STD_LOGIC;
    6979                          fifo_empty : out  STD_LOGIC;
    7080                          priority_rotation : out std_logic;
    71            data_out : out  STD_LOGIC_VECTOR (7 downto 0);
     81           data_out : out  STD_LOGIC_VECTOR (7 downto 0); -- le crossbar est fixé à 8 bits
    7282                          data_out_pulse : out std_logic);
    7383END COMPONENT;
    … …  
    7787COMPONENT OUTPUT_PORT_MODULE
    7888        PORT(
    79                 data_in : IN std_logic_vector(7 downto 0);
     89                data_in : IN std_logic_vector(7 downto 0); -- le crossbar est fixé à 8 bits
    8090                reset : IN std_logic;
    8191                clk : IN std_logic;
    8292                wr_en : IN std_logic;
    8393                rd_out_en : IN std_logic;         
    84                 data_out : OUT std_logic_vector(7 downto 0);
     94                data_out : OUT std_logic_vector(Word-1 downto 0);
    8595                fifo_full : OUT std_logic;
    8696                data_avalaible : OUT std_logic
    … …  
    185195--declaration des signaux de connection entre les modules du switch
    186196
    187 Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
    188 Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
    189 Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
    190 signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
    191 
    192 signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
    193 
    194 
    195 
    196 signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
    197 
    198 
    199 signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
    200 
    201 
    202 signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
     197Signal Request_signal : STD_LOGIC_VECTOR(n_ports*n_ports downto 1);
     198Signal grant_signal : STD_LOGIC_VECTOR(n_ports*n_ports downto 1);
     199Signal priority_rotation_signal : STD_LOGIC_VECTOR(n_ports downto 1);
     200signal fifo_out_full_signal : std_logic_vector(n_ports downto 1);
     201
     202signal crossbar_in_port :  Typ_PortIO8(1 to n_ports);
     203
     204
     205
     206signal crossbar_out_port  :  Typ_PortIO8(1 to n_ports);
     207
     208
     209signal crossbar_in_pulse  : std_logic_vector(n_ports downto 1);
     210
     211
     212signal crossbar_out_pulse  : std_logic_vector(n_ports downto 1);
    203213
    204214
    … …  
    208218-- le circuit genere depend du parametre generique nombre de ports
    209219-- switch 2 ports
    210 switch2x2 : if number_of_ports = 2 generate
     220switch2x2 : if n_ports = 2 generate
    211221
    212222PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    213 GENERIC MAP(number_of_ports =>2,Port_num=>1)
     223GENERIC MAP(number_of_ports =>2,Port_num=>1,
     224adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     225                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     226                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     227                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     228      nbyte =>WORD/8)
    214229PORT MAP(
    215230   data_in => Port_in(1),
    … …  
    230245
    231246PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    232 GENERIC MAP(number_of_ports =>2,Port_num=>2)
     247GENERIC MAP(number_of_ports =>2,Port_num=>2,
     248adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     249                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     250                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     251                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     252      nbyte =>WORD/8)
    233253PORT MAP(
    234254   data_in => Port_in(2),
    … …  
    252272
    253273-- switch 3 ports
    254 switch3x3 : if number_of_ports = 3 generate
     274switch3x3 : if n_ports = 3 generate
    255275
    256276PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    257 GENERIC MAP(number_of_ports =>3,Port_num=>1)
     277GENERIC MAP(number_of_ports =>3,Port_num=>1,
     278adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     279                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     280                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     281                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     282      nbyte =>WORD/8)
    258283PORT MAP(
    259284   data_in => Port_in(1),
    … …  
    276301
    277302PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    278 GENERIC MAP(number_of_ports =>3,Port_num=>2)
     303GENERIC MAP(number_of_ports =>3,Port_num=>2,
     304adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     305                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     306                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     307                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     308      nbyte =>WORD/8)
    279309PORT MAP(
    280310   data_in => Port_in(2),
    … …  
    283313   reset => reset,
    284314   clk =>clk,
    285    grant(4) => grant_signal(4),
    286    grant(5) => grant_signal(5),
    287    grant(6) => grant_signal(6),
     315   grant(1) => grant_signal(4),
     316   grant(2) => grant_signal(5),
     317   grant(3) => grant_signal(6),
    288318   fifo_full =>fifo_in_full(2),
    289319   priority_rotation =>  priority_rotation_signal(2),
    … …  
    291321   data_out =>crossbar_in_port(2),
    292322   data_out_pulse =>crossbar_in_pulse(2),
    293    request(4) =>request_signal(4),
    294    request(5) =>request_signal(5),
    295    request(6) =>request_signal(6)
     323   request(1) =>request_signal(4),
     324   request(2) =>request_signal(5),
     325   request(3) =>request_signal(6)
    296326);
    297327
    298328PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    299 GENERIC MAP(number_of_ports =>3,Port_num=>3)
     329GENERIC MAP(number_of_ports =>3,Port_num=>3,
     330adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     331                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     332                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     333                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     334      nbyte =>WORD/8)
    300335PORT MAP(
    301336   data_in => Port_in(3),
    … …  
    304339   reset => reset,
    305340   clk =>clk,
    306    grant(7) => grant_signal(7),
    307    grant(8) => grant_signal(8),
    308    grant(9) => grant_signal(9),
     341   grant(1) => grant_signal(7),
     342   grant(2) => grant_signal(8),
     343   grant(3) => grant_signal(9),
    309344   fifo_full =>fifo_in_full(3),
    310345   priority_rotation =>  priority_rotation_signal(3),
    … …  
    312347   data_out =>crossbar_in_port(3),
    313348   data_out_pulse =>crossbar_in_pulse(3),
    314    request(7) =>request_signal(7),
    315    request(8) =>request_signal(8),
    316    request(9) =>request_signal(9)
     349   request(1) =>request_signal(7),
     350   request(2) =>request_signal(8),
     351   request(3) =>request_signal(9)
    317352);
    318353
    … …  
    321356
    322357-- switch 4 à 7 ports
    323 switch4x4_7x7 : if number_of_ports >= 4 and number_of_ports <=7 generate
    324 
    325 switch_4x4_7x7:for i in 1 to number_of_ports generate
    326 
    327 constant j: natural:=number_of_ports*(i-1);
     358switch4x4_7x7 : if n_ports >= 4 and n_ports <=7 generate
     359
     360switch_4x4_7x7:for i in 1 to n_ports generate
     361
     362constant j: natural:=n_ports*(i-1);
    328363begin
    329 --j=number_of_ports*(i-1);
     364--j=n_ports*(i-1);
    330365PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    331 GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i)
     366GENERIC MAP(number_of_ports =>n_ports,Port_num=>i,
     367adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     368                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     369                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     370                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     371      nbyte =>WORD/8)
    332372PORT MAP(
    333373   data_in => Port_in(i),
    … …  
    336376   reset => reset,
    337377   clk =>clk,
    338         grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
     378        grant =>grant_signal(j+n_ports downto j+1),
    339379 
    340380   fifo_full =>fifo_in_full(i),
    … …  
    343383   data_out =>crossbar_in_port(i),
    344384   data_out_pulse =>crossbar_in_pulse(i),
    345         request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
     385        request =>request_signal(j+n_ports downto j+1)
    346386   
    347387);
    … …  
    351391
    352392---- switch 5 ports
    353 --switch5x5 : if number_of_ports = 5 generate
     393--switch5x5 : if n_ports = 5 generate
    354394--
    355395--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    356 --GENERIC MAP(number_of_ports =>5)
     396--GENERIC MAP(n_ports =>5)
    357397--PORT MAP(
    358398--   data_in => Port_in(1),
    … …  
    378418--
    379419--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    380 --GENERIC MAP(number_of_ports =>5)
     420--GENERIC MAP(n_ports =>5)
    381421--PORT MAP(
    382422--   data_in => Port_in(2),
    … …  
    402442--
    403443--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    404 --GENERIC MAP(number_of_ports =>5)
     444--GENERIC MAP(n_ports =>5)
    405445--PORT MAP(
    406446--   data_in => Port_in(3),
    … …  
    426466--
    427467--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    428 --GENERIC MAP(number_of_ports =>5)
     468--GENERIC MAP(n_ports =>5)
    429469--PORT MAP(
    430470--   data_in => Port_in(4),
    … …  
    450490--
    451491--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    452 --GENERIC MAP(number_of_ports =>5)
     492--GENERIC MAP(n_ports =>5)
    453493--PORT MAP(
    454494--   data_in => Port_in(5),
    … …  
    477517--
    478518---- switch 6 ports
    479 --switch6x6 : if number_of_ports = 6 generate
     519--switch6x6 : if n_ports = 6 generate
    480520--
    481521--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    482 --GENERIC MAP(number_of_ports =>6)
     522--GENERIC MAP(n_ports =>6)
    483523--PORT MAP(
    484524--   data_in => Port_in(1),
    … …  
    845885
    846886-- switch 8 ports
    847 switch8x8 : if number_of_ports = 8 generate
    848 switch_8x8:for i in 1 to number_of_ports generate
    849 constant j: natural:=number_of_ports*(i-1);
     887switch8x8 : if n_ports = 8 generate
     888switch_8x8:for i in 1 to n_ports generate
     889constant j: natural:=n_ports*(i-1);
    850890begin
    851891--j<=number_of_ports*(i-1);
    852892PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    853 GENERIC MAP(number_of_ports =>8,Port_num=>i)
     893GENERIC MAP(number_of_ports =>8,Port_num=>i,
     894adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     895                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     896                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     897                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     898      nbyte =>WORD/8)
    854899PORT MAP(
    855900   data_in => Port_in(i),
    … …  
    858903   reset => reset,
    859904   clk =>clk,
    860         grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
     905        grant =>grant_signal(j+n_ports downto j+1),
    861906   fifo_full =>fifo_in_full(i),
    862907   priority_rotation =>  priority_rotation_signal(i),
    … …  
    865910   data_out_pulse =>crossbar_in_pulse(i),
    866911
    867         request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
     912        request =>request_signal(j+n_ports downto j+1)
    868913);
    869914end generate switch_8x8;
    … …  
    871916
    872917-- switch 9 ports
    873 switch9x9_to_15 : if (number_of_ports >= 9)and (number_of_ports <= 15) generate
    874 
    875 switch_9x9_to_15:for i in 1 to number_of_ports generate
    876 
    877 constant j: natural:=number_of_ports*(i-1);
     918switch9x9_to_15 : if (n_ports >= 9)and (n_ports <= 15) generate
     919
     920switch_9x9_to_15:for i in 1 to n_ports generate
     921
     922constant j: natural:=n_ports*(i-1);
    878923begin
    879924
    880925PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
    881 GENERIC MAP(number_of_ports =>NUMBER_OF_PORTS,Port_num=>i)
     926GENERIC MAP(number_of_ports =>n_ports,Port_num=>i,
     927adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
     928                        adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
     929                        tot_ports=>tot_ports, --Nomnre de ports total du réseau
     930                        adr_sub_net => NET_ADR,--l'adresse du sous-réseau
     931      nbyte =>WORD/8)
    882932PORT MAP(
    883933   data_in => Port_in(i),
    … …  
    886936   reset => reset,
    887937   clk =>clk,
    888    grant => grant_signal(j+NUMBER_OF_PORTS downto j+1),
     938   grant => grant_signal(j+n_ports downto j+1),
    889939   fifo_full =>fifo_in_full(i),
    890940   priority_rotation =>  priority_rotation_signal(i),
    … …  
    893943   data_out_pulse =>crossbar_in_pulse(i),
    894944
    895         request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
     945        request =>request_signal(j+n_ports downto j+1)
    896946);
    897947end generate switch_9x9_to_15;
    … …  
    38973947
    38983948-- switch 16 ports
    3899 switch16x16 : if number_of_ports = 16 generate
    3900 switch_16x16 :for i in 1 to number_of_ports generate
    3901 Constant j : natural:=number_of_ports*(i-1);
     3949switch16x16 : if n_ports = 16 generate
     3950switch_16x16 :for i in 1 to n_ports generate
     3951Constant j : natural:=n_ports*(i-1);
    39023952begin
    39033953--j<=number_of_ports*(i-1);
    … …  
    46444694-- le circuit genere depend du parametre generique nombre de ports
    46454695-- switch 2 ports
    4646 port_out_switch2x2 : if number_of_ports = 2 generate
     4696port_out_switch2x2 : if n_ports = 2 generate
    46474697
    46484698PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    46744724
    46754725-- switch 3 ports
    4676 port_out_switch3x3 : if number_of_ports = 3 generate
     4726port_out_switch3x3 : if n_ports = 3 generate
    46774727
    46784728PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    47164766
    47174767-- switch 4 ports
    4718 port_out_switch4x4 : if number_of_ports = 4 generate
     4768port_out_switch4x4 : if n_ports = 4 generate
    47194769
    47204770PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    47704820
    47714821-- switch 5 ports
    4772 port_out_switch5x5 : if number_of_ports = 5 generate
     4822port_out_switch5x5 : if n_ports = 5 generate
    47734823
    47744824PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    48364886
    48374887-- switch 6 ports
    4838 port_out_switch6x6 : if number_of_ports = 6 generate
     4888port_out_switch6x6 : if n_ports = 6 generate
    48394889
    48404890PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    49144964
    49154965-- switch 7 ports
    4916 port_out_switch7x7 : if number_of_ports = 7 generate
     4966port_out_switch7x7 : if n_ports = 7 generate
    49174967
    49184968PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    50045054
    50055055-- switch 8 ports
    5006 port_out_switch8x8 : if number_of_ports = 8 generate
     5056port_out_switch8x8 : if n_ports = 8 generate
    50075057
    50085058PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    51065156
    51075157-- switch 9 ports
    5108 port_out_switch9x9 : if number_of_ports = 9 generate
     5158port_out_switch9x9 : if n_ports = 9 generate
    51095159
    51105160PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    52205270
    52215271-- switch 10 ports
    5222 port_out_switch10x10 : if number_of_ports = 10 generate
     5272port_out_switch10x10 : if n_ports = 10 generate
    52235273
    52245274PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    53465396
    53475397-- switch 11 ports
    5348 port_out_switch11x11 : if number_of_ports = 11 generate
     5398port_out_switch11x11 : if n_ports = 11 generate
    53495399
    53505400PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    54845534
    54855535-- switch 12 ports
    5486 port_out_switch12x12 : if number_of_ports = 12 generate
     5536port_out_switch12x12 : if n_ports = 12 generate
    54875537
    54885538PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    56345684
    56355685-- switch 13 ports
    5636 port_out_switch13x13 : if number_of_ports = 13 generate
     5686port_out_switch13x13 : if n_ports = 13 generate
    56375687
    56385688PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    57965846
    57975847-- switch 14 ports
    5798 port_out_switch14x14 : if number_of_ports = 14 generate
     5848port_out_switch14x14 : if n_ports = 14 generate
    57995849
    58005850PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    59706020
    59716021-- switch 15 ports
    5972 port_out_switch15x15 : if number_of_ports = 15 generate
     6022port_out_switch15x15 : if n_ports = 15 generate
    59736023
    59746024PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    61566206
    61576207-- switch 16 ports
    6158 port_out_switch16x16 : if number_of_ports = 16 generate
    6159 port_out_switch_16x16:for i in 1 to number_of_ports generate
     6208port_out_switch16x16 : if n_ports = 16 generate
     6209port_out_switch_16x16:for i in 1 to n_ports generate
    61606210  begin
    61616211  PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
    … …  
    61776227-- le circuit genere depend du parametre generique nombre de ports
    61786228-- switch 2 ports
    6179 crossbar_switch2x2 : if number_of_ports = 2 generate
     6229crossbar_switch2x2 : if n_ports = 2 generate
    61806230
    61816231Switch_Crossbar2_2: Crossbar
    … …  
    62256275
    62266276-- switch 3 ports
    6227 crossbar_switch3x3 : if number_of_ports = 3 generate
     6277crossbar_switch3x3 : if n_ports = 3 generate
    62286278
    62296279Switch_Crossbar3_3: Crossbar
    … …  
    62756325
    62766326-- switch 4 ports
    6277 crossbar_switch4x4 : if number_of_ports = 4 generate
     6327crossbar_switch4x4 : if n_ports = 4 generate
    62786328
    62796329Switch_Crossbar4_4: Crossbar
    … …  
    63276377
    63286378-- switch 5 ports
    6329 crossbar_switch5x5 : if number_of_ports = 5 generate
     6379crossbar_switch5x5 : if n_ports = 5 generate
    63306380
    63316381Switch_Crossbar5_5: Crossbar
    … …  
    63816431
    63826432-- switch 6 ports
    6383 crossbar_switch6x6 : if number_of_ports = 6 generate
     6433crossbar_switch6x6 : if n_ports = 6 generate
    63846434
    63856435Switch_Crossbar6_6: Crossbar
    … …  
    64386488
    64396489-- switch 7 ports
    6440 crossbar_switch7x7 : if number_of_ports = 7 generate
     6490crossbar_switch7x7 : if n_ports = 7 generate
    64416491
    64426492Switch_Crossbar7_7: Crossbar
    … …  
    64966546
    64976547-- switch 8 ports
    6498 crossbar_switch8x8 : if number_of_ports = 8 generate
     6548crossbar_switch8x8 : if n_ports = 8 generate
    64996549
    65006550Switch_Crossbar8_8: Crossbar
    … …  
    65566606
    65576607-- switch 9 ports
    6558 crossbar_switch9x9 : if number_of_ports = 9 generate
     6608crossbar_switch9x9 : if n_ports = 9 generate
    65596609
    65606610Switch_Crossbar9_9: Crossbar
    … …  
    66186668
    66196669-- switch 10 ports
    6620 crossbar_switch10x10 : if number_of_ports = 10 generate
     6670crossbar_switch10x10 : if n_ports = 10 generate
    66216671
    66226672Switch_Crossbar10_10: Crossbar
    … …  
    66826732
    66836733-- switch 11 ports
    6684 crossbar_switch11x11 : if number_of_ports = 11 generate
     6734crossbar_switch11x11 : if n_ports = 11 generate
    66856735
    66866736Switch_Crossbar11_11: Crossbar
    … …  
    67486798
    67496799-- switch 12 ports
    6750 crossbar_switch12x12 : if number_of_ports = 12 generate
     6800crossbar_switch12x12 : if n_ports = 12 generate
    67516801
    67526802Switch_Crossbar12_12: Crossbar
    … …  
    68166866
    68176867-- switch 13 ports
    6818 crossbar_switch13x13 : if number_of_ports = 13 generate
     6868crossbar_switch13x13 : if n_ports = 13 generate
    68196869
    68206870Switch_Crossbar13_13: Crossbar
    … …  
    68866936
    68876937-- switch 14 ports
    6888 crossbar_switch14x14 : if number_of_ports = 14 generate
     6938crossbar_switch14x14 : if n_ports = 14 generate
    68896939
    68906940Switch_Crossbar14_14: Crossbar
    … …  
    69587008
    69597009-- switch 15 ports
    6960 crossbar_switch15x15 : if number_of_ports = 15 generate
     7010crossbar_switch15x15 : if n_ports = 15 generate
    69617011
    69627012Switch_Crossbar15_15: Crossbar
    … …  
    70327082
    70337083-- switch 16 ports
    7034 crossbar_switch16x16 : if number_of_ports = 16 generate
     7084crossbar_switch16x16 : if n_ports = 16 generate
    70357085
    70367086Switch_Crossbar16_16: Crossbar
    … …  
    71087158-- le circuit genere depend du parametre generique nombre de ports
    71097159-- switch 2 ports
    7110 scheduler_switch2x2 : if number_of_ports = 2 generate
     7160scheduler_switch2x2 : if n_ports = 2 generate
    71117161
    71127162Scheduler2_2: Scheduler
    … …  
    71257175
    71267176-- switch 3 ports
    7127 scheduler_switch3x3 : if number_of_ports = 3 generate
     7177scheduler_switch3x3 : if n_ports = 3 generate
    71287178
    71297179Scheduler3_3: Scheduler
    … …  
    71427192
    71437193-- switch 4 ports
    7144 scheduler_switch4x4 : if number_of_ports = 4 generate
     7194scheduler_switch4x4 : if n_ports = 4 generate
    71457195
    71467196Scheduler4_4: Scheduler
    … …  
    71597209
    71607210-- switch 5 ports
    7161 scheduler_switch5x5 : if number_of_ports = 5 generate
     7211scheduler_switch5x5 : if n_ports = 5 generate
    71627212
    71637213Scheduler5_5: Scheduler
    … …  
    71767226
    71777227-- switch 6 ports
    7178 scheduler_switch6x6 : if number_of_ports = 6 generate
     7228scheduler_switch6x6 : if n_ports = 6 generate
    71797229
    71807230Scheduler6_6: Scheduler
    … …  
    71937243
    71947244-- switch 7 ports
    7195 scheduler_switch7x7 : if number_of_ports = 7 generate
     7245scheduler_switch7x7 : if n_ports = 7 generate
    71967246
    71977247Scheduler7_7: Scheduler
    … …  
    72107260
    72117261-- switch 8 ports
    7212 scheduler_switch8x8 : if number_of_ports = 8 generate
     7262scheduler_switch8x8 : if n_ports = 8 generate
    72137263
    72147264Scheduler8_8: Scheduler
    … …  
    72277277
    72287278-- switch 9 ports
    7229 scheduler_switch9x9 : if number_of_ports = 9 generate
     7279scheduler_switch9x9 : if n_ports = 9 generate
    72307280
    72317281Scheduler9_9: Scheduler
    … …  
    72447294
    72457295-- switch 10 ports
    7246 scheduler_switch10x10 : if number_of_ports = 10 generate
     7296scheduler_switch10x10 : if n_ports = 10 generate
    72477297
    72487298Scheduler10_10: Scheduler
    … …  
    72617311
    72627312-- switch 11 ports
    7263 scheduler_switch11x11 : if number_of_ports = 11 generate
     7313scheduler_switch11x11 : if n_ports = 11 generate
    72647314
    72657315Scheduler11_11: Scheduler
    … …  
    72787328
    72797329-- switch 12 ports
    7280 scheduler_switch12x12 : if number_of_ports = 12 generate
     7330scheduler_switch12x12 : if n_ports = 12 generate
    72817331
    72827332Scheduler12_12: Scheduler
    … …  
    72957345
    72967346-- switch 13 ports
    7297 scheduler_switch13x13 : if number_of_ports = 13 generate
     7347scheduler_switch13x13 : if n_ports = 13 generate
    72987348
    72997349Scheduler13_13: Scheduler
    … …  
    73127362
    73137363-- switch 14 ports
    7314 scheduler_switch14x14 : if number_of_ports = 14 generate
     7364scheduler_switch14x14 : if n_ports = 14 generate
    73157365
    73167366Scheduler14_14: Scheduler
    … …  
    73297379
    73307380-- switch 15 ports
    7331 scheduler_switch15x15 : if number_of_ports = 15 generate
     7381scheduler_switch15x15 : if n_ports = 15 generate
    73327382
    73337383Scheduler15_15: Scheduler
    … …  
    73467396
    73477397-- switch 16 ports
    7348 scheduler_switch16x16 : if number_of_ports = 16 generate
     7398scheduler_switch16x16 : if n_ports = 16 generate
    73497399
    73507400Scheduler16_16: Scheduler
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