source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Scheduler.vhd.bak

Last change on this file was 139, checked in by rolagamo, 10 years ago

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
File size: 12.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer: KIEGAING EMMANUEL GEL EN 5
4--
5-- Create Date:    19:56:34 05/06/2011
6-- Design Name:
7-- Module Name:    Sheduler - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Module de l'ordonnanceur du switch crossbar
12-- l'algorithme utilisé est le DPA (diagonal propagation arbiter)
13-- intencie un scheduler particulier en fonction du nombre de port
14-- Dependencies:
15--
16-- Revision: 1.0
17-- reconstruction du dpa
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21----------------------------------------------------------------------------------
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26--use Work.Sheduler_package.all;
27
28---- Uncomment the following library declaration if instantiating
29---- any Xilinx primitives in this code.
30--library UNISIM;
31--use UNISIM.VComponents.all;
32
33entity Scheduler is
34   generic(number_of_ports : positive := 4);
35    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
36                          Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
37           clk : in  STD_LOGIC;
38                reset : in  STD_LOGIC;
39                          priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
40           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
41      end Scheduler;
42               
43architecture Behavioral of Scheduler is
44-- signaux pour le pipeline;
45signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0');
46signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0');
47signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1');
48         
49-- composants du scheduler
50COMPONENT Scheduler2_2
51   PORT(
52      Request : IN std_logic_vector(4 downto 1);
53      Fifo_full : IN std_logic_vector(2 downto 1);
54      clk : IN std_logic;
55      reset : IN std_logic;
56      port_grant : OUT std_logic_vector(4 downto 1);
57      priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1)
58   );
59 END COMPONENT;
60
61COMPONENT Scheduler3_3
62   PORT(
63      Req : IN std_logic_vector(9 downto 1);
64      Fifo_full : IN std_logic_vector(3 downto 1);
65      clk : IN std_logic;
66      reset : IN std_logic;
67      port_grant : OUT std_logic_vector(9 downto 1);
68      priority_rotation : in  STD_LOGIC_VECTOR (3 downto 1)
69   );
70 END COMPONENT;
71
72COMPONENT Scheduler4_4
73   PORT(
74      Req : IN std_logic_vector(16 downto 1);
75      Fifo_full : IN std_logic_vector(4 downto 1);
76      clk : IN std_logic;
77      reset : IN std_logic;
78      port_grant : OUT std_logic_vector(16 downto 1);
79      priority_rotation : in  STD_LOGIC_VECTOR (4 downto 1)
80   );
81 END COMPONENT;
82
83COMPONENT Scheduler5_5
84   PORT(
85      Req : IN std_logic_vector(25 downto 1);
86      Fifo_full : IN std_logic_vector(5 downto 1);
87      clk : IN std_logic;
88      reset : IN std_logic;
89      port_grant : OUT std_logic_vector(25 downto 1);
90      priority_rotation : in  STD_LOGIC_VECTOR (5 downto 1)
91   );
92 END COMPONENT;
93
94COMPONENT Scheduler6_6
95   PORT(
96      Req : IN std_logic_vector(36 downto 1);
97      Fifo_full : IN std_logic_vector(6 downto 1);
98      clk : IN std_logic;
99      reset : IN std_logic;
100      port_grant : OUT std_logic_vector(36 downto 1);
101      priority_rotation : in  STD_LOGIC_VECTOR (6 downto 1)
102   );
103 END COMPONENT;
104
105COMPONENT Scheduler7_7
106   PORT(
107      Req : IN std_logic_vector(49 downto 1);
108      Fifo_full : IN std_logic_vector(7 downto 1);
109      clk : IN std_logic;
110      reset : IN std_logic;
111      port_grant : OUT std_logic_vector(49 downto 1);
112      priority_rotation : in  STD_LOGIC_VECTOR (7 downto 1)
113   );
114 END COMPONENT;
115
116COMPONENT Scheduler8_8
117   PORT(
118      Req : IN std_logic_vector(64 downto 1);
119      Fifo_full : IN std_logic_vector(8 downto 1);
120      clk : IN std_logic;
121      reset : IN std_logic;
122      port_grant : OUT std_logic_vector(64 downto 1);
123      priority_rotation : in  STD_LOGIC_VECTOR (8 downto 1)
124   );
125 END COMPONENT;
126
127COMPONENT Scheduler9_9
128   PORT(
129      Request : IN std_logic_vector(81 downto 1);
130      Fifo_full : IN std_logic_vector(9 downto 1);
131      clk : IN std_logic;
132      reset : IN std_logic;
133      port_grant : OUT std_logic_vector(81 downto 1);
134      priority_rotation : in  STD_LOGIC_VECTOR (9 downto 1)
135   );
136 END COMPONENT;
137
138COMPONENT Scheduler10_10
139   PORT(
140      Request : IN std_logic_vector(100 downto 1);
141      Fifo_full : IN std_logic_vector(10 downto 1);
142      clk : IN std_logic;
143      reset : IN std_logic;
144      port_grant : OUT std_logic_vector(100 downto 1);
145      priority_rotation : in  STD_LOGIC_VECTOR (10 downto 1)
146   );
147 END COMPONENT;
148
149COMPONENT Scheduler11_11
150   PORT(
151      Request : IN std_logic_vector(121 downto 1);
152      Fifo_full : IN std_logic_vector(11 downto 1);
153      clk : IN std_logic;
154      reset : IN std_logic;
155      port_grant : OUT std_logic_vector(121 downto 1);
156      priority_rotation : in  STD_LOGIC_VECTOR (11 downto 1)
157   );
158 END COMPONENT;
159
160COMPONENT Scheduler12_12
161   PORT(
162      Request : IN std_logic_vector(144 downto 1);
163      Fifo_full : IN std_logic_vector(12 downto 1);
164      clk : IN std_logic;
165      reset : IN std_logic;
166      port_grant : OUT std_logic_vector(144 downto 1);
167      priority_rotation : in  STD_LOGIC_VECTOR (12 downto 1)
168   );
169 END COMPONENT;
170
171COMPONENT Scheduler13_13
172   PORT(
173      Request : IN std_logic_vector(169 downto 1);
174      Fifo_full : IN std_logic_vector(13 downto 1);
175      clk : IN std_logic;
176      reset : IN std_logic;
177      port_grant : OUT std_logic_vector(169 downto 1);
178      priority_rotation : in  STD_LOGIC_VECTOR (13 downto 1)
179   );
180 END COMPONENT;
181
182COMPONENT Scheduler14_14
183   PORT(
184      Request : IN std_logic_vector(196 downto 1);
185      Fifo_full : IN std_logic_vector(14 downto 1);
186      clk : IN std_logic;
187      reset : IN std_logic;
188      port_grant : OUT std_logic_vector(196 downto 1);
189      priority_rotation : in  STD_LOGIC_VECTOR (14 downto 1)
190   );
191 END COMPONENT;
192
193COMPONENT Scheduler15_15
194   PORT(
195      Request : IN std_logic_vector(225 downto 1);
196      Fifo_full : IN std_logic_vector(15 downto 1);
197      clk : IN std_logic;
198      reset : IN std_logic;
199      port_grant : OUT std_logic_vector(225 downto 1);
200      priority_rotation : in  STD_LOGIC_VECTOR (15 downto 1)
201   );
202 END COMPONENT;
203
204COMPONENT Scheduler16_16
205   PORT(
206      Request : IN std_logic_vector(256 downto 1);
207      Fifo_full : IN std_logic_vector(16 downto 1);
208      clk : IN std_logic;
209      reset : IN std_logic;
210      port_grant : OUT std_logic_vector(256 downto 1);
211      priority_rotation : in  STD_LOGIC_VECTOR (16 downto 1)
212   );
213 END COMPONENT;
214
215
216-- instanciation des scheduler
217--======================scheduler 2 ports=======================
218
219begin
220
221-- instanciation des scheduler
222--======================scheduler 2 ports=======================
223
224scheduler2x2 : if number_of_ports = 2 generate
225
226  Inst_Scheduler2_2 : Scheduler2_2
227   PORT MAP(
228     Request => Request_latch,
229     Fifo_full => Fifo_full_latch,
230     clk => clk ,
231     reset =>reset,
232     priority_rotation =>priority_rotation_latch,
233     port_grant =>port_grant);
234end generate scheduler2x2;
235
236--======================scheduler 3 ports=======================
237
238scheduler3x3 : if number_of_ports = 3 generate
239
240  Inst_Scheduler3_3 : Scheduler3_3
241   PORT MAP(
242     Req => Request_latch,
243     Fifo_full => Fifo_full_latch,
244     clk => clk ,
245     reset =>reset,
246     priority_rotation =>priority_rotation_latch,
247     port_grant =>port_grant);
248end generate scheduler3x3;
249
250--======================scheduler 4 ports=======================
251
252scheduler4x4 : if number_of_ports = 4 generate
253
254  Inst_Scheduler4_4 : Scheduler4_4
255   PORT MAP(
256     Req => Request_latch,
257     Fifo_full => Fifo_full_latch,
258     clk => clk ,
259     reset =>reset,
260     priority_rotation =>priority_rotation_latch,
261     port_grant =>port_grant);
262end generate scheduler4x4;
263
264--======================scheduler 5 ports=======================
265
266scheduler5x5 : if number_of_ports = 5 generate
267
268  Inst_Scheduler5_5 : Scheduler5_5
269   PORT MAP(
270     Req => Request,
271     Fifo_full => Fifo_full,
272     clk => clk ,
273     reset =>reset,
274     priority_rotation =>priority_rotation,
275     port_grant =>port_grant);
276end generate scheduler5x5;
277
278--======================scheduler 6 ports=======================
279
280scheduler6x6 : if number_of_ports = 6 generate
281
282  Inst_Scheduler6_6 : Scheduler6_6
283   PORT MAP(
284     Req => Request_latch,
285     Fifo_full => Fifo_full_latch,
286     clk => clk ,
287     reset =>reset,
288     priority_rotation =>priority_rotation_latch,
289     port_grant =>port_grant);
290end generate scheduler6x6;
291
292--======================scheduler 7 ports=======================
293
294scheduler7x7 : if number_of_ports = 7 generate
295
296  Inst_Scheduler7_7 : Scheduler7_7
297   PORT MAP(
298     Req => Request_latch,
299     Fifo_full => Fifo_full_latch,
300     clk => clk ,
301     reset =>reset,
302     priority_rotation =>priority_rotation_latch,
303     port_grant =>port_grant);
304end generate scheduler7x7;
305
306--======================scheduler 8 ports=======================
307
308scheduler8x8 : if number_of_ports = 8 generate
309
310  Inst_Scheduler8_8 : Scheduler8_8
311   PORT MAP(
312     Req => Request_latch,
313     Fifo_full => Fifo_full_latch,
314     clk => clk ,
315     reset =>reset,
316     priority_rotation =>priority_rotation_latch,
317     port_grant =>port_grant);
318end generate scheduler8x8;
319
320--======================scheduler 9 ports=======================
321
322scheduler9x9 : if number_of_ports = 9 generate
323
324  Inst_Scheduler9_9 : Scheduler9_9
325   PORT MAP(
326     Request => Request_latch,
327     Fifo_full => Fifo_full_latch,
328     clk => clk ,
329     reset =>reset,
330     priority_rotation =>priority_rotation_latch,
331     port_grant =>port_grant);
332end generate scheduler9x9;
333
334--======================scheduler 10 ports=======================
335
336scheduler10x10 : if number_of_ports = 10 generate
337
338  Inst_Scheduler10_10 : Scheduler10_10
339   PORT MAP(
340     Request => Request,
341     Fifo_full => Fifo_full,
342     clk => clk ,
343     reset =>reset,
344     priority_rotation =>priority_rotation,
345     port_grant =>port_grant);
346end generate scheduler10x10;
347
348--======================scheduler 11 ports=======================
349
350scheduler11x11 : if number_of_ports = 11 generate
351
352  Inst_Scheduler11_11 : Scheduler11_11
353   PORT MAP(
354     Request => Request,
355     Fifo_full => Fifo_full,
356     clk => clk ,
357     reset =>reset,
358     priority_rotation =>priority_rotation,
359     port_grant =>port_grant);
360end generate scheduler11x11;
361
362--======================scheduler 12 ports=======================
363
364scheduler12x12 : if number_of_ports = 12 generate
365
366  Inst_Scheduler12_12 : Scheduler12_12
367   PORT MAP(
368     Request => Request_latch,
369     Fifo_full => Fifo_full_latch,
370     clk => clk ,
371     reset =>reset,
372     priority_rotation =>priority_rotation_latch,
373     port_grant =>port_grant);
374end generate scheduler12x12;
375
376--======================scheduler 13 ports=======================
377
378scheduler13x13 : if number_of_ports = 13 generate
379
380  Inst_Scheduler13_13 : Scheduler13_13
381   PORT MAP(
382     Request => Request_latch,
383     Fifo_full => Fifo_full_latch,
384     clk => clk ,
385     reset =>reset,
386     priority_rotation =>priority_rotation_latch,
387     port_grant =>port_grant);
388end generate scheduler13x13;
389
390--======================scheduler 14 ports=======================
391
392scheduler14x14 : if number_of_ports = 14 generate
393
394  Inst_Scheduler14_14 : Scheduler14_14
395   PORT MAP(
396     Request => Request_latch,
397     Fifo_full => Fifo_full_latch,
398     clk => clk ,
399     reset =>reset,
400     priority_rotation =>priority_rotation_latch,
401     port_grant =>port_grant);
402end generate scheduler14x14;
403
404--======================scheduler 15 ports=======================
405
406scheduler15x15 : if number_of_ports = 15 generate
407
408  Inst_Scheduler15_15 : Scheduler15_15
409   PORT MAP(
410     Request => Request_latch,
411     Fifo_full => Fifo_full_latch,
412     clk => clk ,
413     reset =>reset,
414     priority_rotation =>priority_rotation_latch,
415     port_grant =>port_grant);
416end generate scheduler15x15;
417
418--======================scheduler 16 ports=======================
419
420scheduler16x16 : if number_of_ports = 16 generate
421
422  Inst_Scheduler16_16 : Scheduler16_16
423   PORT MAP(
424     Request => Request_latch,
425     Fifo_full => Fifo_full_latch,
426     clk => clk ,
427     reset =>reset,
428     priority_rotation =>priority_rotation_latch,
429     port_grant =>port_grant);
430end generate scheduler16x16;
431Sched:process (clk,reset)
432begin
433if rising_edge(clk) then
434        if reset='1' then
435                request_latch<=(others=>'0');
436                --Fifo_full_latch<=(others=>'0');
437                priority_rotation_latch<=(others=>'1');
438        else
439                request_latch<=request;
440        --      Fifo_full_latch<=fifo_full;
441                priority_rotation_latch<=priority_rotation;
442        end if;
443end if;
444end process sched;
445Fifo_full_latch<=fifo_full;
446end Behavioral;
447
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