- Timestamp:
- May 21, 2014, 11:36:19 AM (10 years ago)
- Location:
- PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0
- Files:
-
- 1 edited
- 2 copied
Legend:
- Unmodified
- Added
- Removed
-
PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Scheduler.vhd.bak
r101 r139 61 61 COMPONENT Scheduler3_3 62 62 PORT( 63 Req uest: IN std_logic_vector(9 downto 1);63 Req : IN std_logic_vector(9 downto 1); 64 64 Fifo_full : IN std_logic_vector(3 downto 1); 65 65 clk : IN std_logic; … … 72 72 COMPONENT Scheduler4_4 73 73 PORT( 74 Req uest: IN std_logic_vector(16 downto 1);74 Req : IN std_logic_vector(16 downto 1); 75 75 Fifo_full : IN std_logic_vector(4 downto 1); 76 76 clk : IN std_logic; … … 83 83 COMPONENT Scheduler5_5 84 84 PORT( 85 Req uest: IN std_logic_vector(25 downto 1);85 Req : IN std_logic_vector(25 downto 1); 86 86 Fifo_full : IN std_logic_vector(5 downto 1); 87 87 clk : IN std_logic; … … 94 94 COMPONENT Scheduler6_6 95 95 PORT( 96 Req uest: IN std_logic_vector(36 downto 1);96 Req : IN std_logic_vector(36 downto 1); 97 97 Fifo_full : IN std_logic_vector(6 downto 1); 98 98 clk : IN std_logic; … … 105 105 COMPONENT Scheduler7_7 106 106 PORT( 107 Req uest: IN std_logic_vector(49 downto 1);107 Req : IN std_logic_vector(49 downto 1); 108 108 Fifo_full : IN std_logic_vector(7 downto 1); 109 109 clk : IN std_logic; … … 240 240 Inst_Scheduler3_3 : Scheduler3_3 241 241 PORT MAP( 242 Req uest=> Request_latch,242 Req => Request_latch, 243 243 Fifo_full => Fifo_full_latch, 244 244 clk => clk , … … 254 254 Inst_Scheduler4_4 : Scheduler4_4 255 255 PORT MAP( 256 Req uest=> Request_latch,256 Req => Request_latch, 257 257 Fifo_full => Fifo_full_latch, 258 258 clk => clk , … … 268 268 Inst_Scheduler5_5 : Scheduler5_5 269 269 PORT MAP( 270 Req uest=> Request,270 Req => Request, 271 271 Fifo_full => Fifo_full, 272 272 clk => clk , … … 282 282 Inst_Scheduler6_6 : Scheduler6_6 283 283 PORT MAP( 284 Req uest=> Request_latch,284 Req => Request_latch, 285 285 Fifo_full => Fifo_full_latch, 286 286 clk => clk , … … 296 296 Inst_Scheduler7_7 : Scheduler7_7 297 297 PORT MAP( 298 Req uest=> Request_latch,298 Req => Request_latch, 299 299 Fifo_full => Fifo_full_latch, 300 300 clk => clk ,
Note: See TracChangeset
for help on using the changeset viewer.