source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs @ 139

Last change on this file since 139 was 139, checked in by rolagamo, 10 years ago

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
File size: 1.2 KB
Line 
1<?xml version="1.0" encoding="UTF-8"?>
2<!-- IMPORTANT: This is an internal file that has been generated
3     by the Xilinx ISE software.  Any direct editing or
4     changes made to this file may result in unpredictable
5     behavior or data corruption.  It is strongly advised that
6     users do not edit the contents of this file. -->
7<messages>
8<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem8k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
9</msg>
10
11<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;mem8k8&apos; already exists in the project. Output products for this core may be overwritten.</arg>
12</msg>
13
14<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;mem8k8&apos;...</arg>
15</msg>
16
17<msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol.
18</msg>
19
20<msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation.
21</msg>
22
23</messages>
24
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