source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/mpi_test.vhd

Last change on this file was 139, checked in by rolagamo, 10 years ago

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC

File size: 2.2 KB
Line 
1--------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date:   07:29:14 03/26/2013
6-- Design Name:   
7-- Module Name:   C:/Core MPI/CORE_MPI/mpi_test.vhd
8-- Project Name:  MPI_CORE_COMPONENTS
9-- Target Device: 
10-- Tool versions: 
11-- Description:   
12--
13-- VHDL Test Bench Created by ISE for module: MultiMPITest
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28LIBRARY ieee;
29USE ieee.std_logic_1164.ALL;
30 
31-- Uncomment the following library declaration if using
32-- arithmetic functions with Signed or Unsigned values
33--USE ieee.numeric_std.ALL;
34 
35ENTITY mpi_test IS
36END mpi_test;
37 
38ARCHITECTURE behavior OF mpi_test IS 
39 signal clk,reset : std_logic:='0';
40 signal result : std_logic_vector(7 downto 0);
41    -- Component Declaration for the Unit Under Test (UUT)
42 
43    COMPONENT MultiMPITest
44   
45         port (clkm : in std_logic;
46                reset : in std_logic;
47                Led : out std_logic_vector(7 downto 0));
48     
49    END COMPONENT;
50   
51   -- No clocks detected in port list. Replace <clock> below with
52   -- appropriate port name
53 
54   constant clk_period : time := 10 ns;
55 
56BEGIN
57 
58        -- Instantiate the Unit Under Test (UUT)
59   uut: MultiMPITest PORT MAP (
60                clkm=>clk,
61                reset=>reset,
62                led=>result
63        );
64
65   -- Clock process definitions
66   clk_process :process
67   begin
68                clk <= '0';
69                wait for clk_period/2;
70                clk <= '1';
71                wait for clk_period/2;
72   end process;
73 
74
75   -- Stimulus process
76   stim_proc: process
77   begin               
78      -- hold reset state for 100 ns.
79      reset<='1';
80      wait for clk_period*10;
81                reset<='0';
82      wait ;
83
84      -- insert stimulus here
85
86      wait;
87   end process;
88
89END;
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