Last change
on this file since 127 was
115,
checked in by rolagamo, 10 years ago
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Ajout des Cores utilisés dans le projet
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File size:
726 bytes
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Line | |
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1 | <?xml version="1.0" encoding="UTF-8"?> |
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2 | <!-- IMPORTANT: This is an internal file that has been generated |
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3 | by the Xilinx ISE software. Any direct editing or |
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4 | changes made to this file may result in unpredictable |
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5 | behavior or data corruption. It is strongly advised that |
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6 | users do not edit the contents of this file. --> |
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7 | <messages> |
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8 | <msg type="info" file="sim" num="0" delta="new" >Generating component instance '<arg fmt="%s" index="1">mem_4k8</arg>' of '<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>' from '<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>'. |
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9 | </msg> |
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10 | |
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11 | </messages> |
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12 | |
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