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Crossbar.vhd

Last change on this file was 65, checked in by rolagamo, 12 years ago

File size: 121.0 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: KIEGAING EMMANUEL / GAMOM NGOUNOU
4	--
5	-- Create Date: 11:48:18 06/19/2011
6	-- Design Name:
7	-- Module Name: Crossbar - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: module implémentant les crossbar
12	-- ce module instacie les crossbar 1 bit du fichier crossbit.vhd
13	--
14	-- CROSSBAR GENERIQUE
15	-- Revision: 1.0
16	-- a été retiré les signaux inutilisées comme fp, port_source, etc...
17	-- Revision 0.01 - File Created
18	-- Revision 0.02 Ajout des signaux clk et reset
19	-- Additional Comments: pour la gestion du pipeline
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	library NocLib ;
27	use NocLib.CoreTypes.all;
28	---- Uncomment the following library declaration if instantiating
29	---- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity Crossbar is
34	generic
35	(
36	number_of_crossbar_ports: positive := 8
37	);
38	Port ( clk : in STD_LOGIC;
39	reset : in STD_LOGIC; --pour gérer le pipeline
40	Port1_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
41	Port2_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
42	Port3_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
43	Port4_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
44	Port5_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
45	Port6_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
46	Port7_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
47	Port8_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
48	Port9_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
49	Port10_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
50	Port11_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
51	Port12_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
52	Port13_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
53	Port14_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
54	Port15_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
55	Port16_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
56
57	Port1_pulse_in : in std_logic;
58	Port2_pulse_in : in std_logic;
59	Port3_pulse_in : in std_logic;
60	Port4_pulse_in : in std_logic;
61	Port5_pulse_in : in std_logic;
62	Port6_pulse_in : in std_logic;
63	Port7_pulse_in : in std_logic;
64	Port8_pulse_in : in std_logic;
65	Port9_pulse_in : in std_logic;
66	Port10_pulse_in : in std_logic;
67	Port11_pulse_in : in std_logic;
68	Port12_pulse_in : in std_logic;
69	Port13_pulse_in : in std_logic;
70	Port14_pulse_in : in std_logic;
71	Port15_pulse_in : in std_logic;
72	Port16_pulse_in : in std_logic;
73
74	Port1_pulse_out : out std_logic;
75	Port2_pulse_out : out std_logic;
76	Port3_pulse_out : out std_logic;
77	Port4_pulse_out : out std_logic;
78	Port5_pulse_out : out std_logic;
79	Port6_pulse_out : out std_logic;
80	Port7_pulse_out : out std_logic;
81	Port8_pulse_out : out std_logic;
82	Port9_pulse_out : out std_logic;
83	Port10_pulse_out : out std_logic;
84	Port11_pulse_out : out std_logic;
85	Port12_pulse_out : out std_logic;
86	Port13_pulse_out : out std_logic;
87	Port14_pulse_out : out std_logic;
88	Port15_pulse_out : out std_logic;
89	Port16_pulse_out : out std_logic;
90
91	Port1_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
92	Port2_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
93	Port3_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
94	Port4_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
95	Port5_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
96	Port6_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
97	Port7_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
98	Port8_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
99	Port9_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
100	Port10_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
101	Port11_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
102	Port12_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
103	Port13_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
104	Port14_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
105	Port15_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
106	Port16_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
107
108	Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
109	);
110	end Crossbar;
111
112	architecture Behavioral of Crossbar is
113
114	-- declaration du crossbar un bit instanciés pour former les crossbars
115	COMPONENT Crossbit
116	generic
117	(
118	number_of_ports : positive := 4
119	);
120	Port ( clk,reset : in std_logic;
121	Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
122	Data_In : in STD_LOGIC_VECTOR (number_of_ports downto 1);
123	Data_out : out STD_LOGIC_VECTOR (number_of_ports downto 1));
124	END COMPONENT;
125	signal ctrl_buf: STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1):=(others=>'0');
126	--signal ctrl_chg:std_logic:='0';
127	begin
128	-- La matrice interconnectee
129	-- le circuit genere depend du parametre generique nombre de ports
130	--ctrl_chg<=all_zeros(ctrl_buf xor ctrl); --sur chaque changement du mot de contrôle, mettre à jour ce registre
131	--ctrl_proc:process(ctrl)
132	-- begin
133	ctrl_buf<=ctrl;
134	-- end process;
135	--======================crossbar 2 ports=======================
136
137	crossbar2x2 : if number_of_crossbar_ports = 2 generate
138
139	-- crossbit du bit 0 de donnée
140
141	Data0_Crossbit: Crossbit
142	GENERIC MAP(number_of_ports => 2)
143	PORT MAP(
144	reset => reset,
145	clk =>clk,
146
147	Control => Ctrl_buf,
148	Data_In(1) => Port1_in(0),
149	Data_In(2) => Port2_in(0),
150	Data_out(1)=> Port1_out(0),
151	Data_out(2)=> Port2_out(0)
152
153	);
154	-- crossbit du bit 1 de donnée
155
156	Data1_Crossbit: Crossbit
157	GENERIC MAP(number_of_ports => 2)
158	PORT MAP(
159	reset => reset,
160	clk =>clk,
161
162	Control => Ctrl_buf,
163	Data_In(1) => Port1_in(1),
164	Data_In(2) => Port2_in(1),
165	Data_out(1)=> Port1_out(1),
166	Data_out(2)=> Port2_out(1)
167
168	);
169	-- crossbit du bit 2 de donnée
170
171	Data2_Crossbit: Crossbit
172	GENERIC MAP(number_of_ports => 2)
173	PORT MAP(
174	reset => reset,
175	clk =>clk,
176
177	Control => Ctrl_buf,
178	Data_In(1) => Port1_in(2),
179	Data_In(2) => Port2_in(2),
180	Data_out(1)=> Port1_out(2),
181	Data_out(2)=> Port2_out(2)
182
183	);
184	-- crossbit du bit 3 de donnée
185
186	Data3_Crossbit: Crossbit
187	GENERIC MAP(number_of_ports => 2)
188	PORT MAP(
189	reset => reset,
190	clk =>clk,
191
192	Control => Ctrl_buf,
193	Data_In(1) => Port1_in(3),
194	Data_In(2) => Port2_in(3),
195	Data_out(1)=> Port1_out(3),
196	Data_out(2)=> Port2_out(3)
197
198	);
199	-- crossbit du bit 4 de donnée
200
201	Data4_Crossbit: Crossbit
202	GENERIC MAP(number_of_ports => 2)
203	PORT MAP(
204
205	reset => reset,
206	clk =>clk,
207
208	Control => Ctrl_buf,
209	Data_In(1) => Port1_in(4),
210	Data_In(2) => Port2_in(4),
211	Data_out(1)=> Port1_out(4),
212	Data_out(2)=> Port2_out(4)
213
214	);
215	-- crossbit du bit 5 de donnée
216
217	Data5_Crossbit: Crossbit
218	GENERIC MAP(number_of_ports => 2)
219	PORT MAP(
220
221	reset => reset,
222	clk=>clk,
223	Control => Ctrl_buf,
224	Data_In(1) => Port1_in(5),
225	Data_In(2) => Port2_in(5),
226	Data_out(1)=> Port1_out(5),
227	Data_out(2)=> Port2_out(5)
228
229	);
230	-- crossbit du bit 6 de donnée
231
232	Data6_Crossbit: Crossbit
233	GENERIC MAP(number_of_ports => 2)
234	PORT MAP(
235
236	reset => reset,
237	clk=>clk,
238	Control => Ctrl_buf,
239	Data_In(1) => Port1_in(6),
240	Data_In(2) => Port2_in(6),
241	Data_out(1)=> Port1_out(6),
242	Data_out(2)=> Port2_out(6)
243
244	);
245	-- crossbit du bit 7 de donnée
246
247	Data7_Crossbit: Crossbit
248	GENERIC MAP(number_of_ports => 2)
249	PORT MAP(
250
251	reset => reset,
252	clk=>clk,
253	Control => Ctrl_buf,
254	Data_In(1) => Port1_in(7),
255	Data_In(2) => Port2_in(7),
256	Data_out(1)=> Port1_out(7),
257	Data_out(2)=> Port2_out(7)
258
259	);
260	-- crossbit du pulse_out 2 ports
261
262	Pulse_out_Crossbit2: Crossbit
263	GENERIC MAP(number_of_ports => 2)
264	PORT MAP(
265	reset => reset,
266	clk =>clk,
267
268	Control => Ctrl_buf,
269	Data_In(1) => Port1_pulse_in,
270	Data_In(2) => Port2_pulse_in,
271	Data_out(1) => Port1_pulse_out,
272	Data_out(2) => Port2_pulse_out
273
274	);
275	end generate crossbar2x2;
276
277
278	--======================crossbar 3 ports=======================
279
280	crossbar3x3 : if number_of_crossbar_ports = 3 generate
281
282	-- crossbit du bit 0 de donnée
283
284	Data0_Crossbit: Crossbit
285	GENERIC MAP(number_of_ports => 3)
286	PORT MAP(
287
288	reset => reset,
289	clk =>clk,
290
291	Control => Ctrl_buf,
292	Data_In(1) => Port1_in(0),
293	Data_In(2) => Port2_in(0),
294	Data_In(3) => Port3_in(0),
295	Data_out(1)=> Port1_out(0),
296	Data_out(2)=> Port2_out(0),
297	Data_out(3)=> Port3_out(0)
298
299	);
300	-- crossbit du bit 1 de donnée
301
302	Data1_Crossbit: Crossbit
303	GENERIC MAP(number_of_ports => 3)
304	PORT MAP(
305	reset => reset,
306	clk =>clk,
307
308	Control => Ctrl_buf,
309	Data_In(1) => Port1_in(1),
310	Data_In(2) => Port2_in(1),
311	Data_In(3) => Port3_in(1),
312	Data_out(1)=> Port1_out(1),
313	Data_out(2)=> Port2_out(1),
314	Data_out(3)=> Port3_out(1)
315
316	);
317	-- crossbit du bit 2 de donnée
318
319	Data2_Crossbit: Crossbit
320	GENERIC MAP(number_of_ports => 3)
321	PORT MAP(
322
323	reset => reset,
324	clk=>clk,
325	Control => Ctrl_buf,
326	Data_In(1) => Port1_in(2),
327	Data_In(2) => Port2_in(2),
328	Data_In(3) => Port3_in(2),
329	Data_out(1)=> Port1_out(2),
330	Data_out(2)=> Port2_out(2),
331	Data_out(3)=> Port3_out(2)
332
333	);
334	-- crossbit du bit 3 de donnée
335
336	Data3_Crossbit: Crossbit
337	GENERIC MAP(number_of_ports => 3)
338	PORT MAP(
339	reset => reset,
340	clk =>clk,
341
342	Control => Ctrl_buf,
343	Data_In(1) => Port1_in(3),
344	Data_In(2) => Port2_in(3),
345	Data_In(3) => Port3_in(3),
346	Data_out(1)=> Port1_out(3),
347	Data_out(2)=> Port2_out(3),
348	Data_out(3)=> Port3_out(3)
349
350	);
351	-- crossbit du bit 4 de donnée
352
353	Data4_Crossbit: Crossbit
354	GENERIC MAP(number_of_ports => 3)
355	PORT MAP(
356
357	reset => reset,
358	clk=>clk,
359	Control => Ctrl_buf,
360	Data_In(1) => Port1_in(4),
361	Data_In(2) => Port2_in(4),
362	Data_In(3) => Port3_in(4),
363	Data_out(1)=> Port1_out(4),
364	Data_out(2)=> Port2_out(4),
365	Data_out(3)=> Port3_out(4)
366
367	);
368	-- crossbit du bit 5 de donnée
369
370	Data5_Crossbit: Crossbit
371	GENERIC MAP(number_of_ports => 3)
372	PORT MAP(
373
374	reset => reset,
375	clk=>clk,
376	Control => Ctrl_buf,
377	Data_In(1) => Port1_in(5),
378	Data_In(2) => Port2_in(5),
379	Data_In(3) => Port3_in(5),
380	Data_out(1)=> Port1_out(5),
381	Data_out(2)=> Port2_out(5),
382	Data_out(3)=> Port3_out(5)
383
384	);
385	-- crossbit du bit 6 de donnée
386
387	Data6_Crossbit: Crossbit
388	GENERIC MAP(number_of_ports => 3)
389	PORT MAP(
390
391	reset => reset,
392	clk =>clk,
393
394	Control => Ctrl_buf,
395	Data_In(1) => Port1_in(6),
396	Data_In(2) => Port2_in(6),
397	Data_In(3) => Port3_in(6),
398	Data_out(1)=> Port1_out(6),
399	Data_out(2)=> Port2_out(6),
400	Data_out(3)=> Port3_out(6)
401
402	);
403	-- crossbit du bit 7 de donnée
404
405	Data7_Crossbit: Crossbit
406	GENERIC MAP(number_of_ports => 3)
407	PORT MAP(
408	reset => reset,
409	clk =>clk,
410
411	Control => Ctrl_buf,
412	Data_In(1) => Port1_in(7),
413	Data_In(2) => Port2_in(7),
414	Data_In(3) => Port3_in(7),
415	Data_out(1)=> Port1_out(7),
416	Data_out(2)=> Port2_out(7),
417	Data_out(3)=> Port3_out(7)
418
419	);
420	-- crossbit du pulse_out 3 ports
421
422	Pulse_out_Crossbit3: Crossbit
423	GENERIC MAP(number_of_ports => 3)
424	PORT MAP(
425	reset => reset,
426	clk =>clk,
427
428	Control => Ctrl_buf,
429	Data_In(1) => Port1_pulse_in,
430	Data_In(2) => Port2_pulse_in,
431	Data_In(3) => Port3_pulse_in,
432	Data_out(1) => Port1_pulse_out,
433	Data_out(2) => Port2_pulse_out,
434	Data_out(3) => Port3_pulse_out
435
436	);
437	end generate crossbar3x3;
438
439
440	--======================crossbar 4 ports=======================
441
442	crossbar4x4 : if number_of_crossbar_ports = 4 generate
443
444	-- crossbit du bit 0 de donnée
445
446	Data0_Crossbit: Crossbit
447	GENERIC MAP(number_of_ports => 4)
448	PORT MAP(
449
450	reset => reset,
451	clk=>clk,
452	Control => Ctrl_buf,
453	Data_In(1) => Port1_in(0),
454	Data_In(2) => Port2_in(0),
455	Data_In(3) => Port3_in(0),
456	Data_In(4) => Port4_in(0),
457	Data_out(1)=> Port1_out(0),
458	Data_out(2)=> Port2_out(0),
459	Data_out(3)=> Port3_out(0),
460	Data_out(4)=> Port4_out(0)
461
462	);
463	-- crossbit du bit 1 de donnée
464
465	Data1_Crossbit: Crossbit
466	GENERIC MAP(number_of_ports => 4)
467	PORT MAP(
468
469	reset => reset,
470	clk=>clk,
471	Control => Ctrl_buf,
472	Data_In(1) => Port1_in(1),
473	Data_In(2) => Port2_in(1),
474	Data_In(3) => Port3_in(1),
475	Data_In(4) => Port4_in(1),
476	Data_out(1)=> Port1_out(1),
477	Data_out(2)=> Port2_out(1),
478	Data_out(3)=> Port3_out(1),
479	Data_out(4)=> Port4_out(1)
480
481	);
482	-- crossbit du bit 2 de donnée
483
484	Data2_Crossbit: Crossbit
485	GENERIC MAP(number_of_ports => 4)
486	PORT MAP(
487
488	reset => reset,
489	clk=>clk,
490	Control => Ctrl_buf,
491	Data_In(1) => Port1_in(2),
492	Data_In(2) => Port2_in(2),
493	Data_In(3) => Port3_in(2),
494	Data_In(4) => Port4_in(2),
495	Data_out(1)=> Port1_out(2),
496	Data_out(2)=> Port2_out(2),
497	Data_out(3)=> Port3_out(2),
498	Data_out(4)=> Port4_out(2)
499
500	);
501	-- crossbit du bit 3 de donnée
502
503	Data3_Crossbit: Crossbit
504	GENERIC MAP(number_of_ports => 4)
505	PORT MAP(
506
507	reset => reset,
508	clk=>clk,
509	Control => Ctrl_buf,
510	Data_In(1) => Port1_in(3),
511	Data_In(2) => Port2_in(3),
512	Data_In(3) => Port3_in(3),
513	Data_In(4) => Port4_in(3),
514	Data_out(1)=> Port1_out(3),
515	Data_out(2)=> Port2_out(3),
516	Data_out(3)=> Port3_out(3),
517	Data_out(4)=> Port4_out(3)
518
519	);
520	-- crossbit du bit 4 de donnée
521
522	Data4_Crossbit: Crossbit
523	GENERIC MAP(number_of_ports => 4)
524	PORT MAP(
525
526	reset => reset,
527	clk=>clk,
528	Control => Ctrl_buf,
529	Data_In(1) => Port1_in(4),
530	Data_In(2) => Port2_in(4),
531	Data_In(3) => Port3_in(4),
532	Data_In(4) => Port4_in(4),
533	Data_out(1)=> Port1_out(4),
534	Data_out(2)=> Port2_out(4),
535	Data_out(3)=> Port3_out(4),
536	Data_out(4)=> Port4_out(4)
537
538	);
539	-- crossbit du bit 5 de donnée
540
541	Data5_Crossbit: Crossbit
542	GENERIC MAP(number_of_ports => 4)
543	PORT MAP(
544
545	reset => reset,
546	clk=>clk,
547	Control => Ctrl_buf,
548	Data_In(1) => Port1_in(5),
549	Data_In(2) => Port2_in(5),
550	Data_In(3) => Port3_in(5),
551	Data_In(4) => Port4_in(5),
552	Data_out(1)=> Port1_out(5),
553	Data_out(2)=> Port2_out(5),
554	Data_out(3)=> Port3_out(5),
555	Data_out(4)=> Port4_out(5)
556
557	);
558	-- crossbit du bit 6 de donnée
559
560	Data6_Crossbit: Crossbit
561	GENERIC MAP(number_of_ports => 4)
562	PORT MAP(
563
564	reset => reset,
565	clk=>clk,
566	Control => Ctrl_buf,
567	Data_In(1) => Port1_in(6),
568	Data_In(2) => Port2_in(6),
569	Data_In(3) => Port3_in(6),
570	Data_In(4) => Port4_in(6),
571	Data_out(1)=> Port1_out(6),
572	Data_out(2)=> Port2_out(6),
573	Data_out(3)=> Port3_out(6),
574	Data_out(4)=> Port4_out(6)
575
576	);
577	-- crossbit du bit 7 de donnée
578
579	Data7_Crossbit: Crossbit
580	GENERIC MAP(number_of_ports => 4)
581	PORT MAP(
582
583	reset => reset,
584	clk=>clk,
585	Control => Ctrl_buf,
586	Data_In(1) => Port1_in(7),
587	Data_In(2) => Port2_in(7),
588	Data_In(3) => Port3_in(7),
589	Data_In(4) => Port4_in(7),
590	Data_out(1)=> Port1_out(7),
591	Data_out(2)=> Port2_out(7),
592	Data_out(3)=> Port3_out(7),
593	Data_out(4)=> Port4_out(7)
594
595	);
596	-- crossbit du pulse_out 4 ports
597
598	Pulse_out_Crossbit4: Crossbit
599	GENERIC MAP(number_of_ports => 4)
600	PORT MAP(
601
602	reset => reset,
603	clk=>clk,
604	Control => Ctrl_buf,
605	Data_In(1) => Port1_pulse_in,
606	Data_In(2) => Port2_pulse_in,
607	Data_In(3) => Port3_pulse_in,
608	Data_In(4) => Port4_pulse_in,
609	Data_out(1) => Port1_pulse_out,
610	Data_out(2) => Port2_pulse_out,
611	Data_out(3) => Port3_pulse_out,
612	Data_out(4) => Port4_pulse_out
613
614	);
615	end generate crossbar4x4;
616
617
618	--======================crossbar 5 ports=======================
619
620	crossbar5x5 : if number_of_crossbar_ports = 5 generate
621
622	-- crossbit du bit 0 de donnée
623
624	Data0_Crossbit: Crossbit
625	GENERIC MAP(number_of_ports => 5)
626	PORT MAP(
627
628	reset => reset,
629	clk=>clk,
630	Control => Ctrl_buf,
631	Data_In(1) => Port1_in(0),
632	Data_In(2) => Port2_in(0),
633	Data_In(3) => Port3_in(0),
634	Data_In(4) => Port4_in(0),
635	Data_In(5) => Port5_in(0),
636	Data_out(1)=> Port1_out(0),
637	Data_out(2)=> Port2_out(0),
638	Data_out(3)=> Port3_out(0),
639	Data_out(4)=> Port4_out(0),
640	Data_out(5)=> Port5_out(0)
641
642	);
643	-- crossbit du bit 1 de donnée
644
645	Data1_Crossbit: Crossbit
646	GENERIC MAP(number_of_ports => 5)
647	PORT MAP(
648
649	reset => reset,
650	clk=>clk,
651	Control => Ctrl_buf,
652	Data_In(1) => Port1_in(1),
653	Data_In(2) => Port2_in(1),
654	Data_In(3) => Port3_in(1),
655	Data_In(4) => Port4_in(1),
656	Data_In(5) => Port5_in(1),
657	Data_out(1)=> Port1_out(1),
658	Data_out(2)=> Port2_out(1),
659	Data_out(3)=> Port3_out(1),
660	Data_out(4)=> Port4_out(1),
661	Data_out(5)=> Port5_out(1)
662
663	);
664	-- crossbit du bit 2 de donnée
665
666	Data2_Crossbit: Crossbit
667	GENERIC MAP(number_of_ports => 5)
668	PORT MAP(
669
670	reset => reset,
671	clk=>clk,
672	Control => Ctrl_buf,
673	Data_In(1) => Port1_in(2),
674	Data_In(2) => Port2_in(2),
675	Data_In(3) => Port3_in(2),
676	Data_In(4) => Port4_in(2),
677	Data_In(5) => Port5_in(2),
678	Data_out(1)=> Port1_out(2),
679	Data_out(2)=> Port2_out(2),
680	Data_out(3)=> Port3_out(2),
681	Data_out(4)=> Port4_out(2),
682	Data_out(5)=> Port5_out(2)
683
684	);
685	-- crossbit du bit 3 de donnée
686
687	Data3_Crossbit: Crossbit
688	GENERIC MAP(number_of_ports => 5)
689	PORT MAP(
690
691	reset => reset,
692	clk=>clk,
693	Control => Ctrl_buf,
694	Data_In(1) => Port1_in(3),
695	Data_In(2) => Port2_in(3),
696	Data_In(3) => Port3_in(3),
697	Data_In(4) => Port4_in(3),
698	Data_In(5) => Port5_in(3),
699	Data_out(1)=> Port1_out(3),
700	Data_out(2)=> Port2_out(3),
701	Data_out(3)=> Port3_out(3),
702	Data_out(4)=> Port4_out(3),
703	Data_out(5)=> Port5_out(3)
704
705	);
706	-- crossbit du bit 4 de donnée
707
708	Data4_Crossbit: Crossbit
709	GENERIC MAP(number_of_ports => 5)
710	PORT MAP(
711
712	reset => reset,
713	clk=>clk,
714	Control => Ctrl_buf,
715	Data_In(1) => Port1_in(4),
716	Data_In(2) => Port2_in(4),
717	Data_In(3) => Port3_in(4),
718	Data_In(4) => Port4_in(4),
719	Data_In(5) => Port5_in(4),
720	Data_out(1)=> Port1_out(4),
721	Data_out(2)=> Port2_out(4),
722	Data_out(3)=> Port3_out(4),
723	Data_out(4)=> Port4_out(4),
724	Data_out(5)=> Port5_out(4)
725
726	);
727	-- crossbit du bit 5 de donnée
728
729	Data5_Crossbit: Crossbit
730	GENERIC MAP(number_of_ports => 5)
731	PORT MAP(
732
733	reset => reset,
734	clk=>clk,
735	Control => Ctrl_buf,
736	Data_In(1) => Port1_in(5),
737	Data_In(2) => Port2_in(5),
738	Data_In(3) => Port3_in(5),
739	Data_In(4) => Port4_in(5),
740	Data_In(5) => Port5_in(5),
741	Data_out(1)=> Port1_out(5),
742	Data_out(2)=> Port2_out(5),
743	Data_out(3)=> Port3_out(5),
744	Data_out(4)=> Port4_out(5),
745	Data_out(5)=> Port5_out(5)
746
747	);
748	-- crossbit du bit 6 de donnée
749
750	Data6_Crossbit: Crossbit
751	GENERIC MAP(number_of_ports => 5)
752	PORT MAP(
753
754	reset => reset,
755	clk=>clk,
756	Control => Ctrl_buf,
757	Data_In(1) => Port1_in(6),
758	Data_In(2) => Port2_in(6),
759	Data_In(3) => Port3_in(6),
760	Data_In(4) => Port4_in(6),
761	Data_In(5) => Port5_in(6),
762	Data_out(1)=> Port1_out(6),
763	Data_out(2)=> Port2_out(6),
764	Data_out(3)=> Port3_out(6),
765	Data_out(4)=> Port4_out(6),
766	Data_out(5)=> Port5_out(6)
767
768	);
769	-- crossbit du bit 7 de donnée
770
771	Data7_Crossbit: Crossbit
772	GENERIC MAP(number_of_ports => 5)
773	PORT MAP(
774
775	reset => reset,
776	clk=>clk,
777	Control => Ctrl_buf,
778	Data_In(1) => Port1_in(7),
779	Data_In(2) => Port2_in(7),
780	Data_In(3) => Port3_in(7),
781	Data_In(4) => Port4_in(7),
782	Data_In(5) => Port5_in(7),
783	Data_out(1)=> Port1_out(7),
784	Data_out(2)=> Port2_out(7),
785	Data_out(3)=> Port3_out(7),
786	Data_out(4)=> Port4_out(7),
787	Data_out(5)=> Port5_out(7)
788
789	);
790	-- crossbit du pulse_out 5 ports
791
792	Pulse_out_Crossbit5: Crossbit
793	GENERIC MAP(number_of_ports => 5)
794	PORT MAP(
795
796	reset => reset,
797	clk=>clk,
798	Control => Ctrl_buf,
799	Data_In(1) => Port1_pulse_in,
800	Data_In(2) => Port2_pulse_in,
801	Data_In(3) => Port3_pulse_in,
802	Data_In(4) => Port4_pulse_in,
803	Data_In(5) => Port5_pulse_in,
804	Data_out(1) => Port1_pulse_out,
805	Data_out(2) => Port2_pulse_out,
806	Data_out(3) => Port3_pulse_out,
807	Data_out(4) => Port4_pulse_out,
808	Data_out(5) => Port5_pulse_out
809
810	);
811	end generate crossbar5x5;
812
813
814	--======================crossbar 6 ports=======================
815
816	crossbar6x6 : if number_of_crossbar_ports = 6 generate
817
818	-- crossbit du bit 0 de donnée
819
820	Data0_Crossbit: Crossbit
821	GENERIC MAP(number_of_ports => 6)
822	PORT MAP(
823
824	reset => reset,
825	clk=>clk,
826	Control => Ctrl_buf,
827	Data_In(1) => Port1_in(0),
828	Data_In(2) => Port2_in(0),
829	Data_In(3) => Port3_in(0),
830	Data_In(4) => Port4_in(0),
831	Data_In(5) => Port5_in(0),
832	Data_In(6) => Port6_in(0),
833	Data_out(1)=> Port1_out(0),
834	Data_out(2)=> Port2_out(0),
835	Data_out(3)=> Port3_out(0),
836	Data_out(4)=> Port4_out(0),
837	Data_out(5)=> Port5_out(0),
838	Data_out(6)=> Port6_out(0)
839
840	);
841	-- crossbit du bit 1 de donnée
842
843	Data1_Crossbit: Crossbit
844	GENERIC MAP(number_of_ports => 6)
845	PORT MAP(
846
847	reset => reset,
848	clk=>clk,
849	Control => Ctrl_buf,
850	Data_In(1) => Port1_in(1),
851	Data_In(2) => Port2_in(1),
852	Data_In(3) => Port3_in(1),
853	Data_In(4) => Port4_in(1),
854	Data_In(5) => Port5_in(1),
855	Data_In(6) => Port6_in(1),
856	Data_out(1)=> Port1_out(1),
857	Data_out(2)=> Port2_out(1),
858	Data_out(3)=> Port3_out(1),
859	Data_out(4)=> Port4_out(1),
860	Data_out(5)=> Port5_out(1),
861	Data_out(6)=> Port6_out(1)
862
863	);
864	-- crossbit du bit 2 de donnée
865
866	Data2_Crossbit: Crossbit
867	GENERIC MAP(number_of_ports => 6)
868	PORT MAP(
869
870	reset => reset,
871	clk=>clk,
872	Control => Ctrl_buf,
873	Data_In(1) => Port1_in(2),
874	Data_In(2) => Port2_in(2),
875	Data_In(3) => Port3_in(2),
876	Data_In(4) => Port4_in(2),
877	Data_In(5) => Port5_in(2),
878	Data_In(6) => Port6_in(2),
879	Data_out(1)=> Port1_out(2),
880	Data_out(2)=> Port2_out(2),
881	Data_out(3)=> Port3_out(2),
882	Data_out(4)=> Port4_out(2),
883	Data_out(5)=> Port5_out(2),
884	Data_out(6)=> Port6_out(2)
885
886	);
887	-- crossbit du bit 3 de donnée
888
889	Data3_Crossbit: Crossbit
890	GENERIC MAP(number_of_ports => 6)
891	PORT MAP(
892
893	reset => reset,
894	clk=>clk,
895	Control => Ctrl_buf,
896	Data_In(1) => Port1_in(3),
897	Data_In(2) => Port2_in(3),
898	Data_In(3) => Port3_in(3),
899	Data_In(4) => Port4_in(3),
900	Data_In(5) => Port5_in(3),
901	Data_In(6) => Port6_in(3),
902	Data_out(1)=> Port1_out(3),
903	Data_out(2)=> Port2_out(3),
904	Data_out(3)=> Port3_out(3),
905	Data_out(4)=> Port4_out(3),
906	Data_out(5)=> Port5_out(3),
907	Data_out(6)=> Port6_out(3)
908
909	);
910	-- crossbit du bit 4 de donnée
911
912	Data4_Crossbit: Crossbit
913	GENERIC MAP(number_of_ports => 6)
914	PORT MAP(
915
916	reset => reset,
917	clk=>clk,
918	Control => Ctrl_buf,
919	Data_In(1) => Port1_in(4),
920	Data_In(2) => Port2_in(4),
921	Data_In(3) => Port3_in(4),
922	Data_In(4) => Port4_in(4),
923	Data_In(5) => Port5_in(4),
924	Data_In(6) => Port6_in(4),
925	Data_out(1)=> Port1_out(4),
926	Data_out(2)=> Port2_out(4),
927	Data_out(3)=> Port3_out(4),
928	Data_out(4)=> Port4_out(4),
929	Data_out(5)=> Port5_out(4),
930	Data_out(6)=> Port6_out(4)
931
932	);
933	-- crossbit du bit 5 de donnée
934
935	Data5_Crossbit: Crossbit
936	GENERIC MAP(number_of_ports => 6)
937	PORT MAP(
938
939	reset => reset,
940	clk=>clk,
941	Control => Ctrl_buf,
942	Data_In(1) => Port1_in(5),
943	Data_In(2) => Port2_in(5),
944	Data_In(3) => Port3_in(5),
945	Data_In(4) => Port4_in(5),
946	Data_In(5) => Port5_in(5),
947	Data_In(6) => Port6_in(5),
948	Data_out(1)=> Port1_out(5),
949	Data_out(2)=> Port2_out(5),
950	Data_out(3)=> Port3_out(5),
951	Data_out(4)=> Port4_out(5),
952	Data_out(5)=> Port5_out(5),
953	Data_out(6)=> Port6_out(5)
954
955	);
956	-- crossbit du bit 6 de donnée
957
958	Data6_Crossbit: Crossbit
959	GENERIC MAP(number_of_ports => 6)
960	PORT MAP(
961
962	reset => reset,
963	clk=>clk,
964	Control => Ctrl_buf,
965	Data_In(1) => Port1_in(6),
966	Data_In(2) => Port2_in(6),
967	Data_In(3) => Port3_in(6),
968	Data_In(4) => Port4_in(6),
969	Data_In(5) => Port5_in(6),
970	Data_In(6) => Port6_in(6),
971	Data_out(1)=> Port1_out(6),
972	Data_out(2)=> Port2_out(6),
973	Data_out(3)=> Port3_out(6),
974	Data_out(4)=> Port4_out(6),
975	Data_out(5)=> Port5_out(6),
976	Data_out(6)=> Port6_out(6)
977
978	);
979	-- crossbit du bit 7 de donnée
980
981	Data7_Crossbit: Crossbit
982	GENERIC MAP(number_of_ports => 6)
983	PORT MAP(
984
985	reset => reset,
986	clk=>clk,
987	Control => Ctrl_buf,
988	Data_In(1) => Port1_in(7),
989	Data_In(2) => Port2_in(7),
990	Data_In(3) => Port3_in(7),
991	Data_In(4) => Port4_in(7),
992	Data_In(5) => Port5_in(7),
993	Data_In(6) => Port6_in(7),
994	Data_out(1)=> Port1_out(7),
995	Data_out(2)=> Port2_out(7),
996	Data_out(3)=> Port3_out(7),
997	Data_out(4)=> Port4_out(7),
998	Data_out(5)=> Port5_out(7),
999	Data_out(6)=> Port6_out(7)
1000
1001	);
1002	-- crossbit du pulse_out 6 ports
1003
1004	Pulse_out_Crossbit6: Crossbit
1005	GENERIC MAP(number_of_ports => 6)
1006	PORT MAP(
1007
1008	reset => reset,
1009	clk=>clk,
1010	Control => Ctrl_buf,
1011	Data_In(1) => Port1_pulse_in,
1012	Data_In(2) => Port2_pulse_in,
1013	Data_In(3) => Port3_pulse_in,
1014	Data_In(4) => Port4_pulse_in,
1015	Data_In(5) => Port5_pulse_in,
1016	Data_In(6) => Port6_pulse_in,
1017	Data_out(1) => Port1_pulse_out,
1018	Data_out(2) => Port2_pulse_out,
1019	Data_out(3) => Port3_pulse_out,
1020	Data_out(4) => Port4_pulse_out,
1021	Data_out(5) => Port5_pulse_out,
1022	Data_out(6) => Port6_pulse_out
1023
1024	);
1025	end generate crossbar6x6;
1026
1027
1028	--======================crossbar 7 ports=======================
1029
1030	crossbar7x7 : if number_of_crossbar_ports = 7 generate
1031
1032	-- crossbit du bit 0 de donnée
1033
1034	Data0_Crossbit: Crossbit
1035	GENERIC MAP(number_of_ports => 7)
1036	PORT MAP(
1037
1038	reset => reset,
1039	clk=>clk,
1040	Control => Ctrl_buf,
1041	Data_In(1) => Port1_in(0),
1042	Data_In(2) => Port2_in(0),
1043	Data_In(3) => Port3_in(0),
1044	Data_In(4) => Port4_in(0),
1045	Data_In(5) => Port5_in(0),
1046	Data_In(6) => Port6_in(0),
1047	Data_In(7) => Port7_in(0),
1048	Data_out(1)=> Port1_out(0),
1049	Data_out(2)=> Port2_out(0),
1050	Data_out(3)=> Port3_out(0),
1051	Data_out(4)=> Port4_out(0),
1052	Data_out(5)=> Port5_out(0),
1053	Data_out(6)=> Port6_out(0),
1054	Data_out(7)=> Port7_out(0)
1055
1056	);
1057	-- crossbit du bit 1 de donnée
1058
1059	Data1_Crossbit: Crossbit
1060	GENERIC MAP(number_of_ports => 7)
1061	PORT MAP(
1062
1063	reset => reset,
1064	clk=>clk,
1065	Control => Ctrl_buf,
1066	Data_In(1) => Port1_in(1),
1067	Data_In(2) => Port2_in(1),
1068	Data_In(3) => Port3_in(1),
1069	Data_In(4) => Port4_in(1),
1070	Data_In(5) => Port5_in(1),
1071	Data_In(6) => Port6_in(1),
1072	Data_In(7) => Port7_in(1),
1073	Data_out(1)=> Port1_out(1),
1074	Data_out(2)=> Port2_out(1),
1075	Data_out(3)=> Port3_out(1),
1076	Data_out(4)=> Port4_out(1),
1077	Data_out(5)=> Port5_out(1),
1078	Data_out(6)=> Port6_out(1),
1079	Data_out(7)=> Port7_out(1)
1080
1081	);
1082	-- crossbit du bit 2 de donnée
1083
1084	Data2_Crossbit: Crossbit
1085	GENERIC MAP(number_of_ports => 7)
1086	PORT MAP(
1087
1088	reset => reset,
1089	clk=>clk,
1090	Control => Ctrl_buf,
1091	Data_In(1) => Port1_in(2),
1092	Data_In(2) => Port2_in(2),
1093	Data_In(3) => Port3_in(2),
1094	Data_In(4) => Port4_in(2),
1095	Data_In(5) => Port5_in(2),
1096	Data_In(6) => Port6_in(2),
1097	Data_In(7) => Port7_in(2),
1098	Data_out(1)=> Port1_out(2),
1099	Data_out(2)=> Port2_out(2),
1100	Data_out(3)=> Port3_out(2),
1101	Data_out(4)=> Port4_out(2),
1102	Data_out(5)=> Port5_out(2),
1103	Data_out(6)=> Port6_out(2),
1104	Data_out(7)=> Port7_out(2)
1105
1106	);
1107	-- crossbit du bit 3 de donnée
1108
1109	Data3_Crossbit: Crossbit
1110	GENERIC MAP(number_of_ports => 7)
1111	PORT MAP(
1112
1113	reset => reset,
1114	clk=>clk,
1115	Control => Ctrl_buf,
1116	Data_In(1) => Port1_in(3),
1117	Data_In(2) => Port2_in(3),
1118	Data_In(3) => Port3_in(3),
1119	Data_In(4) => Port4_in(3),
1120	Data_In(5) => Port5_in(3),
1121	Data_In(6) => Port6_in(3),
1122	Data_In(7) => Port7_in(3),
1123	Data_out(1)=> Port1_out(3),
1124	Data_out(2)=> Port2_out(3),
1125	Data_out(3)=> Port3_out(3),
1126	Data_out(4)=> Port4_out(3),
1127	Data_out(5)=> Port5_out(3),
1128	Data_out(6)=> Port6_out(3),
1129	Data_out(7)=> Port7_out(3)
1130
1131	);
1132	-- crossbit du bit 4 de donnée
1133
1134	Data4_Crossbit: Crossbit
1135	GENERIC MAP(number_of_ports => 7)
1136	PORT MAP(
1137
1138	reset => reset,
1139	clk=>clk,
1140	Control => Ctrl_buf,
1141	Data_In(1) => Port1_in(4),
1142	Data_In(2) => Port2_in(4),
1143	Data_In(3) => Port3_in(4),
1144	Data_In(4) => Port4_in(4),
1145	Data_In(5) => Port5_in(4),
1146	Data_In(6) => Port6_in(4),
1147	Data_In(7) => Port7_in(4),
1148	Data_out(1)=> Port1_out(4),
1149	Data_out(2)=> Port2_out(4),
1150	Data_out(3)=> Port3_out(4),
1151	Data_out(4)=> Port4_out(4),
1152	Data_out(5)=> Port5_out(4),
1153	Data_out(6)=> Port6_out(4),
1154	Data_out(7)=> Port7_out(4)
1155
1156	);
1157	-- crossbit du bit 5 de donnée
1158
1159	Data5_Crossbit: Crossbit
1160	GENERIC MAP(number_of_ports => 7)
1161	PORT MAP(
1162
1163	reset => reset,
1164	clk=>clk,
1165	Control => Ctrl_buf,
1166	Data_In(1) => Port1_in(5),
1167	Data_In(2) => Port2_in(5),
1168	Data_In(3) => Port3_in(5),
1169	Data_In(4) => Port4_in(5),
1170	Data_In(5) => Port5_in(5),
1171	Data_In(6) => Port6_in(5),
1172	Data_In(7) => Port7_in(5),
1173	Data_out(1)=> Port1_out(5),
1174	Data_out(2)=> Port2_out(5),
1175	Data_out(3)=> Port3_out(5),
1176	Data_out(4)=> Port4_out(5),
1177	Data_out(5)=> Port5_out(5),
1178	Data_out(6)=> Port6_out(5),
1179	Data_out(7)=> Port7_out(5)
1180
1181	);
1182	-- crossbit du bit 6 de donnée
1183
1184	Data6_Crossbit: Crossbit
1185	GENERIC MAP(number_of_ports => 7)
1186	PORT MAP(
1187
1188	reset => reset,
1189	clk=>clk,
1190	Control => Ctrl_buf,
1191	Data_In(1) => Port1_in(6),
1192	Data_In(2) => Port2_in(6),
1193	Data_In(3) => Port3_in(6),
1194	Data_In(4) => Port4_in(6),
1195	Data_In(5) => Port5_in(6),
1196	Data_In(6) => Port6_in(6),
1197	Data_In(7) => Port7_in(6),
1198	Data_out(1)=> Port1_out(6),
1199	Data_out(2)=> Port2_out(6),
1200	Data_out(3)=> Port3_out(6),
1201	Data_out(4)=> Port4_out(6),
1202	Data_out(5)=> Port5_out(6),
1203	Data_out(6)=> Port6_out(6),
1204	Data_out(7)=> Port7_out(6)
1205
1206	);
1207	-- crossbit du bit 7 de donnée
1208
1209	Data7_Crossbit: Crossbit
1210	GENERIC MAP(number_of_ports => 7)
1211	PORT MAP(
1212
1213	reset => reset,
1214	clk=>clk,
1215	Control => Ctrl_buf,
1216	Data_In(1) => Port1_in(7),
1217	Data_In(2) => Port2_in(7),
1218	Data_In(3) => Port3_in(7),
1219	Data_In(4) => Port4_in(7),
1220	Data_In(5) => Port5_in(7),
1221	Data_In(6) => Port6_in(7),
1222	Data_In(7) => Port7_in(7),
1223	Data_out(1)=> Port1_out(7),
1224	Data_out(2)=> Port2_out(7),
1225	Data_out(3)=> Port3_out(7),
1226	Data_out(4)=> Port4_out(7),
1227	Data_out(5)=> Port5_out(7),
1228	Data_out(6)=> Port6_out(7),
1229	Data_out(7)=> Port7_out(7)
1230
1231	);
1232	-- crossbit du pulse_out 7 ports
1233
1234	Pulse_out_Crossbit7: Crossbit
1235	GENERIC MAP(number_of_ports => 7)
1236	PORT MAP(
1237
1238	reset => reset,
1239	clk=>clk,
1240	Control => Ctrl_buf,
1241	Data_In(1) => Port1_pulse_in,
1242	Data_In(2) => Port2_pulse_in,
1243	Data_In(3) => Port3_pulse_in,
1244	Data_In(4) => Port4_pulse_in,
1245	Data_In(5) => Port5_pulse_in,
1246	Data_In(6) => Port6_pulse_in,
1247	Data_In(7) => Port7_pulse_in,
1248	Data_out(1) => Port1_pulse_out,
1249	Data_out(2) => Port2_pulse_out,
1250	Data_out(3) => Port3_pulse_out,
1251	Data_out(4) => Port4_pulse_out,
1252	Data_out(5) => Port5_pulse_out,
1253	Data_out(6) => Port6_pulse_out,
1254	Data_out(7) => Port7_pulse_out
1255
1256	);
1257	end generate crossbar7x7;
1258
1259
1260	--======================crossbar 8 ports=======================
1261
1262	crossbar8x8 : if number_of_crossbar_ports = 8 generate
1263
1264	-- crossbit du bit 0 de donnée
1265
1266	Data0_Crossbit: Crossbit
1267	GENERIC MAP(number_of_ports => 8)
1268	PORT MAP(
1269	clk =>clk,
1270	reset =>reset,
1271
1272	Control => Ctrl_buf,
1273	Data_In(1) => Port1_in(0),
1274	Data_In(2) => Port2_in(0),
1275	Data_In(3) => Port3_in(0),
1276	Data_In(4) => Port4_in(0),
1277	Data_In(5) => Port5_in(0),
1278	Data_In(6) => Port6_in(0),
1279	Data_In(7) => Port7_in(0),
1280	Data_In(8) => Port8_in(0),
1281	Data_out(1)=> Port1_out(0),
1282	Data_out(2)=> Port2_out(0),
1283	Data_out(3)=> Port3_out(0),
1284	Data_out(4)=> Port4_out(0),
1285	Data_out(5)=> Port5_out(0),
1286	Data_out(6)=> Port6_out(0),
1287	Data_out(7)=> Port7_out(0),
1288	Data_out(8)=> Port8_out(0)
1289
1290	);
1291	-- crossbit du bit 1 de donnée
1292
1293	Data1_Crossbit: Crossbit
1294	GENERIC MAP(number_of_ports => 8)
1295	PORT MAP(
1296	clk =>clk,
1297	reset =>reset,
1298
1299	Control => Ctrl_buf,
1300	Data_In(1) => Port1_in(1),
1301	Data_In(2) => Port2_in(1),
1302	Data_In(3) => Port3_in(1),
1303	Data_In(4) => Port4_in(1),
1304	Data_In(5) => Port5_in(1),
1305	Data_In(6) => Port6_in(1),
1306	Data_In(7) => Port7_in(1),
1307	Data_In(8) => Port8_in(1),
1308	Data_out(1)=> Port1_out(1),
1309	Data_out(2)=> Port2_out(1),
1310	Data_out(3)=> Port3_out(1),
1311	Data_out(4)=> Port4_out(1),
1312	Data_out(5)=> Port5_out(1),
1313	Data_out(6)=> Port6_out(1),
1314	Data_out(7)=> Port7_out(1),
1315	Data_out(8)=> Port8_out(1)
1316
1317	);
1318	-- crossbit du bit 2 de donnée
1319
1320	Data2_Crossbit: Crossbit
1321	GENERIC MAP(number_of_ports => 8)
1322	PORT MAP(
1323	clk =>clk,
1324	reset =>reset,
1325
1326	Control => Ctrl_buf,
1327	Data_In(1) => Port1_in(2),
1328	Data_In(2) => Port2_in(2),
1329	Data_In(3) => Port3_in(2),
1330	Data_In(4) => Port4_in(2),
1331	Data_In(5) => Port5_in(2),
1332	Data_In(6) => Port6_in(2),
1333	Data_In(7) => Port7_in(2),
1334	Data_In(8) => Port8_in(2),
1335	Data_out(1)=> Port1_out(2),
1336	Data_out(2)=> Port2_out(2),
1337	Data_out(3)=> Port3_out(2),
1338	Data_out(4)=> Port4_out(2),
1339	Data_out(5)=> Port5_out(2),
1340	Data_out(6)=> Port6_out(2),
1341	Data_out(7)=> Port7_out(2),
1342	Data_out(8)=> Port8_out(2)
1343
1344	);
1345	-- crossbit du bit 3 de donnée
1346
1347	Data3_Crossbit: Crossbit
1348	GENERIC MAP(number_of_ports => 8)
1349	PORT MAP(
1350	clk =>clk,
1351	reset =>reset,
1352
1353	Control => Ctrl_buf,
1354	Data_In(1) => Port1_in(3),
1355	Data_In(2) => Port2_in(3),
1356	Data_In(3) => Port3_in(3),
1357	Data_In(4) => Port4_in(3),
1358	Data_In(5) => Port5_in(3),
1359	Data_In(6) => Port6_in(3),
1360	Data_In(7) => Port7_in(3),
1361	Data_In(8) => Port8_in(3),
1362	Data_out(1)=> Port1_out(3),
1363	Data_out(2)=> Port2_out(3),
1364	Data_out(3)=> Port3_out(3),
1365	Data_out(4)=> Port4_out(3),
1366	Data_out(5)=> Port5_out(3),
1367	Data_out(6)=> Port6_out(3),
1368	Data_out(7)=> Port7_out(3),
1369	Data_out(8)=> Port8_out(3)
1370
1371	);
1372	-- crossbit du bit 4 de donnée
1373
1374	Data4_Crossbit: Crossbit
1375	GENERIC MAP(number_of_ports => 8)
1376	PORT MAP(
1377	clk =>clk,
1378	reset =>reset,
1379
1380	Control => Ctrl_buf,
1381	Data_In(1) => Port1_in(4),
1382	Data_In(2) => Port2_in(4),
1383	Data_In(3) => Port3_in(4),
1384	Data_In(4) => Port4_in(4),
1385	Data_In(5) => Port5_in(4),
1386	Data_In(6) => Port6_in(4),
1387	Data_In(7) => Port7_in(4),
1388	Data_In(8) => Port8_in(4),
1389	Data_out(1)=> Port1_out(4),
1390	Data_out(2)=> Port2_out(4),
1391	Data_out(3)=> Port3_out(4),
1392	Data_out(4)=> Port4_out(4),
1393	Data_out(5)=> Port5_out(4),
1394	Data_out(6)=> Port6_out(4),
1395	Data_out(7)=> Port7_out(4),
1396	Data_out(8)=> Port8_out(4)
1397
1398	);
1399	-- crossbit du bit 5 de donnée
1400
1401	Data5_Crossbit: Crossbit
1402	GENERIC MAP(number_of_ports => 8)
1403	PORT MAP(
1404	clk =>clk,
1405	reset =>reset,
1406
1407	Control => Ctrl_buf,
1408	Data_In(1) => Port1_in(5),
1409	Data_In(2) => Port2_in(5),
1410	Data_In(3) => Port3_in(5),
1411	Data_In(4) => Port4_in(5),
1412	Data_In(5) => Port5_in(5),
1413	Data_In(6) => Port6_in(5),
1414	Data_In(7) => Port7_in(5),
1415	Data_In(8) => Port8_in(5),
1416	Data_out(1)=> Port1_out(5),
1417	Data_out(2)=> Port2_out(5),
1418	Data_out(3)=> Port3_out(5),
1419	Data_out(4)=> Port4_out(5),
1420	Data_out(5)=> Port5_out(5),
1421	Data_out(6)=> Port6_out(5),
1422	Data_out(7)=> Port7_out(5),
1423	Data_out(8)=> Port8_out(5)
1424
1425	);
1426	-- crossbit du bit 6 de donnée
1427
1428	Data6_Crossbit: Crossbit
1429	GENERIC MAP(number_of_ports => 8)
1430	PORT MAP(
1431	clk =>clk,
1432	reset =>reset,
1433
1434	Control => Ctrl_buf,
1435	Data_In(1) => Port1_in(6),
1436	Data_In(2) => Port2_in(6),
1437	Data_In(3) => Port3_in(6),
1438	Data_In(4) => Port4_in(6),
1439	Data_In(5) => Port5_in(6),
1440	Data_In(6) => Port6_in(6),
1441	Data_In(7) => Port7_in(6),
1442	Data_In(8) => Port8_in(6),
1443	Data_out(1)=> Port1_out(6),
1444	Data_out(2)=> Port2_out(6),
1445	Data_out(3)=> Port3_out(6),
1446	Data_out(4)=> Port4_out(6),
1447	Data_out(5)=> Port5_out(6),
1448	Data_out(6)=> Port6_out(6),
1449	Data_out(7)=> Port7_out(6),
1450	Data_out(8)=> Port8_out(6)
1451
1452	);
1453	-- crossbit du bit 7 de donnée
1454
1455	Data7_Crossbit: Crossbit
1456	GENERIC MAP(number_of_ports => 8)
1457	PORT MAP(
1458	clk =>clk,
1459	reset =>reset,
1460
1461	Control => Ctrl_buf,
1462	Data_In(1) => Port1_in(7),
1463	Data_In(2) => Port2_in(7),
1464	Data_In(3) => Port3_in(7),
1465	Data_In(4) => Port4_in(7),
1466	Data_In(5) => Port5_in(7),
1467	Data_In(6) => Port6_in(7),
1468	Data_In(7) => Port7_in(7),
1469	Data_In(8) => Port8_in(7),
1470	Data_out(1)=> Port1_out(7),
1471	Data_out(2)=> Port2_out(7),
1472	Data_out(3)=> Port3_out(7),
1473	Data_out(4)=> Port4_out(7),
1474	Data_out(5)=> Port5_out(7),
1475	Data_out(6)=> Port6_out(7),
1476	Data_out(7)=> Port7_out(7),
1477	Data_out(8)=> Port8_out(7)
1478
1479	);
1480	-- crossbit du pulse_out 8 ports
1481
1482	Pulse_out_Crossbit8: Crossbit
1483	GENERIC MAP(number_of_ports => 8)
1484	PORT MAP(
1485	clk =>clk,
1486	reset =>reset,
1487
1488	Control => Ctrl_buf,
1489	Data_In(1) => Port1_pulse_in,
1490	Data_In(2) => Port2_pulse_in,
1491	Data_In(3) => Port3_pulse_in,
1492	Data_In(4) => Port4_pulse_in,
1493	Data_In(5) => Port5_pulse_in,
1494	Data_In(6) => Port6_pulse_in,
1495	Data_In(7) => Port7_pulse_in,
1496	Data_In(8) => Port8_pulse_in,
1497	Data_out(1) => Port1_pulse_out,
1498	Data_out(2) => Port2_pulse_out,
1499	Data_out(3) => Port3_pulse_out,
1500	Data_out(4) => Port4_pulse_out,
1501	Data_out(5) => Port5_pulse_out,
1502	Data_out(6) => Port6_pulse_out,
1503	Data_out(7) => Port7_pulse_out,
1504	Data_out(8) => Port8_pulse_out
1505
1506	);
1507	end generate crossbar8x8;
1508
1509
1510	--======================crossbar 9 ports=======================
1511
1512	crossbar9x9 : if number_of_crossbar_ports = 9 generate
1513
1514	-- crossbit du bit 0 de donnée
1515
1516	Data0_Crossbit: Crossbit
1517	GENERIC MAP(number_of_ports => 9)
1518	PORT MAP(
1519	clk =>clk,
1520	reset =>reset,
1521
1522	Control => Ctrl_buf,
1523	Data_In(1) => Port1_in(0),
1524	Data_In(2) => Port2_in(0),
1525	Data_In(3) => Port3_in(0),
1526	Data_In(4) => Port4_in(0),
1527	Data_In(5) => Port5_in(0),
1528	Data_In(6) => Port6_in(0),
1529	Data_In(7) => Port7_in(0),
1530	Data_In(8) => Port8_in(0),
1531	Data_In(9) => Port9_in(0),
1532	Data_out(1)=> Port1_out(0),
1533	Data_out(2)=> Port2_out(0),
1534	Data_out(3)=> Port3_out(0),
1535	Data_out(4)=> Port4_out(0),
1536	Data_out(5)=> Port5_out(0),
1537	Data_out(6)=> Port6_out(0),
1538	Data_out(7)=> Port7_out(0),
1539	Data_out(8)=> Port8_out(0),
1540	Data_out(9)=> Port9_out(0)
1541
1542	);
1543	-- crossbit du bit 1 de donnée
1544
1545	Data1_Crossbit: Crossbit
1546	GENERIC MAP(number_of_ports => 9)
1547	PORT MAP(
1548	clk =>clk,
1549	reset =>reset,
1550
1551	Control => Ctrl_buf,
1552	Data_In(1) => Port1_in(1),
1553	Data_In(2) => Port2_in(1),
1554	Data_In(3) => Port3_in(1),
1555	Data_In(4) => Port4_in(1),
1556	Data_In(5) => Port5_in(1),
1557	Data_In(6) => Port6_in(1),
1558	Data_In(7) => Port7_in(1),
1559	Data_In(8) => Port8_in(1),
1560	Data_In(9) => Port9_in(1),
1561	Data_out(1)=> Port1_out(1),
1562	Data_out(2)=> Port2_out(1),
1563	Data_out(3)=> Port3_out(1),
1564	Data_out(4)=> Port4_out(1),
1565	Data_out(5)=> Port5_out(1),
1566	Data_out(6)=> Port6_out(1),
1567	Data_out(7)=> Port7_out(1),
1568	Data_out(8)=> Port8_out(1),
1569	Data_out(9)=> Port9_out(1)
1570
1571	);
1572	-- crossbit du bit 2 de donnée
1573
1574	Data2_Crossbit: Crossbit
1575	GENERIC MAP(number_of_ports => 9)
1576	PORT MAP(
1577	clk =>clk,
1578	reset =>reset,
1579
1580	Control => Ctrl_buf,
1581	Data_In(1) => Port1_in(2),
1582	Data_In(2) => Port2_in(2),
1583	Data_In(3) => Port3_in(2),
1584	Data_In(4) => Port4_in(2),
1585	Data_In(5) => Port5_in(2),
1586	Data_In(6) => Port6_in(2),
1587	Data_In(7) => Port7_in(2),
1588	Data_In(8) => Port8_in(2),
1589	Data_In(9) => Port9_in(2),
1590	Data_out(1)=> Port1_out(2),
1591	Data_out(2)=> Port2_out(2),
1592	Data_out(3)=> Port3_out(2),
1593	Data_out(4)=> Port4_out(2),
1594	Data_out(5)=> Port5_out(2),
1595	Data_out(6)=> Port6_out(2),
1596	Data_out(7)=> Port7_out(2),
1597	Data_out(8)=> Port8_out(2),
1598	Data_out(9)=> Port9_out(2)
1599
1600	);
1601	-- crossbit du bit 3 de donnée
1602
1603	Data3_Crossbit: Crossbit
1604	GENERIC MAP(number_of_ports => 9)
1605	PORT MAP(
1606	clk =>clk,
1607	reset =>reset,
1608
1609	Control => Ctrl_buf,
1610	Data_In(1) => Port1_in(3),
1611	Data_In(2) => Port2_in(3),
1612	Data_In(3) => Port3_in(3),
1613	Data_In(4) => Port4_in(3),
1614	Data_In(5) => Port5_in(3),
1615	Data_In(6) => Port6_in(3),
1616	Data_In(7) => Port7_in(3),
1617	Data_In(8) => Port8_in(3),
1618	Data_In(9) => Port9_in(3),
1619	Data_out(1)=> Port1_out(3),
1620	Data_out(2)=> Port2_out(3),
1621	Data_out(3)=> Port3_out(3),
1622	Data_out(4)=> Port4_out(3),
1623	Data_out(5)=> Port5_out(3),
1624	Data_out(6)=> Port6_out(3),
1625	Data_out(7)=> Port7_out(3),
1626	Data_out(8)=> Port8_out(3),
1627	Data_out(9)=> Port9_out(3)
1628
1629	);
1630	-- crossbit du bit 4 de donnée
1631
1632	Data4_Crossbit: Crossbit
1633	GENERIC MAP(number_of_ports => 9)
1634	PORT MAP(
1635	clk =>clk,
1636	reset =>reset,
1637
1638	Control => Ctrl_buf,
1639	Data_In(1) => Port1_in(4),
1640	Data_In(2) => Port2_in(4),
1641	Data_In(3) => Port3_in(4),
1642	Data_In(4) => Port4_in(4),
1643	Data_In(5) => Port5_in(4),
1644	Data_In(6) => Port6_in(4),
1645	Data_In(7) => Port7_in(4),
1646	Data_In(8) => Port8_in(4),
1647	Data_In(9) => Port9_in(4),
1648	Data_out(1)=> Port1_out(4),
1649	Data_out(2)=> Port2_out(4),
1650	Data_out(3)=> Port3_out(4),
1651	Data_out(4)=> Port4_out(4),
1652	Data_out(5)=> Port5_out(4),
1653	Data_out(6)=> Port6_out(4),
1654	Data_out(7)=> Port7_out(4),
1655	Data_out(8)=> Port8_out(4),
1656	Data_out(9)=> Port9_out(4)
1657
1658	);
1659	-- crossbit du bit 5 de donnée
1660
1661	Data5_Crossbit: Crossbit
1662	GENERIC MAP(number_of_ports => 9)
1663	PORT MAP(
1664	clk =>clk,
1665	reset =>reset,
1666
1667	Control => Ctrl_buf,
1668	Data_In(1) => Port1_in(5),
1669	Data_In(2) => Port2_in(5),
1670	Data_In(3) => Port3_in(5),
1671	Data_In(4) => Port4_in(5),
1672	Data_In(5) => Port5_in(5),
1673	Data_In(6) => Port6_in(5),
1674	Data_In(7) => Port7_in(5),
1675	Data_In(8) => Port8_in(5),
1676	Data_In(9) => Port9_in(5),
1677	Data_out(1)=> Port1_out(5),
1678	Data_out(2)=> Port2_out(5),
1679	Data_out(3)=> Port3_out(5),
1680	Data_out(4)=> Port4_out(5),
1681	Data_out(5)=> Port5_out(5),
1682	Data_out(6)=> Port6_out(5),
1683	Data_out(7)=> Port7_out(5),
1684	Data_out(8)=> Port8_out(5),
1685	Data_out(9)=> Port9_out(5)
1686
1687	);
1688	-- crossbit du bit 6 de donnée
1689
1690	Data6_Crossbit: Crossbit
1691	GENERIC MAP(number_of_ports => 9)
1692	PORT MAP(
1693	clk =>clk,
1694	reset =>reset,
1695
1696	Control => Ctrl_buf,
1697	Data_In(1) => Port1_in(6),
1698	Data_In(2) => Port2_in(6),
1699	Data_In(3) => Port3_in(6),
1700	Data_In(4) => Port4_in(6),
1701	Data_In(5) => Port5_in(6),
1702	Data_In(6) => Port6_in(6),
1703	Data_In(7) => Port7_in(6),
1704	Data_In(8) => Port8_in(6),
1705	Data_In(9) => Port9_in(6),
1706	Data_out(1)=> Port1_out(6),
1707	Data_out(2)=> Port2_out(6),
1708	Data_out(3)=> Port3_out(6),
1709	Data_out(4)=> Port4_out(6),
1710	Data_out(5)=> Port5_out(6),
1711	Data_out(6)=> Port6_out(6),
1712	Data_out(7)=> Port7_out(6),
1713	Data_out(8)=> Port8_out(6),
1714	Data_out(9)=> Port9_out(6)
1715
1716	);
1717	-- crossbit du bit 7 de donnée
1718
1719	Data7_Crossbit: Crossbit
1720	GENERIC MAP(number_of_ports => 9)
1721	PORT MAP(
1722	clk =>clk,
1723	reset =>reset,
1724
1725	Control => Ctrl_buf,
1726	Data_In(1) => Port1_in(7),
1727	Data_In(2) => Port2_in(7),
1728	Data_In(3) => Port3_in(7),
1729	Data_In(4) => Port4_in(7),
1730	Data_In(5) => Port5_in(7),
1731	Data_In(6) => Port6_in(7),
1732	Data_In(7) => Port7_in(7),
1733	Data_In(8) => Port8_in(7),
1734	Data_In(9) => Port9_in(7),
1735	Data_out(1)=> Port1_out(7),
1736	Data_out(2)=> Port2_out(7),
1737	Data_out(3)=> Port3_out(7),
1738	Data_out(4)=> Port4_out(7),
1739	Data_out(5)=> Port5_out(7),
1740	Data_out(6)=> Port6_out(7),
1741	Data_out(7)=> Port7_out(7),
1742	Data_out(8)=> Port8_out(7),
1743	Data_out(9)=> Port9_out(7)
1744
1745	);
1746	-- crossbit du pulse_out 9 ports
1747
1748	Pulse_out_Crossbit9: Crossbit
1749	GENERIC MAP(number_of_ports => 9)
1750	PORT MAP(
1751	clk =>clk,
1752	reset =>reset,
1753
1754	Control => Ctrl_buf,
1755	Data_In(1) => Port1_pulse_in,
1756	Data_In(2) => Port2_pulse_in,
1757	Data_In(3) => Port3_pulse_in,
1758	Data_In(4) => Port4_pulse_in,
1759	Data_In(5) => Port5_pulse_in,
1760	Data_In(6) => Port6_pulse_in,
1761	Data_In(7) => Port7_pulse_in,
1762	Data_In(8) => Port8_pulse_in,
1763	Data_In(9) => Port9_pulse_in,
1764	Data_out(1) => Port1_pulse_out,
1765	Data_out(2) => Port2_pulse_out,
1766	Data_out(3) => Port3_pulse_out,
1767	Data_out(4) => Port4_pulse_out,
1768	Data_out(5) => Port5_pulse_out,
1769	Data_out(6) => Port6_pulse_out,
1770	Data_out(7) => Port7_pulse_out,
1771	Data_out(8) => Port8_pulse_out,
1772	Data_out(9) => Port9_pulse_out
1773
1774	);
1775	end generate crossbar9x9;
1776
1777
1778	--======================crossbar 10 ports=======================
1779
1780	crossbar10x10 : if number_of_crossbar_ports = 10 generate
1781
1782	-- crossbit du bit 0 de donnée
1783
1784	Data0_Crossbit: Crossbit
1785	GENERIC MAP(number_of_ports => 10)
1786	PORT MAP(
1787
1788	reset => reset,
1789	clk=>clk,
1790	Control => Ctrl_buf,
1791	Data_In(1) => Port1_in(0),
1792	Data_In(2) => Port2_in(0),
1793	Data_In(3) => Port3_in(0),
1794	Data_In(4) => Port4_in(0),
1795	Data_In(5) => Port5_in(0),
1796	Data_In(6) => Port6_in(0),
1797	Data_In(7) => Port7_in(0),
1798	Data_In(8) => Port8_in(0),
1799	Data_In(9) => Port9_in(0),
1800	Data_In(10) => Port10_in(0),
1801	Data_out(1)=> Port1_out(0),
1802	Data_out(2)=> Port2_out(0),
1803	Data_out(3)=> Port3_out(0),
1804	Data_out(4)=> Port4_out(0),
1805	Data_out(5)=> Port5_out(0),
1806	Data_out(6)=> Port6_out(0),
1807	Data_out(7)=> Port7_out(0),
1808	Data_out(8)=> Port8_out(0),
1809	Data_out(9)=> Port9_out(0),
1810	Data_out(10)=> Port10_out(0)
1811
1812	);
1813	-- crossbit du bit 1 de donnée
1814
1815	Data1_Crossbit: Crossbit
1816	GENERIC MAP(number_of_ports => 10)
1817	PORT MAP(
1818
1819	reset => reset,
1820	clk=>clk,
1821	Control => Ctrl_buf,
1822	Data_In(1) => Port1_in(1),
1823	Data_In(2) => Port2_in(1),
1824	Data_In(3) => Port3_in(1),
1825	Data_In(4) => Port4_in(1),
1826	Data_In(5) => Port5_in(1),
1827	Data_In(6) => Port6_in(1),
1828	Data_In(7) => Port7_in(1),
1829	Data_In(8) => Port8_in(1),
1830	Data_In(9) => Port9_in(1),
1831	Data_In(10) => Port10_in(1),
1832	Data_out(1)=> Port1_out(1),
1833	Data_out(2)=> Port2_out(1),
1834	Data_out(3)=> Port3_out(1),
1835	Data_out(4)=> Port4_out(1),
1836	Data_out(5)=> Port5_out(1),
1837	Data_out(6)=> Port6_out(1),
1838	Data_out(7)=> Port7_out(1),
1839	Data_out(8)=> Port8_out(1),
1840	Data_out(9)=> Port9_out(1),
1841	Data_out(10)=> Port10_out(1)
1842
1843	);
1844	-- crossbit du bit 2 de donnée
1845
1846	Data2_Crossbit: Crossbit
1847	GENERIC MAP(number_of_ports => 10)
1848	PORT MAP(
1849
1850	reset => reset,
1851	clk=>clk,
1852	Control => Ctrl_buf,
1853	Data_In(1) => Port1_in(2),
1854	Data_In(2) => Port2_in(2),
1855	Data_In(3) => Port3_in(2),
1856	Data_In(4) => Port4_in(2),
1857	Data_In(5) => Port5_in(2),
1858	Data_In(6) => Port6_in(2),
1859	Data_In(7) => Port7_in(2),
1860	Data_In(8) => Port8_in(2),
1861	Data_In(9) => Port9_in(2),
1862	Data_In(10) => Port10_in(2),
1863	Data_out(1)=> Port1_out(2),
1864	Data_out(2)=> Port2_out(2),
1865	Data_out(3)=> Port3_out(2),
1866	Data_out(4)=> Port4_out(2),
1867	Data_out(5)=> Port5_out(2),
1868	Data_out(6)=> Port6_out(2),
1869	Data_out(7)=> Port7_out(2),
1870	Data_out(8)=> Port8_out(2),
1871	Data_out(9)=> Port9_out(2),
1872	Data_out(10)=> Port10_out(2)
1873
1874	);
1875	-- crossbit du bit 3 de donnée
1876
1877	Data3_Crossbit: Crossbit
1878	GENERIC MAP(number_of_ports => 10)
1879	PORT MAP(
1880
1881	reset => reset,
1882	clk=>clk,
1883	Control => Ctrl_buf,
1884	Data_In(1) => Port1_in(3),
1885	Data_In(2) => Port2_in(3),
1886	Data_In(3) => Port3_in(3),
1887	Data_In(4) => Port4_in(3),
1888	Data_In(5) => Port5_in(3),
1889	Data_In(6) => Port6_in(3),
1890	Data_In(7) => Port7_in(3),
1891	Data_In(8) => Port8_in(3),
1892	Data_In(9) => Port9_in(3),
1893	Data_In(10) => Port10_in(3),
1894	Data_out(1)=> Port1_out(3),
1895	Data_out(2)=> Port2_out(3),
1896	Data_out(3)=> Port3_out(3),
1897	Data_out(4)=> Port4_out(3),
1898	Data_out(5)=> Port5_out(3),
1899	Data_out(6)=> Port6_out(3),
1900	Data_out(7)=> Port7_out(3),
1901	Data_out(8)=> Port8_out(3),
1902	Data_out(9)=> Port9_out(3),
1903	Data_out(10)=> Port10_out(3)
1904
1905	);
1906	-- crossbit du bit 4 de donnée
1907
1908	Data4_Crossbit: Crossbit
1909	GENERIC MAP(number_of_ports => 10)
1910	PORT MAP(
1911
1912	reset => reset,
1913	clk=>clk,
1914	Control => Ctrl_buf,
1915	Data_In(1) => Port1_in(4),
1916	Data_In(2) => Port2_in(4),
1917	Data_In(3) => Port3_in(4),
1918	Data_In(4) => Port4_in(4),
1919	Data_In(5) => Port5_in(4),
1920	Data_In(6) => Port6_in(4),
1921	Data_In(7) => Port7_in(4),
1922	Data_In(8) => Port8_in(4),
1923	Data_In(9) => Port9_in(4),
1924	Data_In(10) => Port10_in(4),
1925	Data_out(1)=> Port1_out(4),
1926	Data_out(2)=> Port2_out(4),
1927	Data_out(3)=> Port3_out(4),
1928	Data_out(4)=> Port4_out(4),
1929	Data_out(5)=> Port5_out(4),
1930	Data_out(6)=> Port6_out(4),
1931	Data_out(7)=> Port7_out(4),
1932	Data_out(8)=> Port8_out(4),
1933	Data_out(9)=> Port9_out(4),
1934	Data_out(10)=> Port10_out(4)
1935
1936	);
1937	-- crossbit du bit 5 de donnée
1938
1939	Data5_Crossbit: Crossbit
1940	GENERIC MAP(number_of_ports => 10)
1941	PORT MAP(
1942
1943	reset => reset,
1944	clk=>clk,
1945	Control => Ctrl_buf,
1946	Data_In(1) => Port1_in(5),
1947	Data_In(2) => Port2_in(5),
1948	Data_In(3) => Port3_in(5),
1949	Data_In(4) => Port4_in(5),
1950	Data_In(5) => Port5_in(5),
1951	Data_In(6) => Port6_in(5),
1952	Data_In(7) => Port7_in(5),
1953	Data_In(8) => Port8_in(5),
1954	Data_In(9) => Port9_in(5),
1955	Data_In(10) => Port10_in(5),
1956	Data_out(1)=> Port1_out(5),
1957	Data_out(2)=> Port2_out(5),
1958	Data_out(3)=> Port3_out(5),
1959	Data_out(4)=> Port4_out(5),
1960	Data_out(5)=> Port5_out(5),
1961	Data_out(6)=> Port6_out(5),
1962	Data_out(7)=> Port7_out(5),
1963	Data_out(8)=> Port8_out(5),
1964	Data_out(9)=> Port9_out(5),
1965	Data_out(10)=> Port10_out(5)
1966
1967	);
1968	-- crossbit du bit 6 de donnée
1969
1970	Data6_Crossbit: Crossbit
1971	GENERIC MAP(number_of_ports => 10)
1972	PORT MAP(
1973
1974	reset => reset,
1975	clk=>clk,
1976	Control => Ctrl_buf,
1977	Data_In(1) => Port1_in(6),
1978	Data_In(2) => Port2_in(6),
1979	Data_In(3) => Port3_in(6),
1980	Data_In(4) => Port4_in(6),
1981	Data_In(5) => Port5_in(6),
1982	Data_In(6) => Port6_in(6),
1983	Data_In(7) => Port7_in(6),
1984	Data_In(8) => Port8_in(6),
1985	Data_In(9) => Port9_in(6),
1986	Data_In(10) => Port10_in(6),
1987	Data_out(1)=> Port1_out(6),
1988	Data_out(2)=> Port2_out(6),
1989	Data_out(3)=> Port3_out(6),
1990	Data_out(4)=> Port4_out(6),
1991	Data_out(5)=> Port5_out(6),
1992	Data_out(6)=> Port6_out(6),
1993	Data_out(7)=> Port7_out(6),
1994	Data_out(8)=> Port8_out(6),
1995	Data_out(9)=> Port9_out(6),
1996	Data_out(10)=> Port10_out(6)
1997
1998	);
1999	-- crossbit du bit 7 de donnée
2000
2001	Data7_Crossbit: Crossbit
2002	GENERIC MAP(number_of_ports => 10)
2003	PORT MAP(
2004
2005	reset => reset,
2006	clk=>clk,
2007	Control => Ctrl_buf,
2008	Data_In(1) => Port1_in(7),
2009	Data_In(2) => Port2_in(7),
2010	Data_In(3) => Port3_in(7),
2011	Data_In(4) => Port4_in(7),
2012	Data_In(5) => Port5_in(7),
2013	Data_In(6) => Port6_in(7),
2014	Data_In(7) => Port7_in(7),
2015	Data_In(8) => Port8_in(7),
2016	Data_In(9) => Port9_in(7),
2017	Data_In(10) => Port10_in(7),
2018	Data_out(1)=> Port1_out(7),
2019	Data_out(2)=> Port2_out(7),
2020	Data_out(3)=> Port3_out(7),
2021	Data_out(4)=> Port4_out(7),
2022	Data_out(5)=> Port5_out(7),
2023	Data_out(6)=> Port6_out(7),
2024	Data_out(7)=> Port7_out(7),
2025	Data_out(8)=> Port8_out(7),
2026	Data_out(9)=> Port9_out(7),
2027	Data_out(10)=> Port10_out(7)
2028
2029	);
2030	-- crossbit du pulse_out 10 ports
2031
2032	Pulse_out_Crossbit10: Crossbit
2033	GENERIC MAP(number_of_ports => 10)
2034	PORT MAP(
2035
2036	reset => reset,
2037	clk=>clk,
2038	Control => Ctrl_buf,
2039	Data_In(1) => Port1_pulse_in,
2040	Data_In(2) => Port2_pulse_in,
2041	Data_In(3) => Port3_pulse_in,
2042	Data_In(4) => Port4_pulse_in,
2043	Data_In(5) => Port5_pulse_in,
2044	Data_In(6) => Port6_pulse_in,
2045	Data_In(7) => Port7_pulse_in,
2046	Data_In(8) => Port8_pulse_in,
2047	Data_In(9) => Port9_pulse_in,
2048	Data_In(10) => Port10_pulse_in,
2049	Data_out(1) => Port1_pulse_out,
2050	Data_out(2) => Port2_pulse_out,
2051	Data_out(3) => Port3_pulse_out,
2052	Data_out(4) => Port4_pulse_out,
2053	Data_out(5) => Port5_pulse_out,
2054	Data_out(6) => Port6_pulse_out,
2055	Data_out(7) => Port7_pulse_out,
2056	Data_out(8) => Port8_pulse_out,
2057	Data_out(9) => Port9_pulse_out,
2058	Data_out(10) => Port10_pulse_out
2059
2060	);
2061	end generate crossbar10x10;
2062
2063
2064	--======================crossbar 11 ports=======================
2065
2066	crossbar11x11 : if number_of_crossbar_ports = 11 generate
2067
2068	-- crossbit du bit 0 de donnée
2069
2070	Data0_Crossbit: Crossbit
2071	GENERIC MAP(number_of_ports => 11)
2072	PORT MAP(
2073
2074	reset => reset,
2075	clk=>clk,
2076	Control => Ctrl_buf,
2077	Data_In(1) => Port1_in(0),
2078	Data_In(2) => Port2_in(0),
2079	Data_In(3) => Port3_in(0),
2080	Data_In(4) => Port4_in(0),
2081	Data_In(5) => Port5_in(0),
2082	Data_In(6) => Port6_in(0),
2083	Data_In(7) => Port7_in(0),
2084	Data_In(8) => Port8_in(0),
2085	Data_In(9) => Port9_in(0),
2086	Data_In(10) => Port10_in(0),
2087	Data_In(11) => Port11_in(0),
2088	Data_out(1)=> Port1_out(0),
2089	Data_out(2)=> Port2_out(0),
2090	Data_out(3)=> Port3_out(0),
2091	Data_out(4)=> Port4_out(0),
2092	Data_out(5)=> Port5_out(0),
2093	Data_out(6)=> Port6_out(0),
2094	Data_out(7)=> Port7_out(0),
2095	Data_out(8)=> Port8_out(0),
2096	Data_out(9)=> Port9_out(0),
2097	Data_out(10)=> Port10_out(0),
2098	Data_out(11)=> Port11_out(0)
2099
2100	);
2101	-- crossbit du bit 1 de donnée
2102
2103	Data1_Crossbit: Crossbit
2104	GENERIC MAP(number_of_ports => 11)
2105	PORT MAP(
2106
2107	reset => reset,
2108	clk=>clk,
2109	Control => Ctrl_buf,
2110	Data_In(1) => Port1_in(1),
2111	Data_In(2) => Port2_in(1),
2112	Data_In(3) => Port3_in(1),
2113	Data_In(4) => Port4_in(1),
2114	Data_In(5) => Port5_in(1),
2115	Data_In(6) => Port6_in(1),
2116	Data_In(7) => Port7_in(1),
2117	Data_In(8) => Port8_in(1),
2118	Data_In(9) => Port9_in(1),
2119	Data_In(10) => Port10_in(1),
2120	Data_In(11) => Port11_in(1),
2121	Data_out(1)=> Port1_out(1),
2122	Data_out(2)=> Port2_out(1),
2123	Data_out(3)=> Port3_out(1),
2124	Data_out(4)=> Port4_out(1),
2125	Data_out(5)=> Port5_out(1),
2126	Data_out(6)=> Port6_out(1),
2127	Data_out(7)=> Port7_out(1),
2128	Data_out(8)=> Port8_out(1),
2129	Data_out(9)=> Port9_out(1),
2130	Data_out(10)=> Port10_out(1),
2131	Data_out(11)=> Port11_out(1)
2132
2133	);
2134	-- crossbit du bit 2 de donnée
2135
2136	Data2_Crossbit: Crossbit
2137	GENERIC MAP(number_of_ports => 11)
2138	PORT MAP(
2139
2140	reset => reset,
2141	clk=>clk,
2142	Control => Ctrl_buf,
2143	Data_In(1) => Port1_in(2),
2144	Data_In(2) => Port2_in(2),
2145	Data_In(3) => Port3_in(2),
2146	Data_In(4) => Port4_in(2),
2147	Data_In(5) => Port5_in(2),
2148	Data_In(6) => Port6_in(2),
2149	Data_In(7) => Port7_in(2),
2150	Data_In(8) => Port8_in(2),
2151	Data_In(9) => Port9_in(2),
2152	Data_In(10) => Port10_in(2),
2153	Data_In(11) => Port11_in(2),
2154	Data_out(1)=> Port1_out(2),
2155	Data_out(2)=> Port2_out(2),
2156	Data_out(3)=> Port3_out(2),
2157	Data_out(4)=> Port4_out(2),
2158	Data_out(5)=> Port5_out(2),
2159	Data_out(6)=> Port6_out(2),
2160	Data_out(7)=> Port7_out(2),
2161	Data_out(8)=> Port8_out(2),
2162	Data_out(9)=> Port9_out(2),
2163	Data_out(10)=> Port10_out(2),
2164	Data_out(11)=> Port11_out(2)
2165
2166	);
2167	-- crossbit du bit 3 de donnée
2168
2169	Data3_Crossbit: Crossbit
2170	GENERIC MAP(number_of_ports => 11)
2171	PORT MAP(
2172
2173	reset => reset,
2174	clk=>clk,
2175
2176	Control => Ctrl_buf,
2177	Data_In(1) => Port1_in(3),
2178	Data_In(2) => Port2_in(3),
2179	Data_In(3) => Port3_in(3),
2180	Data_In(4) => Port4_in(3),
2181	Data_In(5) => Port5_in(3),
2182	Data_In(6) => Port6_in(3),
2183	Data_In(7) => Port7_in(3),
2184	Data_In(8) => Port8_in(3),
2185	Data_In(9) => Port9_in(3),
2186	Data_In(10) => Port10_in(3),
2187	Data_In(11) => Port11_in(3),
2188	Data_out(1)=> Port1_out(3),
2189	Data_out(2)=> Port2_out(3),
2190	Data_out(3)=> Port3_out(3),
2191	Data_out(4)=> Port4_out(3),
2192	Data_out(5)=> Port5_out(3),
2193	Data_out(6)=> Port6_out(3),
2194	Data_out(7)=> Port7_out(3),
2195	Data_out(8)=> Port8_out(3),
2196	Data_out(9)=> Port9_out(3),
2197	Data_out(10)=> Port10_out(3),
2198	Data_out(11)=> Port11_out(3)
2199
2200	);
2201	-- crossbit du bit 4 de donnée
2202
2203	Data4_Crossbit: Crossbit
2204	GENERIC MAP(number_of_ports => 11)
2205	PORT MAP(
2206
2207	reset => reset,
2208	clk=>clk,
2209	Control => Ctrl_buf,
2210	Data_In(1) => Port1_in(4),
2211	Data_In(2) => Port2_in(4),
2212	Data_In(3) => Port3_in(4),
2213	Data_In(4) => Port4_in(4),
2214	Data_In(5) => Port5_in(4),
2215	Data_In(6) => Port6_in(4),
2216	Data_In(7) => Port7_in(4),
2217	Data_In(8) => Port8_in(4),
2218	Data_In(9) => Port9_in(4),
2219	Data_In(10) => Port10_in(4),
2220	Data_In(11) => Port11_in(4),
2221	Data_out(1)=> Port1_out(4),
2222	Data_out(2)=> Port2_out(4),
2223	Data_out(3)=> Port3_out(4),
2224	Data_out(4)=> Port4_out(4),
2225	Data_out(5)=> Port5_out(4),
2226	Data_out(6)=> Port6_out(4),
2227	Data_out(7)=> Port7_out(4),
2228	Data_out(8)=> Port8_out(4),
2229	Data_out(9)=> Port9_out(4),
2230	Data_out(10)=> Port10_out(4),
2231	Data_out(11)=> Port11_out(4)
2232
2233	);
2234	-- crossbit du bit 5 de donnée
2235
2236	Data5_Crossbit: Crossbit
2237	GENERIC MAP(number_of_ports => 11)
2238	PORT MAP(
2239
2240	reset => reset,
2241	clk=>clk,
2242
2243	Control => Ctrl_buf,
2244	Data_In(1) => Port1_in(5),
2245	Data_In(2) => Port2_in(5),
2246	Data_In(3) => Port3_in(5),
2247	Data_In(4) => Port4_in(5),
2248	Data_In(5) => Port5_in(5),
2249	Data_In(6) => Port6_in(5),
2250	Data_In(7) => Port7_in(5),
2251	Data_In(8) => Port8_in(5),
2252	Data_In(9) => Port9_in(5),
2253	Data_In(10) => Port10_in(5),
2254	Data_In(11) => Port11_in(5),
2255	Data_out(1)=> Port1_out(5),
2256	Data_out(2)=> Port2_out(5),
2257	Data_out(3)=> Port3_out(5),
2258	Data_out(4)=> Port4_out(5),
2259	Data_out(5)=> Port5_out(5),
2260	Data_out(6)=> Port6_out(5),
2261	Data_out(7)=> Port7_out(5),
2262	Data_out(8)=> Port8_out(5),
2263	Data_out(9)=> Port9_out(5),
2264	Data_out(10)=> Port10_out(5),
2265	Data_out(11)=> Port11_out(5)
2266
2267	);
2268	-- crossbit du bit 6 de donnée
2269
2270	Data6_Crossbit: Crossbit
2271	GENERIC MAP(number_of_ports => 11)
2272	PORT MAP(
2273
2274	reset => reset,
2275	clk=>clk,
2276
2277	Control => Ctrl_buf,
2278	Data_In(1) => Port1_in(6),
2279	Data_In(2) => Port2_in(6),
2280	Data_In(3) => Port3_in(6),
2281	Data_In(4) => Port4_in(6),
2282	Data_In(5) => Port5_in(6),
2283	Data_In(6) => Port6_in(6),
2284	Data_In(7) => Port7_in(6),
2285	Data_In(8) => Port8_in(6),
2286	Data_In(9) => Port9_in(6),
2287	Data_In(10) => Port10_in(6),
2288	Data_In(11) => Port11_in(6),
2289	Data_out(1)=> Port1_out(6),
2290	Data_out(2)=> Port2_out(6),
2291	Data_out(3)=> Port3_out(6),
2292	Data_out(4)=> Port4_out(6),
2293	Data_out(5)=> Port5_out(6),
2294	Data_out(6)=> Port6_out(6),
2295	Data_out(7)=> Port7_out(6),
2296	Data_out(8)=> Port8_out(6),
2297	Data_out(9)=> Port9_out(6),
2298	Data_out(10)=> Port10_out(6),
2299	Data_out(11)=> Port11_out(6)
2300
2301	);
2302	-- crossbit du bit 7 de donnée
2303
2304	Data7_Crossbit: Crossbit
2305	GENERIC MAP(number_of_ports => 11)
2306	PORT MAP(
2307
2308	reset => reset,
2309	clk=>clk,
2310
2311	Control => Ctrl_buf,
2312	Data_In(1) => Port1_in(7),
2313	Data_In(2) => Port2_in(7),
2314	Data_In(3) => Port3_in(7),
2315	Data_In(4) => Port4_in(7),
2316	Data_In(5) => Port5_in(7),
2317	Data_In(6) => Port6_in(7),
2318	Data_In(7) => Port7_in(7),
2319	Data_In(8) => Port8_in(7),
2320	Data_In(9) => Port9_in(7),
2321	Data_In(10) => Port10_in(7),
2322	Data_In(11) => Port11_in(7),
2323	Data_out(1)=> Port1_out(7),
2324	Data_out(2)=> Port2_out(7),
2325	Data_out(3)=> Port3_out(7),
2326	Data_out(4)=> Port4_out(7),
2327	Data_out(5)=> Port5_out(7),
2328	Data_out(6)=> Port6_out(7),
2329	Data_out(7)=> Port7_out(7),
2330	Data_out(8)=> Port8_out(7),
2331	Data_out(9)=> Port9_out(7),
2332	Data_out(10)=> Port10_out(7),
2333	Data_out(11)=> Port11_out(7)
2334
2335	);
2336	-- crossbit du pulse_out 11 ports
2337
2338	Pulse_out_Crossbit11: Crossbit
2339	GENERIC MAP(number_of_ports => 11)
2340	PORT MAP(
2341
2342	reset => reset,
2343	clk=>clk,
2344
2345	Control => Ctrl_buf,
2346	Data_In(1) => Port1_pulse_in,
2347	Data_In(2) => Port2_pulse_in,
2348	Data_In(3) => Port3_pulse_in,
2349	Data_In(4) => Port4_pulse_in,
2350	Data_In(5) => Port5_pulse_in,
2351	Data_In(6) => Port6_pulse_in,
2352	Data_In(7) => Port7_pulse_in,
2353	Data_In(8) => Port8_pulse_in,
2354	Data_In(9) => Port9_pulse_in,
2355	Data_In(10) => Port10_pulse_in,
2356	Data_In(11) => Port11_pulse_in,
2357	Data_out(1) => Port1_pulse_out,
2358	Data_out(2) => Port2_pulse_out,
2359	Data_out(3) => Port3_pulse_out,
2360	Data_out(4) => Port4_pulse_out,
2361	Data_out(5) => Port5_pulse_out,
2362	Data_out(6) => Port6_pulse_out,
2363	Data_out(7) => Port7_pulse_out,
2364	Data_out(8) => Port8_pulse_out,
2365	Data_out(9) => Port9_pulse_out,
2366	Data_out(10) => Port10_pulse_out,
2367	Data_out(11) => Port11_pulse_out
2368
2369	);
2370	end generate crossbar11x11;
2371
2372
2373	--======================crossbar 12 ports=======================
2374
2375	crossbar12x12 : if number_of_crossbar_ports = 12 generate
2376
2377	-- crossbit du bit 0 de donnée
2378
2379	Data0_Crossbit: Crossbit
2380	GENERIC MAP(number_of_ports => 12)
2381	PORT MAP(
2382
2383	reset => reset,
2384	clk=>clk,
2385
2386	Control => Ctrl_buf,
2387	Data_In(1) => Port1_in(0),
2388	Data_In(2) => Port2_in(0),
2389	Data_In(3) => Port3_in(0),
2390	Data_In(4) => Port4_in(0),
2391	Data_In(5) => Port5_in(0),
2392	Data_In(6) => Port6_in(0),
2393	Data_In(7) => Port7_in(0),
2394	Data_In(8) => Port8_in(0),
2395	Data_In(9) => Port9_in(0),
2396	Data_In(10) => Port10_in(0),
2397	Data_In(11) => Port11_in(0),
2398	Data_In(12) => Port12_in(0),
2399	Data_out(1)=> Port1_out(0),
2400	Data_out(2)=> Port2_out(0),
2401	Data_out(3)=> Port3_out(0),
2402	Data_out(4)=> Port4_out(0),
2403	Data_out(5)=> Port5_out(0),
2404	Data_out(6)=> Port6_out(0),
2405	Data_out(7)=> Port7_out(0),
2406	Data_out(8)=> Port8_out(0),
2407	Data_out(9)=> Port9_out(0),
2408	Data_out(10)=> Port10_out(0),
2409	Data_out(11)=> Port11_out(0),
2410	Data_out(12)=> Port12_out(0)
2411
2412	);
2413	-- crossbit du bit 1 de donnée
2414
2415	Data1_Crossbit: Crossbit
2416	GENERIC MAP(number_of_ports => 12)
2417	PORT MAP(
2418
2419	reset => reset,
2420	clk=>clk,
2421
2422	Control => Ctrl_buf,
2423	Data_In(1) => Port1_in(1),
2424	Data_In(2) => Port2_in(1),
2425	Data_In(3) => Port3_in(1),
2426	Data_In(4) => Port4_in(1),
2427	Data_In(5) => Port5_in(1),
2428	Data_In(6) => Port6_in(1),
2429	Data_In(7) => Port7_in(1),
2430	Data_In(8) => Port8_in(1),
2431	Data_In(9) => Port9_in(1),
2432	Data_In(10) => Port10_in(1),
2433	Data_In(11) => Port11_in(1),
2434	Data_In(12) => Port12_in(1),
2435	Data_out(1)=> Port1_out(1),
2436	Data_out(2)=> Port2_out(1),
2437	Data_out(3)=> Port3_out(1),
2438	Data_out(4)=> Port4_out(1),
2439	Data_out(5)=> Port5_out(1),
2440	Data_out(6)=> Port6_out(1),
2441	Data_out(7)=> Port7_out(1),
2442	Data_out(8)=> Port8_out(1),
2443	Data_out(9)=> Port9_out(1),
2444	Data_out(10)=> Port10_out(1),
2445	Data_out(11)=> Port11_out(1),
2446	Data_out(12)=> Port12_out(1)
2447
2448	);
2449	-- crossbit du bit 2 de donnée
2450
2451	Data2_Crossbit: Crossbit
2452	GENERIC MAP(number_of_ports => 12)
2453	PORT MAP(
2454
2455	reset => reset,
2456	clk=>clk,
2457
2458	Control => Ctrl_buf,
2459	Data_In(1) => Port1_in(2),
2460	Data_In(2) => Port2_in(2),
2461	Data_In(3) => Port3_in(2),
2462	Data_In(4) => Port4_in(2),
2463	Data_In(5) => Port5_in(2),
2464	Data_In(6) => Port6_in(2),
2465	Data_In(7) => Port7_in(2),
2466	Data_In(8) => Port8_in(2),
2467	Data_In(9) => Port9_in(2),
2468	Data_In(10) => Port10_in(2),
2469	Data_In(11) => Port11_in(2),
2470	Data_In(12) => Port12_in(2),
2471	Data_out(1)=> Port1_out(2),
2472	Data_out(2)=> Port2_out(2),
2473	Data_out(3)=> Port3_out(2),
2474	Data_out(4)=> Port4_out(2),
2475	Data_out(5)=> Port5_out(2),
2476	Data_out(6)=> Port6_out(2),
2477	Data_out(7)=> Port7_out(2),
2478	Data_out(8)=> Port8_out(2),
2479	Data_out(9)=> Port9_out(2),
2480	Data_out(10)=> Port10_out(2),
2481	Data_out(11)=> Port11_out(2),
2482	Data_out(12)=> Port12_out(2)
2483
2484	);
2485	-- crossbit du bit 3 de donnée
2486
2487	Data3_Crossbit: Crossbit
2488	GENERIC MAP(number_of_ports => 12)
2489	PORT MAP(
2490
2491	reset => reset,
2492	clk=>clk,
2493
2494	Control => Ctrl_buf,
2495	Data_In(1) => Port1_in(3),
2496	Data_In(2) => Port2_in(3),
2497	Data_In(3) => Port3_in(3),
2498	Data_In(4) => Port4_in(3),
2499	Data_In(5) => Port5_in(3),
2500	Data_In(6) => Port6_in(3),
2501	Data_In(7) => Port7_in(3),
2502	Data_In(8) => Port8_in(3),
2503	Data_In(9) => Port9_in(3),
2504	Data_In(10) => Port10_in(3),
2505	Data_In(11) => Port11_in(3),
2506	Data_In(12) => Port12_in(3),
2507	Data_out(1)=> Port1_out(3),
2508	Data_out(2)=> Port2_out(3),
2509	Data_out(3)=> Port3_out(3),
2510	Data_out(4)=> Port4_out(3),
2511	Data_out(5)=> Port5_out(3),
2512	Data_out(6)=> Port6_out(3),
2513	Data_out(7)=> Port7_out(3),
2514	Data_out(8)=> Port8_out(3),
2515	Data_out(9)=> Port9_out(3),
2516	Data_out(10)=> Port10_out(3),
2517	Data_out(11)=> Port11_out(3),
2518	Data_out(12)=> Port12_out(3)
2519
2520	);
2521	-- crossbit du bit 4 de donnée
2522
2523	Data4_Crossbit: Crossbit
2524	GENERIC MAP(number_of_ports => 12)
2525	PORT MAP(
2526
2527	reset => reset,
2528	clk=>clk,
2529
2530	Control => Ctrl_buf,
2531	Data_In(1) => Port1_in(4),
2532	Data_In(2) => Port2_in(4),
2533	Data_In(3) => Port3_in(4),
2534	Data_In(4) => Port4_in(4),
2535	Data_In(5) => Port5_in(4),
2536	Data_In(6) => Port6_in(4),
2537	Data_In(7) => Port7_in(4),
2538	Data_In(8) => Port8_in(4),
2539	Data_In(9) => Port9_in(4),
2540	Data_In(10) => Port10_in(4),
2541	Data_In(11) => Port11_in(4),
2542	Data_In(12) => Port12_in(4),
2543	Data_out(1)=> Port1_out(4),
2544	Data_out(2)=> Port2_out(4),
2545	Data_out(3)=> Port3_out(4),
2546	Data_out(4)=> Port4_out(4),
2547	Data_out(5)=> Port5_out(4),
2548	Data_out(6)=> Port6_out(4),
2549	Data_out(7)=> Port7_out(4),
2550	Data_out(8)=> Port8_out(4),
2551	Data_out(9)=> Port9_out(4),
2552	Data_out(10)=> Port10_out(4),
2553	Data_out(11)=> Port11_out(4),
2554	Data_out(12)=> Port12_out(4)
2555
2556	);
2557	-- crossbit du bit 5 de donnée
2558
2559	Data5_Crossbit: Crossbit
2560	GENERIC MAP(number_of_ports => 12)
2561	PORT MAP(
2562
2563	reset => reset,
2564	clk=>clk,
2565
2566	Control => Ctrl_buf,
2567	Data_In(1) => Port1_in(5),
2568	Data_In(2) => Port2_in(5),
2569	Data_In(3) => Port3_in(5),
2570	Data_In(4) => Port4_in(5),
2571	Data_In(5) => Port5_in(5),
2572	Data_In(6) => Port6_in(5),
2573	Data_In(7) => Port7_in(5),
2574	Data_In(8) => Port8_in(5),
2575	Data_In(9) => Port9_in(5),
2576	Data_In(10) => Port10_in(5),
2577	Data_In(11) => Port11_in(5),
2578	Data_In(12) => Port12_in(5),
2579	Data_out(1)=> Port1_out(5),
2580	Data_out(2)=> Port2_out(5),
2581	Data_out(3)=> Port3_out(5),
2582	Data_out(4)=> Port4_out(5),
2583	Data_out(5)=> Port5_out(5),
2584	Data_out(6)=> Port6_out(5),
2585	Data_out(7)=> Port7_out(5),
2586	Data_out(8)=> Port8_out(5),
2587	Data_out(9)=> Port9_out(5),
2588	Data_out(10)=> Port10_out(5),
2589	Data_out(11)=> Port11_out(5),
2590	Data_out(12)=> Port12_out(5)
2591
2592	);
2593	-- crossbit du bit 6 de donnée
2594
2595	Data6_Crossbit: Crossbit
2596	GENERIC MAP(number_of_ports => 12)
2597	PORT MAP(
2598
2599	reset => reset,
2600	clk=>clk,
2601
2602	Control => Ctrl_buf,
2603	Data_In(1) => Port1_in(6),
2604	Data_In(2) => Port2_in(6),
2605	Data_In(3) => Port3_in(6),
2606	Data_In(4) => Port4_in(6),
2607	Data_In(5) => Port5_in(6),
2608	Data_In(6) => Port6_in(6),
2609	Data_In(7) => Port7_in(6),
2610	Data_In(8) => Port8_in(6),
2611	Data_In(9) => Port9_in(6),
2612	Data_In(10) => Port10_in(6),
2613	Data_In(11) => Port11_in(6),
2614	Data_In(12) => Port12_in(6),
2615	Data_out(1)=> Port1_out(6),
2616	Data_out(2)=> Port2_out(6),
2617	Data_out(3)=> Port3_out(6),
2618	Data_out(4)=> Port4_out(6),
2619	Data_out(5)=> Port5_out(6),
2620	Data_out(6)=> Port6_out(6),
2621	Data_out(7)=> Port7_out(6),
2622	Data_out(8)=> Port8_out(6),
2623	Data_out(9)=> Port9_out(6),
2624	Data_out(10)=> Port10_out(6),
2625	Data_out(11)=> Port11_out(6),
2626	Data_out(12)=> Port12_out(6)
2627
2628	);
2629	-- crossbit du bit 7 de donnée
2630
2631	Data7_Crossbit: Crossbit
2632	GENERIC MAP(number_of_ports => 12)
2633	PORT MAP(
2634
2635	reset => reset,
2636	clk=>clk,
2637
2638	Control => Ctrl_buf,
2639	Data_In(1) => Port1_in(7),
2640	Data_In(2) => Port2_in(7),
2641	Data_In(3) => Port3_in(7),
2642	Data_In(4) => Port4_in(7),
2643	Data_In(5) => Port5_in(7),
2644	Data_In(6) => Port6_in(7),
2645	Data_In(7) => Port7_in(7),
2646	Data_In(8) => Port8_in(7),
2647	Data_In(9) => Port9_in(7),
2648	Data_In(10) => Port10_in(7),
2649	Data_In(11) => Port11_in(7),
2650	Data_In(12) => Port12_in(7),
2651	Data_out(1)=> Port1_out(7),
2652	Data_out(2)=> Port2_out(7),
2653	Data_out(3)=> Port3_out(7),
2654	Data_out(4)=> Port4_out(7),
2655	Data_out(5)=> Port5_out(7),
2656	Data_out(6)=> Port6_out(7),
2657	Data_out(7)=> Port7_out(7),
2658	Data_out(8)=> Port8_out(7),
2659	Data_out(9)=> Port9_out(7),
2660	Data_out(10)=> Port10_out(7),
2661	Data_out(11)=> Port11_out(7),
2662	Data_out(12)=> Port12_out(7)
2663
2664	);
2665	-- crossbit du pulse_out 12 ports
2666
2667	Pulse_out_Crossbit12: Crossbit
2668	GENERIC MAP(number_of_ports => 12)
2669	PORT MAP(
2670
2671	reset => reset,
2672	clk=>clk,
2673
2674	Control => Ctrl_buf,
2675	Data_In(1) => Port1_pulse_in,
2676	Data_In(2) => Port2_pulse_in,
2677	Data_In(3) => Port3_pulse_in,
2678	Data_In(4) => Port4_pulse_in,
2679	Data_In(5) => Port5_pulse_in,
2680	Data_In(6) => Port6_pulse_in,
2681	Data_In(7) => Port7_pulse_in,
2682	Data_In(8) => Port8_pulse_in,
2683	Data_In(9) => Port9_pulse_in,
2684	Data_In(10) => Port10_pulse_in,
2685	Data_In(11) => Port11_pulse_in,
2686	Data_In(12) => Port12_pulse_in,
2687	Data_out(1) => Port1_pulse_out,
2688	Data_out(2) => Port2_pulse_out,
2689	Data_out(3) => Port3_pulse_out,
2690	Data_out(4) => Port4_pulse_out,
2691	Data_out(5) => Port5_pulse_out,
2692	Data_out(6) => Port6_pulse_out,
2693	Data_out(7) => Port7_pulse_out,
2694	Data_out(8) => Port8_pulse_out,
2695	Data_out(9) => Port9_pulse_out,
2696	Data_out(10) => Port10_pulse_out,
2697	Data_out(11) => Port11_pulse_out,
2698	Data_out(12) => Port12_pulse_out
2699
2700	);
2701	end generate crossbar12x12;
2702
2703
2704	--======================crossbar 13 ports=======================
2705
2706	crossbar13x13 : if number_of_crossbar_ports = 13 generate
2707
2708	-- crossbit du bit 0 de donnée
2709
2710	Data0_Crossbit: Crossbit
2711	GENERIC MAP(number_of_ports => 13)
2712	PORT MAP(
2713
2714	reset => reset,
2715	clk=>clk,
2716	Control => Ctrl_buf,
2717	Data_In(1) => Port1_in(0),
2718	Data_In(2) => Port2_in(0),
2719	Data_In(3) => Port3_in(0),
2720	Data_In(4) => Port4_in(0),
2721	Data_In(5) => Port5_in(0),
2722	Data_In(6) => Port6_in(0),
2723	Data_In(7) => Port7_in(0),
2724	Data_In(8) => Port8_in(0),
2725	Data_In(9) => Port9_in(0),
2726	Data_In(10) => Port10_in(0),
2727	Data_In(11) => Port11_in(0),
2728	Data_In(12) => Port12_in(0),
2729	Data_In(13) => Port13_in(0),
2730	Data_out(1)=> Port1_out(0),
2731	Data_out(2)=> Port2_out(0),
2732	Data_out(3)=> Port3_out(0),
2733	Data_out(4)=> Port4_out(0),
2734	Data_out(5)=> Port5_out(0),
2735	Data_out(6)=> Port6_out(0),
2736	Data_out(7)=> Port7_out(0),
2737	Data_out(8)=> Port8_out(0),
2738	Data_out(9)=> Port9_out(0),
2739	Data_out(10)=> Port10_out(0),
2740	Data_out(11)=> Port11_out(0),
2741	Data_out(12)=> Port12_out(0),
2742	Data_out(13)=> Port13_out(0)
2743
2744	);
2745	-- crossbit du bit 1 de donnée
2746
2747	Data1_Crossbit: Crossbit
2748	GENERIC MAP(number_of_ports => 13)
2749	PORT MAP(
2750
2751	reset => reset,
2752	clk=>clk,
2753
2754	Control => Ctrl_buf,
2755	Data_In(1) => Port1_in(1),
2756	Data_In(2) => Port2_in(1),
2757	Data_In(3) => Port3_in(1),
2758	Data_In(4) => Port4_in(1),
2759	Data_In(5) => Port5_in(1),
2760	Data_In(6) => Port6_in(1),
2761	Data_In(7) => Port7_in(1),
2762	Data_In(8) => Port8_in(1),
2763	Data_In(9) => Port9_in(1),
2764	Data_In(10) => Port10_in(1),
2765	Data_In(11) => Port11_in(1),
2766	Data_In(12) => Port12_in(1),
2767	Data_In(13) => Port13_in(1),
2768	Data_out(1)=> Port1_out(1),
2769	Data_out(2)=> Port2_out(1),
2770	Data_out(3)=> Port3_out(1),
2771	Data_out(4)=> Port4_out(1),
2772	Data_out(5)=> Port5_out(1),
2773	Data_out(6)=> Port6_out(1),
2774	Data_out(7)=> Port7_out(1),
2775	Data_out(8)=> Port8_out(1),
2776	Data_out(9)=> Port9_out(1),
2777	Data_out(10)=> Port10_out(1),
2778	Data_out(11)=> Port11_out(1),
2779	Data_out(12)=> Port12_out(1),
2780	Data_out(13)=> Port13_out(1)
2781
2782	);
2783	-- crossbit du bit 2 de donnée
2784
2785	Data2_Crossbit: Crossbit
2786	GENERIC MAP(number_of_ports => 13)
2787	PORT MAP(
2788
2789	reset => reset,
2790	clk=>clk,
2791
2792	Control => Ctrl_buf,
2793	Data_In(1) => Port1_in(2),
2794	Data_In(2) => Port2_in(2),
2795	Data_In(3) => Port3_in(2),
2796	Data_In(4) => Port4_in(2),
2797	Data_In(5) => Port5_in(2),
2798	Data_In(6) => Port6_in(2),
2799	Data_In(7) => Port7_in(2),
2800	Data_In(8) => Port8_in(2),
2801	Data_In(9) => Port9_in(2),
2802	Data_In(10) => Port10_in(2),
2803	Data_In(11) => Port11_in(2),
2804	Data_In(12) => Port12_in(2),
2805	Data_In(13) => Port13_in(2),
2806	Data_out(1)=> Port1_out(2),
2807	Data_out(2)=> Port2_out(2),
2808	Data_out(3)=> Port3_out(2),
2809	Data_out(4)=> Port4_out(2),
2810	Data_out(5)=> Port5_out(2),
2811	Data_out(6)=> Port6_out(2),
2812	Data_out(7)=> Port7_out(2),
2813	Data_out(8)=> Port8_out(2),
2814	Data_out(9)=> Port9_out(2),
2815	Data_out(10)=> Port10_out(2),
2816	Data_out(11)=> Port11_out(2),
2817	Data_out(12)=> Port12_out(2),
2818	Data_out(13)=> Port13_out(2)
2819
2820	);
2821	-- crossbit du bit 3 de donnée
2822
2823	Data3_Crossbit: Crossbit
2824	GENERIC MAP(number_of_ports => 13)
2825	PORT MAP(
2826
2827	reset => reset,
2828	clk=>clk,
2829	Control => Ctrl_buf,
2830	Data_In(1) => Port1_in(3),
2831	Data_In(2) => Port2_in(3),
2832	Data_In(3) => Port3_in(3),
2833	Data_In(4) => Port4_in(3),
2834	Data_In(5) => Port5_in(3),
2835	Data_In(6) => Port6_in(3),
2836	Data_In(7) => Port7_in(3),
2837	Data_In(8) => Port8_in(3),
2838	Data_In(9) => Port9_in(3),
2839	Data_In(10) => Port10_in(3),
2840	Data_In(11) => Port11_in(3),
2841	Data_In(12) => Port12_in(3),
2842	Data_In(13) => Port13_in(3),
2843	Data_out(1)=> Port1_out(3),
2844	Data_out(2)=> Port2_out(3),
2845	Data_out(3)=> Port3_out(3),
2846	Data_out(4)=> Port4_out(3),
2847	Data_out(5)=> Port5_out(3),
2848	Data_out(6)=> Port6_out(3),
2849	Data_out(7)=> Port7_out(3),
2850	Data_out(8)=> Port8_out(3),
2851	Data_out(9)=> Port9_out(3),
2852	Data_out(10)=> Port10_out(3),
2853	Data_out(11)=> Port11_out(3),
2854	Data_out(12)=> Port12_out(3),
2855	Data_out(13)=> Port13_out(3)
2856
2857	);
2858	-- crossbit du bit 4 de donnée
2859
2860	Data4_Crossbit: Crossbit
2861	GENERIC MAP(number_of_ports => 13)
2862	PORT MAP(
2863
2864	reset => reset,
2865	clk=>clk,
2866	Control => Ctrl_buf,
2867	Data_In(1) => Port1_in(4),
2868	Data_In(2) => Port2_in(4),
2869	Data_In(3) => Port3_in(4),
2870	Data_In(4) => Port4_in(4),
2871	Data_In(5) => Port5_in(4),
2872	Data_In(6) => Port6_in(4),
2873	Data_In(7) => Port7_in(4),
2874	Data_In(8) => Port8_in(4),
2875	Data_In(9) => Port9_in(4),
2876	Data_In(10) => Port10_in(4),
2877	Data_In(11) => Port11_in(4),
2878	Data_In(12) => Port12_in(4),
2879	Data_In(13) => Port13_in(4),
2880	Data_out(1)=> Port1_out(4),
2881	Data_out(2)=> Port2_out(4),
2882	Data_out(3)=> Port3_out(4),
2883	Data_out(4)=> Port4_out(4),
2884	Data_out(5)=> Port5_out(4),
2885	Data_out(6)=> Port6_out(4),
2886	Data_out(7)=> Port7_out(4),
2887	Data_out(8)=> Port8_out(4),
2888	Data_out(9)=> Port9_out(4),
2889	Data_out(10)=> Port10_out(4),
2890	Data_out(11)=> Port11_out(4),
2891	Data_out(12)=> Port12_out(4),
2892	Data_out(13)=> Port13_out(4)
2893
2894	);
2895	-- crossbit du bit 5 de donnée
2896
2897	Data5_Crossbit: Crossbit
2898	GENERIC MAP(number_of_ports => 13)
2899	PORT MAP(
2900
2901	reset => reset,
2902	clk=>clk,
2903	Control => Ctrl_buf,
2904	Data_In(1) => Port1_in(5),
2905	Data_In(2) => Port2_in(5),
2906	Data_In(3) => Port3_in(5),
2907	Data_In(4) => Port4_in(5),
2908	Data_In(5) => Port5_in(5),
2909	Data_In(6) => Port6_in(5),
2910	Data_In(7) => Port7_in(5),
2911	Data_In(8) => Port8_in(5),
2912	Data_In(9) => Port9_in(5),
2913	Data_In(10) => Port10_in(5),
2914	Data_In(11) => Port11_in(5),
2915	Data_In(12) => Port12_in(5),
2916	Data_In(13) => Port13_in(5),
2917	Data_out(1)=> Port1_out(5),
2918	Data_out(2)=> Port2_out(5),
2919	Data_out(3)=> Port3_out(5),
2920	Data_out(4)=> Port4_out(5),
2921	Data_out(5)=> Port5_out(5),
2922	Data_out(6)=> Port6_out(5),
2923	Data_out(7)=> Port7_out(5),
2924	Data_out(8)=> Port8_out(5),
2925	Data_out(9)=> Port9_out(5),
2926	Data_out(10)=> Port10_out(5),
2927	Data_out(11)=> Port11_out(5),
2928	Data_out(12)=> Port12_out(5),
2929	Data_out(13)=> Port13_out(5)
2930
2931	);
2932	-- crossbit du bit 6 de donnée
2933
2934	Data6_Crossbit: Crossbit
2935	GENERIC MAP(number_of_ports => 13)
2936	PORT MAP(
2937
2938	reset => reset,
2939	clk=>clk,
2940	Control => Ctrl_buf,
2941	Data_In(1) => Port1_in(6),
2942	Data_In(2) => Port2_in(6),
2943	Data_In(3) => Port3_in(6),
2944	Data_In(4) => Port4_in(6),
2945	Data_In(5) => Port5_in(6),
2946	Data_In(6) => Port6_in(6),
2947	Data_In(7) => Port7_in(6),
2948	Data_In(8) => Port8_in(6),
2949	Data_In(9) => Port9_in(6),
2950	Data_In(10) => Port10_in(6),
2951	Data_In(11) => Port11_in(6),
2952	Data_In(12) => Port12_in(6),
2953	Data_In(13) => Port13_in(6),
2954	Data_out(1)=> Port1_out(6),
2955	Data_out(2)=> Port2_out(6),
2956	Data_out(3)=> Port3_out(6),
2957	Data_out(4)=> Port4_out(6),
2958	Data_out(5)=> Port5_out(6),
2959	Data_out(6)=> Port6_out(6),
2960	Data_out(7)=> Port7_out(6),
2961	Data_out(8)=> Port8_out(6),
2962	Data_out(9)=> Port9_out(6),
2963	Data_out(10)=> Port10_out(6),
2964	Data_out(11)=> Port11_out(6),
2965	Data_out(12)=> Port12_out(6),
2966	Data_out(13)=> Port13_out(6)
2967
2968	);
2969	-- crossbit du bit 7 de donnée
2970
2971	Data7_Crossbit: Crossbit
2972	GENERIC MAP(number_of_ports => 13)
2973	PORT MAP(
2974
2975	reset => reset,
2976	clk=>clk,
2977	Control => Ctrl_buf,
2978	Data_In(1) => Port1_in(7),
2979	Data_In(2) => Port2_in(7),
2980	Data_In(3) => Port3_in(7),
2981	Data_In(4) => Port4_in(7),
2982	Data_In(5) => Port5_in(7),
2983	Data_In(6) => Port6_in(7),
2984	Data_In(7) => Port7_in(7),
2985	Data_In(8) => Port8_in(7),
2986	Data_In(9) => Port9_in(7),
2987	Data_In(10) => Port10_in(7),
2988	Data_In(11) => Port11_in(7),
2989	Data_In(12) => Port12_in(7),
2990	Data_In(13) => Port13_in(7),
2991	Data_out(1)=> Port1_out(7),
2992	Data_out(2)=> Port2_out(7),
2993	Data_out(3)=> Port3_out(7),
2994	Data_out(4)=> Port4_out(7),
2995	Data_out(5)=> Port5_out(7),
2996	Data_out(6)=> Port6_out(7),
2997	Data_out(7)=> Port7_out(7),
2998	Data_out(8)=> Port8_out(7),
2999	Data_out(9)=> Port9_out(7),
3000	Data_out(10)=> Port10_out(7),
3001	Data_out(11)=> Port11_out(7),
3002	Data_out(12)=> Port12_out(7),
3003	Data_out(13)=> Port13_out(7)
3004
3005	);
3006	-- crossbit du pulse_out 13 ports
3007
3008	Pulse_out_Crossbit13: Crossbit
3009	GENERIC MAP(number_of_ports => 13)
3010	PORT MAP(
3011
3012	reset => reset,
3013	clk=>clk,
3014	Control => Ctrl_buf,
3015	Data_In(1) => Port1_pulse_in,
3016	Data_In(2) => Port2_pulse_in,
3017	Data_In(3) => Port3_pulse_in,
3018	Data_In(4) => Port4_pulse_in,
3019	Data_In(5) => Port5_pulse_in,
3020	Data_In(6) => Port6_pulse_in,
3021	Data_In(7) => Port7_pulse_in,
3022	Data_In(8) => Port8_pulse_in,
3023	Data_In(9) => Port9_pulse_in,
3024	Data_In(10) => Port10_pulse_in,
3025	Data_In(11) => Port11_pulse_in,
3026	Data_In(12) => Port12_pulse_in,
3027	Data_In(13) => Port13_pulse_in,
3028	Data_out(1) => Port1_pulse_out,
3029	Data_out(2) => Port2_pulse_out,
3030	Data_out(3) => Port3_pulse_out,
3031	Data_out(4) => Port4_pulse_out,
3032	Data_out(5) => Port5_pulse_out,
3033	Data_out(6) => Port6_pulse_out,
3034	Data_out(7) => Port7_pulse_out,
3035	Data_out(8) => Port8_pulse_out,
3036	Data_out(9) => Port9_pulse_out,
3037	Data_out(10) => Port10_pulse_out,
3038	Data_out(11) => Port11_pulse_out,
3039	Data_out(12) => Port12_pulse_out,
3040	Data_out(13) => Port13_pulse_out
3041
3042	);
3043	end generate crossbar13x13;
3044
3045
3046	--======================crossbar 14 ports=======================
3047
3048	crossbar14x14 : if number_of_crossbar_ports = 14 generate
3049
3050	-- crossbit du bit 0 de donnée
3051
3052	Data0_Crossbit: Crossbit
3053	GENERIC MAP(number_of_ports => 14)
3054	PORT MAP(
3055
3056	reset => reset,
3057	clk=>clk,
3058	Control => Ctrl_buf,
3059	Data_In(1) => Port1_in(0),
3060	Data_In(2) => Port2_in(0),
3061	Data_In(3) => Port3_in(0),
3062	Data_In(4) => Port4_in(0),
3063	Data_In(5) => Port5_in(0),
3064	Data_In(6) => Port6_in(0),
3065	Data_In(7) => Port7_in(0),
3066	Data_In(8) => Port8_in(0),
3067	Data_In(9) => Port9_in(0),
3068	Data_In(10) => Port10_in(0),
3069	Data_In(11) => Port11_in(0),
3070	Data_In(12) => Port12_in(0),
3071	Data_In(13) => Port13_in(0),
3072	Data_In(14) => Port14_in(0),
3073	Data_out(1)=> Port1_out(0),
3074	Data_out(2)=> Port2_out(0),
3075	Data_out(3)=> Port3_out(0),
3076	Data_out(4)=> Port4_out(0),
3077	Data_out(5)=> Port5_out(0),
3078	Data_out(6)=> Port6_out(0),
3079	Data_out(7)=> Port7_out(0),
3080	Data_out(8)=> Port8_out(0),
3081	Data_out(9)=> Port9_out(0),
3082	Data_out(10)=> Port10_out(0),
3083	Data_out(11)=> Port11_out(0),
3084	Data_out(12)=> Port12_out(0),
3085	Data_out(13)=> Port13_out(0),
3086	Data_out(14)=> Port14_out(0)
3087
3088	);
3089	-- crossbit du bit 1 de donnée
3090
3091	Data1_Crossbit: Crossbit
3092	GENERIC MAP(number_of_ports => 14)
3093	PORT MAP(
3094
3095	reset => reset,
3096	clk=>clk,
3097	Control => Ctrl_buf,
3098	Data_In(1) => Port1_in(1),
3099	Data_In(2) => Port2_in(1),
3100	Data_In(3) => Port3_in(1),
3101	Data_In(4) => Port4_in(1),
3102	Data_In(5) => Port5_in(1),
3103	Data_In(6) => Port6_in(1),
3104	Data_In(7) => Port7_in(1),
3105	Data_In(8) => Port8_in(1),
3106	Data_In(9) => Port9_in(1),
3107	Data_In(10) => Port10_in(1),
3108	Data_In(11) => Port11_in(1),
3109	Data_In(12) => Port12_in(1),
3110	Data_In(13) => Port13_in(1),
3111	Data_In(14) => Port14_in(1),
3112	Data_out(1)=> Port1_out(1),
3113	Data_out(2)=> Port2_out(1),
3114	Data_out(3)=> Port3_out(1),
3115	Data_out(4)=> Port4_out(1),
3116	Data_out(5)=> Port5_out(1),
3117	Data_out(6)=> Port6_out(1),
3118	Data_out(7)=> Port7_out(1),
3119	Data_out(8)=> Port8_out(1),
3120	Data_out(9)=> Port9_out(1),
3121	Data_out(10)=> Port10_out(1),
3122	Data_out(11)=> Port11_out(1),
3123	Data_out(12)=> Port12_out(1),
3124	Data_out(13)=> Port13_out(1),
3125	Data_out(14)=> Port14_out(1)
3126
3127	);
3128	-- crossbit du bit 2 de donnée
3129
3130	Data2_Crossbit: Crossbit
3131	GENERIC MAP(number_of_ports => 14)
3132	PORT MAP(
3133
3134	reset => reset,
3135	clk=>clk,
3136	Control => Ctrl_buf,
3137	Data_In(1) => Port1_in(2),
3138	Data_In(2) => Port2_in(2),
3139	Data_In(3) => Port3_in(2),
3140	Data_In(4) => Port4_in(2),
3141	Data_In(5) => Port5_in(2),
3142	Data_In(6) => Port6_in(2),
3143	Data_In(7) => Port7_in(2),
3144	Data_In(8) => Port8_in(2),
3145	Data_In(9) => Port9_in(2),
3146	Data_In(10) => Port10_in(2),
3147	Data_In(11) => Port11_in(2),
3148	Data_In(12) => Port12_in(2),
3149	Data_In(13) => Port13_in(2),
3150	Data_In(14) => Port14_in(2),
3151	Data_out(1)=> Port1_out(2),
3152	Data_out(2)=> Port2_out(2),
3153	Data_out(3)=> Port3_out(2),
3154	Data_out(4)=> Port4_out(2),
3155	Data_out(5)=> Port5_out(2),
3156	Data_out(6)=> Port6_out(2),
3157	Data_out(7)=> Port7_out(2),
3158	Data_out(8)=> Port8_out(2),
3159	Data_out(9)=> Port9_out(2),
3160	Data_out(10)=> Port10_out(2),
3161	Data_out(11)=> Port11_out(2),
3162	Data_out(12)=> Port12_out(2),
3163	Data_out(13)=> Port13_out(2),
3164	Data_out(14)=> Port14_out(2)
3165
3166	);
3167	-- crossbit du bit 3 de donnée
3168
3169	Data3_Crossbit: Crossbit
3170	GENERIC MAP(number_of_ports => 14)
3171	PORT MAP(
3172
3173	reset => reset,
3174	clk=>clk,
3175	Control => Ctrl_buf,
3176	Data_In(1) => Port1_in(3),
3177	Data_In(2) => Port2_in(3),
3178	Data_In(3) => Port3_in(3),
3179	Data_In(4) => Port4_in(3),
3180	Data_In(5) => Port5_in(3),
3181	Data_In(6) => Port6_in(3),
3182	Data_In(7) => Port7_in(3),
3183	Data_In(8) => Port8_in(3),
3184	Data_In(9) => Port9_in(3),
3185	Data_In(10) => Port10_in(3),
3186	Data_In(11) => Port11_in(3),
3187	Data_In(12) => Port12_in(3),
3188	Data_In(13) => Port13_in(3),
3189	Data_In(14) => Port14_in(3),
3190	Data_out(1)=> Port1_out(3),
3191	Data_out(2)=> Port2_out(3),
3192	Data_out(3)=> Port3_out(3),
3193	Data_out(4)=> Port4_out(3),
3194	Data_out(5)=> Port5_out(3),
3195	Data_out(6)=> Port6_out(3),
3196	Data_out(7)=> Port7_out(3),
3197	Data_out(8)=> Port8_out(3),
3198	Data_out(9)=> Port9_out(3),
3199	Data_out(10)=> Port10_out(3),
3200	Data_out(11)=> Port11_out(3),
3201	Data_out(12)=> Port12_out(3),
3202	Data_out(13)=> Port13_out(3),
3203	Data_out(14)=> Port14_out(3)
3204
3205	);
3206	-- crossbit du bit 4 de donnée
3207
3208	Data4_Crossbit: Crossbit
3209	GENERIC MAP(number_of_ports => 14)
3210	PORT MAP(
3211
3212	reset => reset,
3213	clk=>clk,
3214	Control => Ctrl_buf,
3215	Data_In(1) => Port1_in(4),
3216	Data_In(2) => Port2_in(4),
3217	Data_In(3) => Port3_in(4),
3218	Data_In(4) => Port4_in(4),
3219	Data_In(5) => Port5_in(4),
3220	Data_In(6) => Port6_in(4),
3221	Data_In(7) => Port7_in(4),
3222	Data_In(8) => Port8_in(4),
3223	Data_In(9) => Port9_in(4),
3224	Data_In(10) => Port10_in(4),
3225	Data_In(11) => Port11_in(4),
3226	Data_In(12) => Port12_in(4),
3227	Data_In(13) => Port13_in(4),
3228	Data_In(14) => Port14_in(4),
3229	Data_out(1)=> Port1_out(4),
3230	Data_out(2)=> Port2_out(4),
3231	Data_out(3)=> Port3_out(4),
3232	Data_out(4)=> Port4_out(4),
3233	Data_out(5)=> Port5_out(4),
3234	Data_out(6)=> Port6_out(4),
3235	Data_out(7)=> Port7_out(4),
3236	Data_out(8)=> Port8_out(4),
3237	Data_out(9)=> Port9_out(4),
3238	Data_out(10)=> Port10_out(4),
3239	Data_out(11)=> Port11_out(4),
3240	Data_out(12)=> Port12_out(4),
3241	Data_out(13)=> Port13_out(4),
3242	Data_out(14)=> Port14_out(4)
3243
3244	);
3245	-- crossbit du bit 5 de donnée
3246
3247	Data5_Crossbit: Crossbit
3248	GENERIC MAP(number_of_ports => 14)
3249	PORT MAP(
3250
3251	reset => reset,
3252	clk=>clk,
3253	Control => Ctrl_buf,
3254	Data_In(1) => Port1_in(5),
3255	Data_In(2) => Port2_in(5),
3256	Data_In(3) => Port3_in(5),
3257	Data_In(4) => Port4_in(5),
3258	Data_In(5) => Port5_in(5),
3259	Data_In(6) => Port6_in(5),
3260	Data_In(7) => Port7_in(5),
3261	Data_In(8) => Port8_in(5),
3262	Data_In(9) => Port9_in(5),
3263	Data_In(10) => Port10_in(5),
3264	Data_In(11) => Port11_in(5),
3265	Data_In(12) => Port12_in(5),
3266	Data_In(13) => Port13_in(5),
3267	Data_In(14) => Port14_in(5),
3268	Data_out(1)=> Port1_out(5),
3269	Data_out(2)=> Port2_out(5),
3270	Data_out(3)=> Port3_out(5),
3271	Data_out(4)=> Port4_out(5),
3272	Data_out(5)=> Port5_out(5),
3273	Data_out(6)=> Port6_out(5),
3274	Data_out(7)=> Port7_out(5),
3275	Data_out(8)=> Port8_out(5),
3276	Data_out(9)=> Port9_out(5),
3277	Data_out(10)=> Port10_out(5),
3278	Data_out(11)=> Port11_out(5),
3279	Data_out(12)=> Port12_out(5),
3280	Data_out(13)=> Port13_out(5),
3281	Data_out(14)=> Port14_out(5)
3282
3283	);
3284	-- crossbit du bit 6 de donnée
3285
3286	Data6_Crossbit: Crossbit
3287	GENERIC MAP(number_of_ports => 14)
3288	PORT MAP(
3289
3290	reset => reset,
3291	clk=>clk,
3292	Control => Ctrl_buf,
3293	Data_In(1) => Port1_in(6),
3294	Data_In(2) => Port2_in(6),
3295	Data_In(3) => Port3_in(6),
3296	Data_In(4) => Port4_in(6),
3297	Data_In(5) => Port5_in(6),
3298	Data_In(6) => Port6_in(6),
3299	Data_In(7) => Port7_in(6),
3300	Data_In(8) => Port8_in(6),
3301	Data_In(9) => Port9_in(6),
3302	Data_In(10) => Port10_in(6),
3303	Data_In(11) => Port11_in(6),
3304	Data_In(12) => Port12_in(6),
3305	Data_In(13) => Port13_in(6),
3306	Data_In(14) => Port14_in(6),
3307	Data_out(1)=> Port1_out(6),
3308	Data_out(2)=> Port2_out(6),
3309	Data_out(3)=> Port3_out(6),
3310	Data_out(4)=> Port4_out(6),
3311	Data_out(5)=> Port5_out(6),
3312	Data_out(6)=> Port6_out(6),
3313	Data_out(7)=> Port7_out(6),
3314	Data_out(8)=> Port8_out(6),
3315	Data_out(9)=> Port9_out(6),
3316	Data_out(10)=> Port10_out(6),
3317	Data_out(11)=> Port11_out(6),
3318	Data_out(12)=> Port12_out(6),
3319	Data_out(13)=> Port13_out(6),
3320	Data_out(14)=> Port14_out(6)
3321
3322	);
3323	-- crossbit du bit 7 de donnée
3324
3325	Data7_Crossbit: Crossbit
3326	GENERIC MAP(number_of_ports => 14)
3327	PORT MAP(
3328
3329	reset => reset,
3330	clk=>clk,
3331	Control => Ctrl_buf,
3332	Data_In(1) => Port1_in(7),
3333	Data_In(2) => Port2_in(7),
3334	Data_In(3) => Port3_in(7),
3335	Data_In(4) => Port4_in(7),
3336	Data_In(5) => Port5_in(7),
3337	Data_In(6) => Port6_in(7),
3338	Data_In(7) => Port7_in(7),
3339	Data_In(8) => Port8_in(7),
3340	Data_In(9) => Port9_in(7),
3341	Data_In(10) => Port10_in(7),
3342	Data_In(11) => Port11_in(7),
3343	Data_In(12) => Port12_in(7),
3344	Data_In(13) => Port13_in(7),
3345	Data_In(14) => Port14_in(7),
3346	Data_out(1)=> Port1_out(7),
3347	Data_out(2)=> Port2_out(7),
3348	Data_out(3)=> Port3_out(7),
3349	Data_out(4)=> Port4_out(7),
3350	Data_out(5)=> Port5_out(7),
3351	Data_out(6)=> Port6_out(7),
3352	Data_out(7)=> Port7_out(7),
3353	Data_out(8)=> Port8_out(7),
3354	Data_out(9)=> Port9_out(7),
3355	Data_out(10)=> Port10_out(7),
3356	Data_out(11)=> Port11_out(7),
3357	Data_out(12)=> Port12_out(7),
3358	Data_out(13)=> Port13_out(7),
3359	Data_out(14)=> Port14_out(7)
3360
3361	);
3362	-- crossbit du pulse_out 14 ports
3363
3364	Pulse_out_Crossbit14: Crossbit
3365	GENERIC MAP(number_of_ports => 14)
3366	PORT MAP(
3367
3368	reset => reset,
3369	clk=>clk,
3370	Control => Ctrl_buf,
3371	Data_In(1) => Port1_pulse_in,
3372	Data_In(2) => Port2_pulse_in,
3373	Data_In(3) => Port3_pulse_in,
3374	Data_In(4) => Port4_pulse_in,
3375	Data_In(5) => Port5_pulse_in,
3376	Data_In(6) => Port6_pulse_in,
3377	Data_In(7) => Port7_pulse_in,
3378	Data_In(8) => Port8_pulse_in,
3379	Data_In(9) => Port9_pulse_in,
3380	Data_In(10) => Port10_pulse_in,
3381	Data_In(11) => Port11_pulse_in,
3382	Data_In(12) => Port12_pulse_in,
3383	Data_In(13) => Port13_pulse_in,
3384	Data_In(14) => Port14_pulse_in,
3385	Data_out(1) => Port1_pulse_out,
3386	Data_out(2) => Port2_pulse_out,
3387	Data_out(3) => Port3_pulse_out,
3388	Data_out(4) => Port4_pulse_out,
3389	Data_out(5) => Port5_pulse_out,
3390	Data_out(6) => Port6_pulse_out,
3391	Data_out(7) => Port7_pulse_out,
3392	Data_out(8) => Port8_pulse_out,
3393	Data_out(9) => Port9_pulse_out,
3394	Data_out(10) => Port10_pulse_out,
3395	Data_out(11) => Port11_pulse_out,
3396	Data_out(12) => Port12_pulse_out,
3397	Data_out(13) => Port13_pulse_out,
3398	Data_out(14) => Port14_pulse_out
3399
3400	);
3401	end generate crossbar14x14;
3402
3403
3404	--======================crossbar 15 ports=======================
3405
3406	crossbar15x15 : if number_of_crossbar_ports = 15 generate
3407
3408	-- crossbit du bit 0 de donnée
3409
3410	Data0_Crossbit: Crossbit
3411	GENERIC MAP(number_of_ports => 15)
3412	PORT MAP(
3413
3414	reset => reset,
3415	clk=>clk,
3416	Control => Ctrl_buf,
3417	Data_In(1) => Port1_in(0),
3418	Data_In(2) => Port2_in(0),
3419	Data_In(3) => Port3_in(0),
3420	Data_In(4) => Port4_in(0),
3421	Data_In(5) => Port5_in(0),
3422	Data_In(6) => Port6_in(0),
3423	Data_In(7) => Port7_in(0),
3424	Data_In(8) => Port8_in(0),
3425	Data_In(9) => Port9_in(0),
3426	Data_In(10) => Port10_in(0),
3427	Data_In(11) => Port11_in(0),
3428	Data_In(12) => Port12_in(0),
3429	Data_In(13) => Port13_in(0),
3430	Data_In(14) => Port14_in(0),
3431	Data_In(15) => Port15_in(0),
3432	Data_out(1)=> Port1_out(0),
3433	Data_out(2)=> Port2_out(0),
3434	Data_out(3)=> Port3_out(0),
3435	Data_out(4)=> Port4_out(0),
3436	Data_out(5)=> Port5_out(0),
3437	Data_out(6)=> Port6_out(0),
3438	Data_out(7)=> Port7_out(0),
3439	Data_out(8)=> Port8_out(0),
3440	Data_out(9)=> Port9_out(0),
3441	Data_out(10)=> Port10_out(0),
3442	Data_out(11)=> Port11_out(0),
3443	Data_out(12)=> Port12_out(0),
3444	Data_out(13)=> Port13_out(0),
3445	Data_out(14)=> Port14_out(0),
3446	Data_out(15)=> Port15_out(0)
3447
3448	);
3449	-- crossbit du bit 1 de donnée
3450
3451	Data1_Crossbit: Crossbit
3452	GENERIC MAP(number_of_ports => 15)
3453	PORT MAP(
3454
3455	reset => reset,
3456	clk=>clk,
3457	Control => Ctrl_buf,
3458	Data_In(1) => Port1_in(1),
3459	Data_In(2) => Port2_in(1),
3460	Data_In(3) => Port3_in(1),
3461	Data_In(4) => Port4_in(1),
3462	Data_In(5) => Port5_in(1),
3463	Data_In(6) => Port6_in(1),
3464	Data_In(7) => Port7_in(1),
3465	Data_In(8) => Port8_in(1),
3466	Data_In(9) => Port9_in(1),
3467	Data_In(10) => Port10_in(1),
3468	Data_In(11) => Port11_in(1),
3469	Data_In(12) => Port12_in(1),
3470	Data_In(13) => Port13_in(1),
3471	Data_In(14) => Port14_in(1),
3472	Data_In(15) => Port15_in(1),
3473	Data_out(1)=> Port1_out(1),
3474	Data_out(2)=> Port2_out(1),
3475	Data_out(3)=> Port3_out(1),
3476	Data_out(4)=> Port4_out(1),
3477	Data_out(5)=> Port5_out(1),
3478	Data_out(6)=> Port6_out(1),
3479	Data_out(7)=> Port7_out(1),
3480	Data_out(8)=> Port8_out(1),
3481	Data_out(9)=> Port9_out(1),
3482	Data_out(10)=> Port10_out(1),
3483	Data_out(11)=> Port11_out(1),
3484	Data_out(12)=> Port12_out(1),
3485	Data_out(13)=> Port13_out(1),
3486	Data_out(14)=> Port14_out(1),
3487	Data_out(15)=> Port15_out(1)
3488
3489	);
3490	-- crossbit du bit 2 de donnée
3491
3492	Data2_Crossbit: Crossbit
3493	GENERIC MAP(number_of_ports => 15)
3494	PORT MAP(
3495
3496	reset => reset,
3497	clk=>clk,
3498	Control => Ctrl_buf,
3499	Data_In(1) => Port1_in(2),
3500	Data_In(2) => Port2_in(2),
3501	Data_In(3) => Port3_in(2),
3502	Data_In(4) => Port4_in(2),
3503	Data_In(5) => Port5_in(2),
3504	Data_In(6) => Port6_in(2),
3505	Data_In(7) => Port7_in(2),
3506	Data_In(8) => Port8_in(2),
3507	Data_In(9) => Port9_in(2),
3508	Data_In(10) => Port10_in(2),
3509	Data_In(11) => Port11_in(2),
3510	Data_In(12) => Port12_in(2),
3511	Data_In(13) => Port13_in(2),
3512	Data_In(14) => Port14_in(2),
3513	Data_In(15) => Port15_in(2),
3514	Data_out(1)=> Port1_out(2),
3515	Data_out(2)=> Port2_out(2),
3516	Data_out(3)=> Port3_out(2),
3517	Data_out(4)=> Port4_out(2),
3518	Data_out(5)=> Port5_out(2),
3519	Data_out(6)=> Port6_out(2),
3520	Data_out(7)=> Port7_out(2),
3521	Data_out(8)=> Port8_out(2),
3522	Data_out(9)=> Port9_out(2),
3523	Data_out(10)=> Port10_out(2),
3524	Data_out(11)=> Port11_out(2),
3525	Data_out(12)=> Port12_out(2),
3526	Data_out(13)=> Port13_out(2),
3527	Data_out(14)=> Port14_out(2),
3528	Data_out(15)=> Port15_out(2)
3529
3530	);
3531	-- crossbit du bit 3 de donnée
3532
3533	Data3_Crossbit: Crossbit
3534	GENERIC MAP(number_of_ports => 15)
3535	PORT MAP(
3536
3537	reset => reset,
3538	clk=>clk,
3539	Control => Ctrl_buf,
3540	Data_In(1) => Port1_in(3),
3541	Data_In(2) => Port2_in(3),
3542	Data_In(3) => Port3_in(3),
3543	Data_In(4) => Port4_in(3),
3544	Data_In(5) => Port5_in(3),
3545	Data_In(6) => Port6_in(3),
3546	Data_In(7) => Port7_in(3),
3547	Data_In(8) => Port8_in(3),
3548	Data_In(9) => Port9_in(3),
3549	Data_In(10) => Port10_in(3),
3550	Data_In(11) => Port11_in(3),
3551	Data_In(12) => Port12_in(3),
3552	Data_In(13) => Port13_in(3),
3553	Data_In(14) => Port14_in(3),
3554	Data_In(15) => Port15_in(3),
3555	Data_out(1)=> Port1_out(3),
3556	Data_out(2)=> Port2_out(3),
3557	Data_out(3)=> Port3_out(3),
3558	Data_out(4)=> Port4_out(3),
3559	Data_out(5)=> Port5_out(3),
3560	Data_out(6)=> Port6_out(3),
3561	Data_out(7)=> Port7_out(3),
3562	Data_out(8)=> Port8_out(3),
3563	Data_out(9)=> Port9_out(3),
3564	Data_out(10)=> Port10_out(3),
3565	Data_out(11)=> Port11_out(3),
3566	Data_out(12)=> Port12_out(3),
3567	Data_out(13)=> Port13_out(3),
3568	Data_out(14)=> Port14_out(3),
3569	Data_out(15)=> Port15_out(3)
3570
3571	);
3572	-- crossbit du bit 4 de donnée
3573
3574	Data4_Crossbit: Crossbit
3575	GENERIC MAP(number_of_ports => 15)
3576	PORT MAP(
3577
3578	reset => reset,
3579	clk=>clk,
3580	Control => Ctrl_buf,
3581	Data_In(1) => Port1_in(4),
3582	Data_In(2) => Port2_in(4),
3583	Data_In(3) => Port3_in(4),
3584	Data_In(4) => Port4_in(4),
3585	Data_In(5) => Port5_in(4),
3586	Data_In(6) => Port6_in(4),
3587	Data_In(7) => Port7_in(4),
3588	Data_In(8) => Port8_in(4),
3589	Data_In(9) => Port9_in(4),
3590	Data_In(10) => Port10_in(4),
3591	Data_In(11) => Port11_in(4),
3592	Data_In(12) => Port12_in(4),
3593	Data_In(13) => Port13_in(4),
3594	Data_In(14) => Port14_in(4),
3595	Data_In(15) => Port15_in(4),
3596	Data_out(1)=> Port1_out(4),
3597	Data_out(2)=> Port2_out(4),
3598	Data_out(3)=> Port3_out(4),
3599	Data_out(4)=> Port4_out(4),
3600	Data_out(5)=> Port5_out(4),
3601	Data_out(6)=> Port6_out(4),
3602	Data_out(7)=> Port7_out(4),
3603	Data_out(8)=> Port8_out(4),
3604	Data_out(9)=> Port9_out(4),
3605	Data_out(10)=> Port10_out(4),
3606	Data_out(11)=> Port11_out(4),
3607	Data_out(12)=> Port12_out(4),
3608	Data_out(13)=> Port13_out(4),
3609	Data_out(14)=> Port14_out(4),
3610	Data_out(15)=> Port15_out(4)
3611
3612	);
3613	-- crossbit du bit 5 de donnée
3614
3615	Data5_Crossbit: Crossbit
3616	GENERIC MAP(number_of_ports => 15)
3617	PORT MAP(
3618
3619	reset => reset,
3620	clk=>clk,
3621	Control => Ctrl_buf,
3622	Data_In(1) => Port1_in(5),
3623	Data_In(2) => Port2_in(5),
3624	Data_In(3) => Port3_in(5),
3625	Data_In(4) => Port4_in(5),
3626	Data_In(5) => Port5_in(5),
3627	Data_In(6) => Port6_in(5),
3628	Data_In(7) => Port7_in(5),
3629	Data_In(8) => Port8_in(5),
3630	Data_In(9) => Port9_in(5),
3631	Data_In(10) => Port10_in(5),
3632	Data_In(11) => Port11_in(5),
3633	Data_In(12) => Port12_in(5),
3634	Data_In(13) => Port13_in(5),
3635	Data_In(14) => Port14_in(5),
3636	Data_In(15) => Port15_in(5),
3637	Data_out(1)=> Port1_out(5),
3638	Data_out(2)=> Port2_out(5),
3639	Data_out(3)=> Port3_out(5),
3640	Data_out(4)=> Port4_out(5),
3641	Data_out(5)=> Port5_out(5),
3642	Data_out(6)=> Port6_out(5),
3643	Data_out(7)=> Port7_out(5),
3644	Data_out(8)=> Port8_out(5),
3645	Data_out(9)=> Port9_out(5),
3646	Data_out(10)=> Port10_out(5),
3647	Data_out(11)=> Port11_out(5),
3648	Data_out(12)=> Port12_out(5),
3649	Data_out(13)=> Port13_out(5),
3650	Data_out(14)=> Port14_out(5),
3651	Data_out(15)=> Port15_out(5)
3652
3653	);
3654	-- crossbit du bit 6 de donnée
3655
3656	Data6_Crossbit: Crossbit
3657	GENERIC MAP(number_of_ports => 15)
3658	PORT MAP(
3659
3660	reset => reset,
3661	clk=>clk,
3662	Control => Ctrl_buf,
3663	Data_In(1) => Port1_in(6),
3664	Data_In(2) => Port2_in(6),
3665	Data_In(3) => Port3_in(6),
3666	Data_In(4) => Port4_in(6),
3667	Data_In(5) => Port5_in(6),
3668	Data_In(6) => Port6_in(6),
3669	Data_In(7) => Port7_in(6),
3670	Data_In(8) => Port8_in(6),
3671	Data_In(9) => Port9_in(6),
3672	Data_In(10) => Port10_in(6),
3673	Data_In(11) => Port11_in(6),
3674	Data_In(12) => Port12_in(6),
3675	Data_In(13) => Port13_in(6),
3676	Data_In(14) => Port14_in(6),
3677	Data_In(15) => Port15_in(6),
3678	Data_out(1)=> Port1_out(6),
3679	Data_out(2)=> Port2_out(6),
3680	Data_out(3)=> Port3_out(6),
3681	Data_out(4)=> Port4_out(6),
3682	Data_out(5)=> Port5_out(6),
3683	Data_out(6)=> Port6_out(6),
3684	Data_out(7)=> Port7_out(6),
3685	Data_out(8)=> Port8_out(6),
3686	Data_out(9)=> Port9_out(6),
3687	Data_out(10)=> Port10_out(6),
3688	Data_out(11)=> Port11_out(6),
3689	Data_out(12)=> Port12_out(6),
3690	Data_out(13)=> Port13_out(6),
3691	Data_out(14)=> Port14_out(6),
3692	Data_out(15)=> Port15_out(6)
3693
3694	);
3695	-- crossbit du bit 7 de donnée
3696
3697	Data7_Crossbit: Crossbit
3698	GENERIC MAP(number_of_ports => 15)
3699	PORT MAP(
3700
3701	reset => reset,
3702	clk=>clk,
3703	Control => Ctrl_buf,
3704	Data_In(1) => Port1_in(7),
3705	Data_In(2) => Port2_in(7),
3706	Data_In(3) => Port3_in(7),
3707	Data_In(4) => Port4_in(7),
3708	Data_In(5) => Port5_in(7),
3709	Data_In(6) => Port6_in(7),
3710	Data_In(7) => Port7_in(7),
3711	Data_In(8) => Port8_in(7),
3712	Data_In(9) => Port9_in(7),
3713	Data_In(10) => Port10_in(7),
3714	Data_In(11) => Port11_in(7),
3715	Data_In(12) => Port12_in(7),
3716	Data_In(13) => Port13_in(7),
3717	Data_In(14) => Port14_in(7),
3718	Data_In(15) => Port15_in(7),
3719	Data_out(1)=> Port1_out(7),
3720	Data_out(2)=> Port2_out(7),
3721	Data_out(3)=> Port3_out(7),
3722	Data_out(4)=> Port4_out(7),
3723	Data_out(5)=> Port5_out(7),
3724	Data_out(6)=> Port6_out(7),
3725	Data_out(7)=> Port7_out(7),
3726	Data_out(8)=> Port8_out(7),
3727	Data_out(9)=> Port9_out(7),
3728	Data_out(10)=> Port10_out(7),
3729	Data_out(11)=> Port11_out(7),
3730	Data_out(12)=> Port12_out(7),
3731	Data_out(13)=> Port13_out(7),
3732	Data_out(14)=> Port14_out(7),
3733	Data_out(15)=> Port15_out(7)
3734
3735	);
3736	-- crossbit du pulse_out 15 ports
3737
3738	Pulse_out_Crossbit15: Crossbit
3739	GENERIC MAP(number_of_ports => 15)
3740	PORT MAP(
3741
3742	reset => reset,
3743	clk=>clk,
3744	Control => Ctrl_buf,
3745	Data_In(1) => Port1_pulse_in,
3746	Data_In(2) => Port2_pulse_in,
3747	Data_In(3) => Port3_pulse_in,
3748	Data_In(4) => Port4_pulse_in,
3749	Data_In(5) => Port5_pulse_in,
3750	Data_In(6) => Port6_pulse_in,
3751	Data_In(7) => Port7_pulse_in,
3752	Data_In(8) => Port8_pulse_in,
3753	Data_In(9) => Port9_pulse_in,
3754	Data_In(10) => Port10_pulse_in,
3755	Data_In(11) => Port11_pulse_in,
3756	Data_In(12) => Port12_pulse_in,
3757	Data_In(13) => Port13_pulse_in,
3758	Data_In(14) => Port14_pulse_in,
3759	Data_In(15) => Port15_pulse_in,
3760	Data_out(1) => Port1_pulse_out,
3761	Data_out(2) => Port2_pulse_out,
3762	Data_out(3) => Port3_pulse_out,
3763	Data_out(4) => Port4_pulse_out,
3764	Data_out(5) => Port5_pulse_out,
3765	Data_out(6) => Port6_pulse_out,
3766	Data_out(7) => Port7_pulse_out,
3767	Data_out(8) => Port8_pulse_out,
3768	Data_out(9) => Port9_pulse_out,
3769	Data_out(10) => Port10_pulse_out,
3770	Data_out(11) => Port11_pulse_out,
3771	Data_out(12) => Port12_pulse_out,
3772	Data_out(13) => Port13_pulse_out,
3773	Data_out(14) => Port14_pulse_out,
3774	Data_out(15) => Port15_pulse_out
3775
3776	);
3777	end generate crossbar15x15;
3778
3779
3780	--======================crossbar 16 ports=======================
3781
3782	crossbar16x16 : if number_of_crossbar_ports = 16 generate
3783
3784	-- crossbit du bit 0 de donnée
3785
3786	Data0_Crossbit: Crossbit
3787	GENERIC MAP(number_of_ports => 16)
3788	PORT MAP(
3789
3790	reset => reset,
3791	clk=>clk,
3792	Control => Ctrl_buf,
3793	Data_In(1) => Port1_in(0),
3794	Data_In(2) => Port2_in(0),
3795	Data_In(3) => Port3_in(0),
3796	Data_In(4) => Port4_in(0),
3797	Data_In(5) => Port5_in(0),
3798	Data_In(6) => Port6_in(0),
3799	Data_In(7) => Port7_in(0),
3800	Data_In(8) => Port8_in(0),
3801	Data_In(9) => Port9_in(0),
3802	Data_In(10) => Port10_in(0),
3803	Data_In(11) => Port11_in(0),
3804	Data_In(12) => Port12_in(0),
3805	Data_In(13) => Port13_in(0),
3806	Data_In(14) => Port14_in(0),
3807	Data_In(15) => Port15_in(0),
3808	Data_In(16) => Port16_in(0),
3809	Data_out(1)=> Port1_out(0),
3810	Data_out(2)=> Port2_out(0),
3811	Data_out(3)=> Port3_out(0),
3812	Data_out(4)=> Port4_out(0),
3813	Data_out(5)=> Port5_out(0),
3814	Data_out(6)=> Port6_out(0),
3815	Data_out(7)=> Port7_out(0),
3816	Data_out(8)=> Port8_out(0),
3817	Data_out(9)=> Port9_out(0),
3818	Data_out(10)=> Port10_out(0),
3819	Data_out(11)=> Port11_out(0),
3820	Data_out(12)=> Port12_out(0),
3821	Data_out(13)=> Port13_out(0),
3822	Data_out(14)=> Port14_out(0),
3823	Data_out(15)=> Port15_out(0),
3824	Data_out(16)=> Port16_out(0)
3825
3826	);
3827	-- crossbit du bit 1 de donnée
3828
3829	Data1_Crossbit: Crossbit
3830	GENERIC MAP(number_of_ports => 16)
3831	PORT MAP(
3832
3833	reset => reset,
3834	clk=>clk,
3835	Control => Ctrl_buf,
3836	Data_In(1) => Port1_in(1),
3837	Data_In(2) => Port2_in(1),
3838	Data_In(3) => Port3_in(1),
3839	Data_In(4) => Port4_in(1),
3840	Data_In(5) => Port5_in(1),
3841	Data_In(6) => Port6_in(1),
3842	Data_In(7) => Port7_in(1),
3843	Data_In(8) => Port8_in(1),
3844	Data_In(9) => Port9_in(1),
3845	Data_In(10) => Port10_in(1),
3846	Data_In(11) => Port11_in(1),
3847	Data_In(12) => Port12_in(1),
3848	Data_In(13) => Port13_in(1),
3849	Data_In(14) => Port14_in(1),
3850	Data_In(15) => Port15_in(1),
3851	Data_In(16) => Port16_in(1),
3852	Data_out(1)=> Port1_out(1),
3853	Data_out(2)=> Port2_out(1),
3854	Data_out(3)=> Port3_out(1),
3855	Data_out(4)=> Port4_out(1),
3856	Data_out(5)=> Port5_out(1),
3857	Data_out(6)=> Port6_out(1),
3858	Data_out(7)=> Port7_out(1),
3859	Data_out(8)=> Port8_out(1),
3860	Data_out(9)=> Port9_out(1),
3861	Data_out(10)=> Port10_out(1),
3862	Data_out(11)=> Port11_out(1),
3863	Data_out(12)=> Port12_out(1),
3864	Data_out(13)=> Port13_out(1),
3865	Data_out(14)=> Port14_out(1),
3866	Data_out(15)=> Port15_out(1),
3867	Data_out(16)=> Port16_out(1)
3868
3869	);
3870	-- crossbit du bit 2 de donnée
3871
3872	Data2_Crossbit: Crossbit
3873	GENERIC MAP(number_of_ports => 16)
3874	PORT MAP(
3875
3876	reset => reset,
3877	clk=>clk,
3878	Control => Ctrl_buf,
3879	Data_In(1) => Port1_in(2),
3880	Data_In(2) => Port2_in(2),
3881	Data_In(3) => Port3_in(2),
3882	Data_In(4) => Port4_in(2),
3883	Data_In(5) => Port5_in(2),
3884	Data_In(6) => Port6_in(2),
3885	Data_In(7) => Port7_in(2),
3886	Data_In(8) => Port8_in(2),
3887	Data_In(9) => Port9_in(2),
3888	Data_In(10) => Port10_in(2),
3889	Data_In(11) => Port11_in(2),
3890	Data_In(12) => Port12_in(2),
3891	Data_In(13) => Port13_in(2),
3892	Data_In(14) => Port14_in(2),
3893	Data_In(15) => Port15_in(2),
3894	Data_In(16) => Port16_in(2),
3895	Data_out(1)=> Port1_out(2),
3896	Data_out(2)=> Port2_out(2),
3897	Data_out(3)=> Port3_out(2),
3898	Data_out(4)=> Port4_out(2),
3899	Data_out(5)=> Port5_out(2),
3900	Data_out(6)=> Port6_out(2),
3901	Data_out(7)=> Port7_out(2),
3902	Data_out(8)=> Port8_out(2),
3903	Data_out(9)=> Port9_out(2),
3904	Data_out(10)=> Port10_out(2),
3905	Data_out(11)=> Port11_out(2),
3906	Data_out(12)=> Port12_out(2),
3907	Data_out(13)=> Port13_out(2),
3908	Data_out(14)=> Port14_out(2),
3909	Data_out(15)=> Port15_out(2),
3910	Data_out(16)=> Port16_out(2)
3911
3912	);
3913	-- crossbit du bit 3 de donnée
3914
3915	Data3_Crossbit: Crossbit
3916	GENERIC MAP(number_of_ports => 16)
3917	PORT MAP(
3918
3919	reset => reset,
3920	clk=>clk,
3921	Control => Ctrl_buf,
3922	Data_In(1) => Port1_in(3),
3923	Data_In(2) => Port2_in(3),
3924	Data_In(3) => Port3_in(3),
3925	Data_In(4) => Port4_in(3),
3926	Data_In(5) => Port5_in(3),
3927	Data_In(6) => Port6_in(3),
3928	Data_In(7) => Port7_in(3),
3929	Data_In(8) => Port8_in(3),
3930	Data_In(9) => Port9_in(3),
3931	Data_In(10) => Port10_in(3),
3932	Data_In(11) => Port11_in(3),
3933	Data_In(12) => Port12_in(3),
3934	Data_In(13) => Port13_in(3),
3935	Data_In(14) => Port14_in(3),
3936	Data_In(15) => Port15_in(3),
3937	Data_In(16) => Port16_in(3),
3938	Data_out(1)=> Port1_out(3),
3939	Data_out(2)=> Port2_out(3),
3940	Data_out(3)=> Port3_out(3),
3941	Data_out(4)=> Port4_out(3),
3942	Data_out(5)=> Port5_out(3),
3943	Data_out(6)=> Port6_out(3),
3944	Data_out(7)=> Port7_out(3),
3945	Data_out(8)=> Port8_out(3),
3946	Data_out(9)=> Port9_out(3),
3947	Data_out(10)=> Port10_out(3),
3948	Data_out(11)=> Port11_out(3),
3949	Data_out(12)=> Port12_out(3),
3950	Data_out(13)=> Port13_out(3),
3951	Data_out(14)=> Port14_out(3),
3952	Data_out(15)=> Port15_out(3),
3953	Data_out(16)=> Port16_out(3)
3954
3955	);
3956	-- crossbit du bit 4 de donnée
3957
3958	Data4_Crossbit: Crossbit
3959	GENERIC MAP(number_of_ports => 16)
3960	PORT MAP(
3961
3962	reset => reset,
3963	clk=>clk,
3964	Control => Ctrl_buf,
3965	Data_In(1) => Port1_in(4),
3966	Data_In(2) => Port2_in(4),
3967	Data_In(3) => Port3_in(4),
3968	Data_In(4) => Port4_in(4),
3969	Data_In(5) => Port5_in(4),
3970	Data_In(6) => Port6_in(4),
3971	Data_In(7) => Port7_in(4),
3972	Data_In(8) => Port8_in(4),
3973	Data_In(9) => Port9_in(4),
3974	Data_In(10) => Port10_in(4),
3975	Data_In(11) => Port11_in(4),
3976	Data_In(12) => Port12_in(4),
3977	Data_In(13) => Port13_in(4),
3978	Data_In(14) => Port14_in(4),
3979	Data_In(15) => Port15_in(4),
3980	Data_In(16) => Port16_in(4),
3981	Data_out(1)=> Port1_out(4),
3982	Data_out(2)=> Port2_out(4),
3983	Data_out(3)=> Port3_out(4),
3984	Data_out(4)=> Port4_out(4),
3985	Data_out(5)=> Port5_out(4),
3986	Data_out(6)=> Port6_out(4),
3987	Data_out(7)=> Port7_out(4),
3988	Data_out(8)=> Port8_out(4),
3989	Data_out(9)=> Port9_out(4),
3990	Data_out(10)=> Port10_out(4),
3991	Data_out(11)=> Port11_out(4),
3992	Data_out(12)=> Port12_out(4),
3993	Data_out(13)=> Port13_out(4),
3994	Data_out(14)=> Port14_out(4),
3995	Data_out(15)=> Port15_out(4),
3996	Data_out(16)=> Port16_out(4)
3997
3998	);
3999	-- crossbit du bit 5 de donnée
4000
4001	Data5_Crossbit: Crossbit
4002	GENERIC MAP(number_of_ports => 16)
4003	PORT MAP(
4004
4005	reset => reset,
4006	clk=>clk,
4007	Control => Ctrl_buf,
4008	Data_In(1) => Port1_in(5),
4009	Data_In(2) => Port2_in(5),
4010	Data_In(3) => Port3_in(5),
4011	Data_In(4) => Port4_in(5),
4012	Data_In(5) => Port5_in(5),
4013	Data_In(6) => Port6_in(5),
4014	Data_In(7) => Port7_in(5),
4015	Data_In(8) => Port8_in(5),
4016	Data_In(9) => Port9_in(5),
4017	Data_In(10) => Port10_in(5),
4018	Data_In(11) => Port11_in(5),
4019	Data_In(12) => Port12_in(5),
4020	Data_In(13) => Port13_in(5),
4021	Data_In(14) => Port14_in(5),
4022	Data_In(15) => Port15_in(5),
4023	Data_In(16) => Port16_in(5),
4024	Data_out(1)=> Port1_out(5),
4025	Data_out(2)=> Port2_out(5),
4026	Data_out(3)=> Port3_out(5),
4027	Data_out(4)=> Port4_out(5),
4028	Data_out(5)=> Port5_out(5),
4029	Data_out(6)=> Port6_out(5),
4030	Data_out(7)=> Port7_out(5),
4031	Data_out(8)=> Port8_out(5),
4032	Data_out(9)=> Port9_out(5),
4033	Data_out(10)=> Port10_out(5),
4034	Data_out(11)=> Port11_out(5),
4035	Data_out(12)=> Port12_out(5),
4036	Data_out(13)=> Port13_out(5),
4037	Data_out(14)=> Port14_out(5),
4038	Data_out(15)=> Port15_out(5),
4039	Data_out(16)=> Port16_out(5)
4040
4041	);
4042	-- crossbit du bit 6 de donnée
4043
4044	Data6_Crossbit: Crossbit
4045	GENERIC MAP(number_of_ports => 16)
4046	PORT MAP(
4047
4048	reset => reset,
4049	clk=>clk,
4050	Control => Ctrl_buf,
4051	Data_In(1) => Port1_in(6),
4052	Data_In(2) => Port2_in(6),
4053	Data_In(3) => Port3_in(6),
4054	Data_In(4) => Port4_in(6),
4055	Data_In(5) => Port5_in(6),
4056	Data_In(6) => Port6_in(6),
4057	Data_In(7) => Port7_in(6),
4058	Data_In(8) => Port8_in(6),
4059	Data_In(9) => Port9_in(6),
4060	Data_In(10) => Port10_in(6),
4061	Data_In(11) => Port11_in(6),
4062	Data_In(12) => Port12_in(6),
4063	Data_In(13) => Port13_in(6),
4064	Data_In(14) => Port14_in(6),
4065	Data_In(15) => Port15_in(6),
4066	Data_In(16) => Port16_in(6),
4067	Data_out(1)=> Port1_out(6),
4068	Data_out(2)=> Port2_out(6),
4069	Data_out(3)=> Port3_out(6),
4070	Data_out(4)=> Port4_out(6),
4071	Data_out(5)=> Port5_out(6),
4072	Data_out(6)=> Port6_out(6),
4073	Data_out(7)=> Port7_out(6),
4074	Data_out(8)=> Port8_out(6),
4075	Data_out(9)=> Port9_out(6),
4076	Data_out(10)=> Port10_out(6),
4077	Data_out(11)=> Port11_out(6),
4078	Data_out(12)=> Port12_out(6),
4079	Data_out(13)=> Port13_out(6),
4080	Data_out(14)=> Port14_out(6),
4081	Data_out(15)=> Port15_out(6),
4082	Data_out(16)=> Port16_out(6)
4083
4084	);
4085	-- crossbit du bit 7 de donnée
4086
4087	Data7_Crossbit: Crossbit
4088	GENERIC MAP(number_of_ports => 16)
4089	PORT MAP(
4090
4091	reset => reset,
4092	clk=>clk,
4093	Control => Ctrl_buf,
4094	Data_In(1) => Port1_in(7),
4095	Data_In(2) => Port2_in(7),
4096	Data_In(3) => Port3_in(7),
4097	Data_In(4) => Port4_in(7),
4098	Data_In(5) => Port5_in(7),
4099	Data_In(6) => Port6_in(7),
4100	Data_In(7) => Port7_in(7),
4101	Data_In(8) => Port8_in(7),
4102	Data_In(9) => Port9_in(7),
4103	Data_In(10) => Port10_in(7),
4104	Data_In(11) => Port11_in(7),
4105	Data_In(12) => Port12_in(7),
4106	Data_In(13) => Port13_in(7),
4107	Data_In(14) => Port14_in(7),
4108	Data_In(15) => Port15_in(7),
4109	Data_In(16) => Port16_in(7),
4110	Data_out(1)=> Port1_out(7),
4111	Data_out(2)=> Port2_out(7),
4112	Data_out(3)=> Port3_out(7),
4113	Data_out(4)=> Port4_out(7),
4114	Data_out(5)=> Port5_out(7),
4115	Data_out(6)=> Port6_out(7),
4116	Data_out(7)=> Port7_out(7),
4117	Data_out(8)=> Port8_out(7),
4118	Data_out(9)=> Port9_out(7),
4119	Data_out(10)=> Port10_out(7),
4120	Data_out(11)=> Port11_out(7),
4121	Data_out(12)=> Port12_out(7),
4122	Data_out(13)=> Port13_out(7),
4123	Data_out(14)=> Port14_out(7),
4124	Data_out(15)=> Port15_out(7),
4125	Data_out(16)=> Port16_out(7)
4126
4127	);
4128	-- crossbit du pulse_out 16 ports
4129
4130	Pulse_out_Crossbit16: Crossbit
4131	GENERIC MAP(number_of_ports => 16)
4132	PORT MAP(
4133
4134	reset => reset,
4135	clk=>clk,
4136	Control => Ctrl_buf,
4137	Data_In(1) => Port1_pulse_in,
4138	Data_In(2) => Port2_pulse_in,
4139	Data_In(3) => Port3_pulse_in,
4140	Data_In(4) => Port4_pulse_in,
4141	Data_In(5) => Port5_pulse_in,
4142	Data_In(6) => Port6_pulse_in,
4143	Data_In(7) => Port7_pulse_in,
4144	Data_In(8) => Port8_pulse_in,
4145	Data_In(9) => Port9_pulse_in,
4146	Data_In(10) => Port10_pulse_in,
4147	Data_In(11) => Port11_pulse_in,
4148	Data_In(12) => Port12_pulse_in,
4149	Data_In(13) => Port13_pulse_in,
4150	Data_In(14) => Port14_pulse_in,
4151	Data_In(15) => Port15_pulse_in,
4152	Data_In(16) => Port16_pulse_in,
4153	Data_out(1) => Port1_pulse_out,
4154	Data_out(2) => Port2_pulse_out,
4155	Data_out(3) => Port3_pulse_out,
4156	Data_out(4) => Port4_pulse_out,
4157	Data_out(5) => Port5_pulse_out,
4158	Data_out(6) => Port6_pulse_out,
4159	Data_out(7) => Port7_pulse_out,
4160	Data_out(8) => Port8_pulse_out,
4161	Data_out(9) => Port9_pulse_out,
4162	Data_out(10) => Port10_pulse_out,
4163	Data_out(11) => Port11_pulse_out,
4164	Data_out(12) => Port12_pulse_out,
4165	Data_out(13) => Port13_pulse_out,
4166	Data_out(14) => Port14_pulse_out,
4167	Data_out(15) => Port15_pulse_out,
4168	Data_out(16) => Port16_pulse_out
4169
4170	);
4171	end generate crossbar16x16;
4172
4173	end Behavioral;
4174

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source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd

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