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Changeset 65 for PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd
- Timestamp:
- Apr 22, 2013, 11:35:33 AM (11 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd
r22 r65 1 1 ---------------------------------------------------------------------------------- 2 2 -- Company: 3 -- Engineer: KIEGAING EMMANUEL 3 -- Engineer: KIEGAING EMMANUEL / GAMOM NGOUNOU 4 4 -- 5 5 -- Create Date: 11:48:18 06/19/2011 … … 16 16 -- a été retiré les signaux inutilisées comme fp, port_source, etc... 17 17 -- Revision 0.01 - File Created 18 -- Additional Comments: 18 -- Revision 0.02 Ajout des signaux clk et reset 19 -- Additional Comments: pour la gestion du pipeline 19 20 -- 20 21 ---------------------------------------------------------------------------------- … … 33 34 generic 34 35 ( 35 number_of_crossbar_ports: positive := 436 number_of_crossbar_ports: positive := 8 36 37 ); 37 Port ( Port1_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 38 Port ( clk : in STD_LOGIC; 39 reset : in STD_LOGIC; --pour gérer le pipeline 40 Port1_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 38 41 Port2_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 39 42 Port3_in : in STD_LOGIC_VECTOR (Word-1 downto 0); … … 115 118 number_of_ports : positive := 4 116 119 ); 117 Port ( Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); 120 Port ( clk,reset : in std_logic; 121 Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); 118 122 Data_In : in STD_LOGIC_VECTOR (number_of_ports downto 1); 119 123 Data_out : out STD_LOGIC_VECTOR (number_of_ports downto 1)); 120 124 END COMPONENT; 121 125 signal ctrl_buf: STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1):=(others=>'0'); 126 --signal ctrl_chg:std_logic:='0'; 122 127 begin 123 128 -- La matrice interconnectee 124 129 -- le circuit genere depend du parametre generique nombre de ports 125 130 --ctrl_chg<=all_zeros(ctrl_buf xor ctrl); --sur chaque changement du mot de contrôle, mettre à jour ce registre 131 --ctrl_proc:process(ctrl) 132 -- begin 133 ctrl_buf<=ctrl; 134 -- end process; 126 135 --======================crossbar 2 ports======================= 127 136 … … 133 142 GENERIC MAP(number_of_ports => 2) 134 143 PORT MAP( 135 136 Control => Ctrl, 144 reset => reset, 145 clk =>clk, 146 147 Control => Ctrl_buf, 137 148 Data_In(1) => Port1_in(0), 138 149 Data_In(2) => Port2_in(0), … … 146 157 GENERIC MAP(number_of_ports => 2) 147 158 PORT MAP( 148 149 Control => Ctrl, 159 reset => reset, 160 clk =>clk, 161 162 Control => Ctrl_buf, 150 163 Data_In(1) => Port1_in(1), 151 164 Data_In(2) => Port2_in(1), … … 159 172 GENERIC MAP(number_of_ports => 2) 160 173 PORT MAP( 161 162 Control => Ctrl, 174 reset => reset, 175 clk =>clk, 176 177 Control => Ctrl_buf, 163 178 Data_In(1) => Port1_in(2), 164 179 Data_In(2) => Port2_in(2), … … 172 187 GENERIC MAP(number_of_ports => 2) 173 188 PORT MAP( 174 175 Control => Ctrl, 189 reset => reset, 190 clk =>clk, 191 192 Control => Ctrl_buf, 176 193 Data_In(1) => Port1_in(3), 177 194 Data_In(2) => Port2_in(3), … … 186 203 PORT MAP( 187 204 188 Control => Ctrl, 205 reset => reset, 206 clk =>clk, 207 208 Control => Ctrl_buf, 189 209 Data_In(1) => Port1_in(4), 190 210 Data_In(2) => Port2_in(4), … … 199 219 PORT MAP( 200 220 201 Control => Ctrl, 221 reset => reset, 222 clk=>clk, 223 Control => Ctrl_buf, 202 224 Data_In(1) => Port1_in(5), 203 225 Data_In(2) => Port2_in(5), … … 212 234 PORT MAP( 213 235 214 Control => Ctrl, 236 reset => reset, 237 clk=>clk, 238 Control => Ctrl_buf, 215 239 Data_In(1) => Port1_in(6), 216 240 Data_In(2) => Port2_in(6), … … 225 249 PORT MAP( 226 250 227 Control => Ctrl, 251 reset => reset, 252 clk=>clk, 253 Control => Ctrl_buf, 228 254 Data_In(1) => Port1_in(7), 229 255 Data_In(2) => Port2_in(7), … … 237 263 GENERIC MAP(number_of_ports => 2) 238 264 PORT MAP( 239 240 Control => Ctrl, 265 reset => reset, 266 clk =>clk, 267 268 Control => Ctrl_buf, 241 269 Data_In(1) => Port1_pulse_in, 242 270 Data_In(2) => Port2_pulse_in, … … 258 286 PORT MAP( 259 287 260 Control => Ctrl, 288 reset => reset, 289 clk =>clk, 290 291 Control => Ctrl_buf, 261 292 Data_In(1) => Port1_in(0), 262 293 Data_In(2) => Port2_in(0), … … 272 303 GENERIC MAP(number_of_ports => 3) 273 304 PORT MAP( 274 275 Control => Ctrl, 305 reset => reset, 306 clk =>clk, 307 308 Control => Ctrl_buf, 276 309 Data_In(1) => Port1_in(1), 277 310 Data_In(2) => Port2_in(1), … … 288 321 PORT MAP( 289 322 290 Control => Ctrl, 323 reset => reset, 324 clk=>clk, 325 Control => Ctrl_buf, 291 326 Data_In(1) => Port1_in(2), 292 327 Data_In(2) => Port2_in(2), … … 302 337 GENERIC MAP(number_of_ports => 3) 303 338 PORT MAP( 304 305 Control => Ctrl, 339 reset => reset, 340 clk =>clk, 341 342 Control => Ctrl_buf, 306 343 Data_In(1) => Port1_in(3), 307 344 Data_In(2) => Port2_in(3), … … 318 355 PORT MAP( 319 356 320 Control => Ctrl, 357 reset => reset, 358 clk=>clk, 359 Control => Ctrl_buf, 321 360 Data_In(1) => Port1_in(4), 322 361 Data_In(2) => Port2_in(4), … … 333 372 PORT MAP( 334 373 335 Control => Ctrl, 374 reset => reset, 375 clk=>clk, 376 Control => Ctrl_buf, 336 377 Data_In(1) => Port1_in(5), 337 378 Data_In(2) => Port2_in(5), … … 348 389 PORT MAP( 349 390 350 Control => Ctrl, 391 reset => reset, 392 clk =>clk, 393 394 Control => Ctrl_buf, 351 395 Data_In(1) => Port1_in(6), 352 396 Data_In(2) => Port2_in(6), … … 362 406 GENERIC MAP(number_of_ports => 3) 363 407 PORT MAP( 364 365 Control => Ctrl, 408 reset => reset, 409 clk =>clk, 410 411 Control => Ctrl_buf, 366 412 Data_In(1) => Port1_in(7), 367 413 Data_In(2) => Port2_in(7), … … 377 423 GENERIC MAP(number_of_ports => 3) 378 424 PORT MAP( 379 380 Control => Ctrl, 425 reset => reset, 426 clk =>clk, 427 428 Control => Ctrl_buf, 381 429 Data_In(1) => Port1_pulse_in, 382 430 Data_In(2) => Port2_pulse_in, … … 400 448 PORT MAP( 401 449 402 Control => Ctrl, 450 reset => reset, 451 clk=>clk, 452 Control => Ctrl_buf, 403 453 Data_In(1) => Port1_in(0), 404 454 Data_In(2) => Port2_in(0), … … 417 467 PORT MAP( 418 468 419 Control => Ctrl, 469 reset => reset, 470 clk=>clk, 471 Control => Ctrl_buf, 420 472 Data_In(1) => Port1_in(1), 421 473 Data_In(2) => Port2_in(1), … … 434 486 PORT MAP( 435 487 436 Control => Ctrl, 488 reset => reset, 489 clk=>clk, 490 Control => Ctrl_buf, 437 491 Data_In(1) => Port1_in(2), 438 492 Data_In(2) => Port2_in(2), … … 451 505 PORT MAP( 452 506 453 Control => Ctrl, 507 reset => reset, 508 clk=>clk, 509 Control => Ctrl_buf, 454 510 Data_In(1) => Port1_in(3), 455 511 Data_In(2) => Port2_in(3), … … 468 524 PORT MAP( 469 525 470 Control => Ctrl, 526 reset => reset, 527 clk=>clk, 528 Control => Ctrl_buf, 471 529 Data_In(1) => Port1_in(4), 472 530 Data_In(2) => Port2_in(4), … … 485 543 PORT MAP( 486 544 487 Control => Ctrl, 545 reset => reset, 546 clk=>clk, 547 Control => Ctrl_buf, 488 548 Data_In(1) => Port1_in(5), 489 549 Data_In(2) => Port2_in(5), … … 502 562 PORT MAP( 503 563 504 Control => Ctrl, 564 reset => reset, 565 clk=>clk, 566 Control => Ctrl_buf, 505 567 Data_In(1) => Port1_in(6), 506 568 Data_In(2) => Port2_in(6), … … 519 581 PORT MAP( 520 582 521 Control => Ctrl, 583 reset => reset, 584 clk=>clk, 585 Control => Ctrl_buf, 522 586 Data_In(1) => Port1_in(7), 523 587 Data_In(2) => Port2_in(7), … … 536 600 PORT MAP( 537 601 538 Control => Ctrl, 602 reset => reset, 603 clk=>clk, 604 Control => Ctrl_buf, 539 605 Data_In(1) => Port1_pulse_in, 540 606 Data_In(2) => Port2_pulse_in, … … 560 626 PORT MAP( 561 627 562 Control => Ctrl, 628 reset => reset, 629 clk=>clk, 630 Control => Ctrl_buf, 563 631 Data_In(1) => Port1_in(0), 564 632 Data_In(2) => Port2_in(0), … … 579 647 PORT MAP( 580 648 581 Control => Ctrl, 649 reset => reset, 650 clk=>clk, 651 Control => Ctrl_buf, 582 652 Data_In(1) => Port1_in(1), 583 653 Data_In(2) => Port2_in(1), … … 598 668 PORT MAP( 599 669 600 Control => Ctrl, 670 reset => reset, 671 clk=>clk, 672 Control => Ctrl_buf, 601 673 Data_In(1) => Port1_in(2), 602 674 Data_In(2) => Port2_in(2), … … 617 689 PORT MAP( 618 690 619 Control => Ctrl, 691 reset => reset, 692 clk=>clk, 693 Control => Ctrl_buf, 620 694 Data_In(1) => Port1_in(3), 621 695 Data_In(2) => Port2_in(3), … … 636 710 PORT MAP( 637 711 638 Control => Ctrl, 712 reset => reset, 713 clk=>clk, 714 Control => Ctrl_buf, 639 715 Data_In(1) => Port1_in(4), 640 716 Data_In(2) => Port2_in(4), … … 655 731 PORT MAP( 656 732 657 Control => Ctrl, 733 reset => reset, 734 clk=>clk, 735 Control => Ctrl_buf, 658 736 Data_In(1) => Port1_in(5), 659 737 Data_In(2) => Port2_in(5), … … 674 752 PORT MAP( 675 753 676 Control => Ctrl, 754 reset => reset, 755 clk=>clk, 756 Control => Ctrl_buf, 677 757 Data_In(1) => Port1_in(6), 678 758 Data_In(2) => Port2_in(6), … … 693 773 PORT MAP( 694 774 695 Control => Ctrl, 775 reset => reset, 776 clk=>clk, 777 Control => Ctrl_buf, 696 778 Data_In(1) => Port1_in(7), 697 779 Data_In(2) => Port2_in(7), … … 712 794 PORT MAP( 713 795 714 Control => Ctrl, 796 reset => reset, 797 clk=>clk, 798 Control => Ctrl_buf, 715 799 Data_In(1) => Port1_pulse_in, 716 800 Data_In(2) => Port2_pulse_in, … … 738 822 PORT MAP( 739 823 740 Control => Ctrl, 824 reset => reset, 825 clk=>clk, 826 Control => Ctrl_buf, 741 827 Data_In(1) => Port1_in(0), 742 828 Data_In(2) => Port2_in(0), … … 759 845 PORT MAP( 760 846 761 Control => Ctrl, 847 reset => reset, 848 clk=>clk, 849 Control => Ctrl_buf, 762 850 Data_In(1) => Port1_in(1), 763 851 Data_In(2) => Port2_in(1), … … 780 868 PORT MAP( 781 869 782 Control => Ctrl, 870 reset => reset, 871 clk=>clk, 872 Control => Ctrl_buf, 783 873 Data_In(1) => Port1_in(2), 784 874 Data_In(2) => Port2_in(2), … … 801 891 PORT MAP( 802 892 803 Control => Ctrl, 893 reset => reset, 894 clk=>clk, 895 Control => Ctrl_buf, 804 896 Data_In(1) => Port1_in(3), 805 897 Data_In(2) => Port2_in(3), … … 822 914 PORT MAP( 823 915 824 Control => Ctrl, 916 reset => reset, 917 clk=>clk, 918 Control => Ctrl_buf, 825 919 Data_In(1) => Port1_in(4), 826 920 Data_In(2) => Port2_in(4), … … 843 937 PORT MAP( 844 938 845 Control => Ctrl, 939 reset => reset, 940 clk=>clk, 941 Control => Ctrl_buf, 846 942 Data_In(1) => Port1_in(5), 847 943 Data_In(2) => Port2_in(5), … … 864 960 PORT MAP( 865 961 866 Control => Ctrl, 962 reset => reset, 963 clk=>clk, 964 Control => Ctrl_buf, 867 965 Data_In(1) => Port1_in(6), 868 966 Data_In(2) => Port2_in(6), … … 885 983 PORT MAP( 886 984 887 Control => Ctrl, 985 reset => reset, 986 clk=>clk, 987 Control => Ctrl_buf, 888 988 Data_In(1) => Port1_in(7), 889 989 Data_In(2) => Port2_in(7), … … 906 1006 PORT MAP( 907 1007 908 Control => Ctrl, 1008 reset => reset, 1009 clk=>clk, 1010 Control => Ctrl_buf, 909 1011 Data_In(1) => Port1_pulse_in, 910 1012 Data_In(2) => Port2_pulse_in, … … 934 1036 PORT MAP( 935 1037 936 Control => Ctrl, 1038 reset => reset, 1039 clk=>clk, 1040 Control => Ctrl_buf, 937 1041 Data_In(1) => Port1_in(0), 938 1042 Data_In(2) => Port2_in(0), … … 957 1061 PORT MAP( 958 1062 959 Control => Ctrl, 1063 reset => reset, 1064 clk=>clk, 1065 Control => Ctrl_buf, 960 1066 Data_In(1) => Port1_in(1), 961 1067 Data_In(2) => Port2_in(1), … … 980 1086 PORT MAP( 981 1087 982 Control => Ctrl, 1088 reset => reset, 1089 clk=>clk, 1090 Control => Ctrl_buf, 983 1091 Data_In(1) => Port1_in(2), 984 1092 Data_In(2) => Port2_in(2), … … 1003 1111 PORT MAP( 1004 1112 1005 Control => Ctrl, 1113 reset => reset, 1114 clk=>clk, 1115 Control => Ctrl_buf, 1006 1116 Data_In(1) => Port1_in(3), 1007 1117 Data_In(2) => Port2_in(3), … … 1026 1136 PORT MAP( 1027 1137 1028 Control => Ctrl, 1138 reset => reset, 1139 clk=>clk, 1140 Control => Ctrl_buf, 1029 1141 Data_In(1) => Port1_in(4), 1030 1142 Data_In(2) => Port2_in(4), … … 1049 1161 PORT MAP( 1050 1162 1051 Control => Ctrl, 1163 reset => reset, 1164 clk=>clk, 1165 Control => Ctrl_buf, 1052 1166 Data_In(1) => Port1_in(5), 1053 1167 Data_In(2) => Port2_in(5), … … 1072 1186 PORT MAP( 1073 1187 1074 Control => Ctrl, 1188 reset => reset, 1189 clk=>clk, 1190 Control => Ctrl_buf, 1075 1191 Data_In(1) => Port1_in(6), 1076 1192 Data_In(2) => Port2_in(6), … … 1095 1211 PORT MAP( 1096 1212 1097 Control => Ctrl, 1213 reset => reset, 1214 clk=>clk, 1215 Control => Ctrl_buf, 1098 1216 Data_In(1) => Port1_in(7), 1099 1217 Data_In(2) => Port2_in(7), … … 1118 1236 PORT MAP( 1119 1237 1120 Control => Ctrl, 1238 reset => reset, 1239 clk=>clk, 1240 Control => Ctrl_buf, 1121 1241 Data_In(1) => Port1_pulse_in, 1122 1242 Data_In(2) => Port2_pulse_in, … … 1147 1267 GENERIC MAP(number_of_ports => 8) 1148 1268 PORT MAP( 1149 1150 Control => Ctrl, 1269 clk =>clk, 1270 reset =>reset, 1271 1272 Control => Ctrl_buf, 1151 1273 Data_In(1) => Port1_in(0), 1152 1274 Data_In(2) => Port2_in(0), … … 1172 1294 GENERIC MAP(number_of_ports => 8) 1173 1295 PORT MAP( 1174 1175 Control => Ctrl, 1296 clk =>clk, 1297 reset =>reset, 1298 1299 Control => Ctrl_buf, 1176 1300 Data_In(1) => Port1_in(1), 1177 1301 Data_In(2) => Port2_in(1), … … 1197 1321 GENERIC MAP(number_of_ports => 8) 1198 1322 PORT MAP( 1199 1200 Control => Ctrl, 1323 clk =>clk, 1324 reset =>reset, 1325 1326 Control => Ctrl_buf, 1201 1327 Data_In(1) => Port1_in(2), 1202 1328 Data_In(2) => Port2_in(2), … … 1222 1348 GENERIC MAP(number_of_ports => 8) 1223 1349 PORT MAP( 1224 1225 Control => Ctrl, 1350 clk =>clk, 1351 reset =>reset, 1352 1353 Control => Ctrl_buf, 1226 1354 Data_In(1) => Port1_in(3), 1227 1355 Data_In(2) => Port2_in(3), … … 1247 1375 GENERIC MAP(number_of_ports => 8) 1248 1376 PORT MAP( 1249 1250 Control => Ctrl, 1377 clk =>clk, 1378 reset =>reset, 1379 1380 Control => Ctrl_buf, 1251 1381 Data_In(1) => Port1_in(4), 1252 1382 Data_In(2) => Port2_in(4), … … 1272 1402 GENERIC MAP(number_of_ports => 8) 1273 1403 PORT MAP( 1274 1275 Control => Ctrl, 1404 clk =>clk, 1405 reset =>reset, 1406 1407 Control => Ctrl_buf, 1276 1408 Data_In(1) => Port1_in(5), 1277 1409 Data_In(2) => Port2_in(5), … … 1297 1429 GENERIC MAP(number_of_ports => 8) 1298 1430 PORT MAP( 1299 1300 Control => Ctrl, 1431 clk =>clk, 1432 reset =>reset, 1433 1434 Control => Ctrl_buf, 1301 1435 Data_In(1) => Port1_in(6), 1302 1436 Data_In(2) => Port2_in(6), … … 1322 1456 GENERIC MAP(number_of_ports => 8) 1323 1457 PORT MAP( 1324 1325 Control => Ctrl, 1458 clk =>clk, 1459 reset =>reset, 1460 1461 Control => Ctrl_buf, 1326 1462 Data_In(1) => Port1_in(7), 1327 1463 Data_In(2) => Port2_in(7), … … 1347 1483 GENERIC MAP(number_of_ports => 8) 1348 1484 PORT MAP( 1349 1350 Control => Ctrl, 1485 clk =>clk, 1486 reset =>reset, 1487 1488 Control => Ctrl_buf, 1351 1489 Data_In(1) => Port1_pulse_in, 1352 1490 Data_In(2) => Port2_pulse_in, … … 1379 1517 GENERIC MAP(number_of_ports => 9) 1380 1518 PORT MAP( 1381 1382 Control => Ctrl, 1519 clk =>clk, 1520 reset =>reset, 1521 1522 Control => Ctrl_buf, 1383 1523 Data_In(1) => Port1_in(0), 1384 1524 Data_In(2) => Port2_in(0), … … 1406 1546 GENERIC MAP(number_of_ports => 9) 1407 1547 PORT MAP( 1408 1409 Control => Ctrl, 1548 clk =>clk, 1549 reset =>reset, 1550 1551 Control => Ctrl_buf, 1410 1552 Data_In(1) => Port1_in(1), 1411 1553 Data_In(2) => Port2_in(1), … … 1433 1575 GENERIC MAP(number_of_ports => 9) 1434 1576 PORT MAP( 1435 1436 Control => Ctrl, 1577 clk =>clk, 1578 reset =>reset, 1579 1580 Control => Ctrl_buf, 1437 1581 Data_In(1) => Port1_in(2), 1438 1582 Data_In(2) => Port2_in(2), … … 1460 1604 GENERIC MAP(number_of_ports => 9) 1461 1605 PORT MAP( 1462 1463 Control => Ctrl, 1606 clk =>clk, 1607 reset =>reset, 1608 1609 Control => Ctrl_buf, 1464 1610 Data_In(1) => Port1_in(3), 1465 1611 Data_In(2) => Port2_in(3), … … 1487 1633 GENERIC MAP(number_of_ports => 9) 1488 1634 PORT MAP( 1489 1490 Control => Ctrl, 1635 clk =>clk, 1636 reset =>reset, 1637 1638 Control => Ctrl_buf, 1491 1639 Data_In(1) => Port1_in(4), 1492 1640 Data_In(2) => Port2_in(4), … … 1514 1662 GENERIC MAP(number_of_ports => 9) 1515 1663 PORT MAP( 1516 1517 Control => Ctrl, 1664 clk =>clk, 1665 reset =>reset, 1666 1667 Control => Ctrl_buf, 1518 1668 Data_In(1) => Port1_in(5), 1519 1669 Data_In(2) => Port2_in(5), … … 1541 1691 GENERIC MAP(number_of_ports => 9) 1542 1692 PORT MAP( 1543 1544 Control => Ctrl, 1693 clk =>clk, 1694 reset =>reset, 1695 1696 Control => Ctrl_buf, 1545 1697 Data_In(1) => Port1_in(6), 1546 1698 Data_In(2) => Port2_in(6), … … 1568 1720 GENERIC MAP(number_of_ports => 9) 1569 1721 PORT MAP( 1570 1571 Control => Ctrl, 1722 clk =>clk, 1723 reset =>reset, 1724 1725 Control => Ctrl_buf, 1572 1726 Data_In(1) => Port1_in(7), 1573 1727 Data_In(2) => Port2_in(7), … … 1595 1749 GENERIC MAP(number_of_ports => 9) 1596 1750 PORT MAP( 1597 1598 Control => Ctrl, 1751 clk =>clk, 1752 reset =>reset, 1753 1754 Control => Ctrl_buf, 1599 1755 Data_In(1) => Port1_pulse_in, 1600 1756 Data_In(2) => Port2_pulse_in, … … 1630 1786 PORT MAP( 1631 1787 1632 Control => Ctrl, 1788 reset => reset, 1789 clk=>clk, 1790 Control => Ctrl_buf, 1633 1791 Data_In(1) => Port1_in(0), 1634 1792 Data_In(2) => Port2_in(0), … … 1659 1817 PORT MAP( 1660 1818 1661 Control => Ctrl, 1819 reset => reset, 1820 clk=>clk, 1821 Control => Ctrl_buf, 1662 1822 Data_In(1) => Port1_in(1), 1663 1823 Data_In(2) => Port2_in(1), … … 1688 1848 PORT MAP( 1689 1849 1690 Control => Ctrl, 1850 reset => reset, 1851 clk=>clk, 1852 Control => Ctrl_buf, 1691 1853 Data_In(1) => Port1_in(2), 1692 1854 Data_In(2) => Port2_in(2), … … 1717 1879 PORT MAP( 1718 1880 1719 Control => Ctrl, 1881 reset => reset, 1882 clk=>clk, 1883 Control => Ctrl_buf, 1720 1884 Data_In(1) => Port1_in(3), 1721 1885 Data_In(2) => Port2_in(3), … … 1746 1910 PORT MAP( 1747 1911 1748 Control => Ctrl, 1912 reset => reset, 1913 clk=>clk, 1914 Control => Ctrl_buf, 1749 1915 Data_In(1) => Port1_in(4), 1750 1916 Data_In(2) => Port2_in(4), … … 1775 1941 PORT MAP( 1776 1942 1777 Control => Ctrl, 1943 reset => reset, 1944 clk=>clk, 1945 Control => Ctrl_buf, 1778 1946 Data_In(1) => Port1_in(5), 1779 1947 Data_In(2) => Port2_in(5), … … 1804 1972 PORT MAP( 1805 1973 1806 Control => Ctrl, 1974 reset => reset, 1975 clk=>clk, 1976 Control => Ctrl_buf, 1807 1977 Data_In(1) => Port1_in(6), 1808 1978 Data_In(2) => Port2_in(6), … … 1833 2003 PORT MAP( 1834 2004 1835 Control => Ctrl, 2005 reset => reset, 2006 clk=>clk, 2007 Control => Ctrl_buf, 1836 2008 Data_In(1) => Port1_in(7), 1837 2009 Data_In(2) => Port2_in(7), … … 1862 2034 PORT MAP( 1863 2035 1864 Control => Ctrl, 2036 reset => reset, 2037 clk=>clk, 2038 Control => Ctrl_buf, 1865 2039 Data_In(1) => Port1_pulse_in, 1866 2040 Data_In(2) => Port2_pulse_in, … … 1898 2072 PORT MAP( 1899 2073 1900 Control => Ctrl, 2074 reset => reset, 2075 clk=>clk, 2076 Control => Ctrl_buf, 1901 2077 Data_In(1) => Port1_in(0), 1902 2078 Data_In(2) => Port2_in(0), … … 1929 2105 PORT MAP( 1930 2106 1931 Control => Ctrl, 2107 reset => reset, 2108 clk=>clk, 2109 Control => Ctrl_buf, 1932 2110 Data_In(1) => Port1_in(1), 1933 2111 Data_In(2) => Port2_in(1), … … 1960 2138 PORT MAP( 1961 2139 1962 Control => Ctrl, 2140 reset => reset, 2141 clk=>clk, 2142 Control => Ctrl_buf, 1963 2143 Data_In(1) => Port1_in(2), 1964 2144 Data_In(2) => Port2_in(2), … … 1991 2171 PORT MAP( 1992 2172 1993 Control => Ctrl, 2173 reset => reset, 2174 clk=>clk, 2175 2176 Control => Ctrl_buf, 1994 2177 Data_In(1) => Port1_in(3), 1995 2178 Data_In(2) => Port2_in(3), … … 2022 2205 PORT MAP( 2023 2206 2024 Control => Ctrl, 2207 reset => reset, 2208 clk=>clk, 2209 Control => Ctrl_buf, 2025 2210 Data_In(1) => Port1_in(4), 2026 2211 Data_In(2) => Port2_in(4), … … 2053 2238 PORT MAP( 2054 2239 2055 Control => Ctrl, 2240 reset => reset, 2241 clk=>clk, 2242 2243 Control => Ctrl_buf, 2056 2244 Data_In(1) => Port1_in(5), 2057 2245 Data_In(2) => Port2_in(5), … … 2084 2272 PORT MAP( 2085 2273 2086 Control => Ctrl, 2274 reset => reset, 2275 clk=>clk, 2276 2277 Control => Ctrl_buf, 2087 2278 Data_In(1) => Port1_in(6), 2088 2279 Data_In(2) => Port2_in(6), … … 2115 2306 PORT MAP( 2116 2307 2117 Control => Ctrl, 2308 reset => reset, 2309 clk=>clk, 2310 2311 Control => Ctrl_buf, 2118 2312 Data_In(1) => Port1_in(7), 2119 2313 Data_In(2) => Port2_in(7), … … 2146 2340 PORT MAP( 2147 2341 2148 Control => Ctrl, 2342 reset => reset, 2343 clk=>clk, 2344 2345 Control => Ctrl_buf, 2149 2346 Data_In(1) => Port1_pulse_in, 2150 2347 Data_In(2) => Port2_pulse_in, … … 2184 2381 PORT MAP( 2185 2382 2186 Control => Ctrl, 2383 reset => reset, 2384 clk=>clk, 2385 2386 Control => Ctrl_buf, 2187 2387 Data_In(1) => Port1_in(0), 2188 2388 Data_In(2) => Port2_in(0), … … 2217 2417 PORT MAP( 2218 2418 2219 Control => Ctrl, 2419 reset => reset, 2420 clk=>clk, 2421 2422 Control => Ctrl_buf, 2220 2423 Data_In(1) => Port1_in(1), 2221 2424 Data_In(2) => Port2_in(1), … … 2250 2453 PORT MAP( 2251 2454 2252 Control => Ctrl, 2455 reset => reset, 2456 clk=>clk, 2457 2458 Control => Ctrl_buf, 2253 2459 Data_In(1) => Port1_in(2), 2254 2460 Data_In(2) => Port2_in(2), … … 2283 2489 PORT MAP( 2284 2490 2285 Control => Ctrl, 2491 reset => reset, 2492 clk=>clk, 2493 2494 Control => Ctrl_buf, 2286 2495 Data_In(1) => Port1_in(3), 2287 2496 Data_In(2) => Port2_in(3), … … 2316 2525 PORT MAP( 2317 2526 2318 Control => Ctrl, 2527 reset => reset, 2528 clk=>clk, 2529 2530 Control => Ctrl_buf, 2319 2531 Data_In(1) => Port1_in(4), 2320 2532 Data_In(2) => Port2_in(4), … … 2349 2561 PORT MAP( 2350 2562 2351 Control => Ctrl, 2563 reset => reset, 2564 clk=>clk, 2565 2566 Control => Ctrl_buf, 2352 2567 Data_In(1) => Port1_in(5), 2353 2568 Data_In(2) => Port2_in(5), … … 2382 2597 PORT MAP( 2383 2598 2384 Control => Ctrl, 2599 reset => reset, 2600 clk=>clk, 2601 2602 Control => Ctrl_buf, 2385 2603 Data_In(1) => Port1_in(6), 2386 2604 Data_In(2) => Port2_in(6), … … 2415 2633 PORT MAP( 2416 2634 2417 Control => Ctrl, 2635 reset => reset, 2636 clk=>clk, 2637 2638 Control => Ctrl_buf, 2418 2639 Data_In(1) => Port1_in(7), 2419 2640 Data_In(2) => Port2_in(7), … … 2448 2669 PORT MAP( 2449 2670 2450 Control => Ctrl, 2671 reset => reset, 2672 clk=>clk, 2673 2674 Control => Ctrl_buf, 2451 2675 Data_In(1) => Port1_pulse_in, 2452 2676 Data_In(2) => Port2_pulse_in, … … 2488 2712 PORT MAP( 2489 2713 2490 Control => Ctrl, 2714 reset => reset, 2715 clk=>clk, 2716 Control => Ctrl_buf, 2491 2717 Data_In(1) => Port1_in(0), 2492 2718 Data_In(2) => Port2_in(0), … … 2523 2749 PORT MAP( 2524 2750 2525 Control => Ctrl, 2751 reset => reset, 2752 clk=>clk, 2753 2754 Control => Ctrl_buf, 2526 2755 Data_In(1) => Port1_in(1), 2527 2756 Data_In(2) => Port2_in(1), … … 2558 2787 PORT MAP( 2559 2788 2560 Control => Ctrl, 2789 reset => reset, 2790 clk=>clk, 2791 2792 Control => Ctrl_buf, 2561 2793 Data_In(1) => Port1_in(2), 2562 2794 Data_In(2) => Port2_in(2), … … 2593 2825 PORT MAP( 2594 2826 2595 Control => Ctrl, 2827 reset => reset, 2828 clk=>clk, 2829 Control => Ctrl_buf, 2596 2830 Data_In(1) => Port1_in(3), 2597 2831 Data_In(2) => Port2_in(3), … … 2628 2862 PORT MAP( 2629 2863 2630 Control => Ctrl, 2864 reset => reset, 2865 clk=>clk, 2866 Control => Ctrl_buf, 2631 2867 Data_In(1) => Port1_in(4), 2632 2868 Data_In(2) => Port2_in(4), … … 2663 2899 PORT MAP( 2664 2900 2665 Control => Ctrl, 2901 reset => reset, 2902 clk=>clk, 2903 Control => Ctrl_buf, 2666 2904 Data_In(1) => Port1_in(5), 2667 2905 Data_In(2) => Port2_in(5), … … 2698 2936 PORT MAP( 2699 2937 2700 Control => Ctrl, 2938 reset => reset, 2939 clk=>clk, 2940 Control => Ctrl_buf, 2701 2941 Data_In(1) => Port1_in(6), 2702 2942 Data_In(2) => Port2_in(6), … … 2733 2973 PORT MAP( 2734 2974 2735 Control => Ctrl, 2975 reset => reset, 2976 clk=>clk, 2977 Control => Ctrl_buf, 2736 2978 Data_In(1) => Port1_in(7), 2737 2979 Data_In(2) => Port2_in(7), … … 2768 3010 PORT MAP( 2769 3011 2770 Control => Ctrl, 3012 reset => reset, 3013 clk=>clk, 3014 Control => Ctrl_buf, 2771 3015 Data_In(1) => Port1_pulse_in, 2772 3016 Data_In(2) => Port2_pulse_in, … … 2810 3054 PORT MAP( 2811 3055 2812 Control => Ctrl, 3056 reset => reset, 3057 clk=>clk, 3058 Control => Ctrl_buf, 2813 3059 Data_In(1) => Port1_in(0), 2814 3060 Data_In(2) => Port2_in(0), … … 2847 3093 PORT MAP( 2848 3094 2849 Control => Ctrl, 3095 reset => reset, 3096 clk=>clk, 3097 Control => Ctrl_buf, 2850 3098 Data_In(1) => Port1_in(1), 2851 3099 Data_In(2) => Port2_in(1), … … 2884 3132 PORT MAP( 2885 3133 2886 Control => Ctrl, 3134 reset => reset, 3135 clk=>clk, 3136 Control => Ctrl_buf, 2887 3137 Data_In(1) => Port1_in(2), 2888 3138 Data_In(2) => Port2_in(2), … … 2921 3171 PORT MAP( 2922 3172 2923 Control => Ctrl, 3173 reset => reset, 3174 clk=>clk, 3175 Control => Ctrl_buf, 2924 3176 Data_In(1) => Port1_in(3), 2925 3177 Data_In(2) => Port2_in(3), … … 2958 3210 PORT MAP( 2959 3211 2960 Control => Ctrl, 3212 reset => reset, 3213 clk=>clk, 3214 Control => Ctrl_buf, 2961 3215 Data_In(1) => Port1_in(4), 2962 3216 Data_In(2) => Port2_in(4), … … 2995 3249 PORT MAP( 2996 3250 2997 Control => Ctrl, 3251 reset => reset, 3252 clk=>clk, 3253 Control => Ctrl_buf, 2998 3254 Data_In(1) => Port1_in(5), 2999 3255 Data_In(2) => Port2_in(5), … … 3032 3288 PORT MAP( 3033 3289 3034 Control => Ctrl, 3290 reset => reset, 3291 clk=>clk, 3292 Control => Ctrl_buf, 3035 3293 Data_In(1) => Port1_in(6), 3036 3294 Data_In(2) => Port2_in(6), … … 3069 3327 PORT MAP( 3070 3328 3071 Control => Ctrl, 3329 reset => reset, 3330 clk=>clk, 3331 Control => Ctrl_buf, 3072 3332 Data_In(1) => Port1_in(7), 3073 3333 Data_In(2) => Port2_in(7), … … 3106 3366 PORT MAP( 3107 3367 3108 Control => Ctrl, 3368 reset => reset, 3369 clk=>clk, 3370 Control => Ctrl_buf, 3109 3371 Data_In(1) => Port1_pulse_in, 3110 3372 Data_In(2) => Port2_pulse_in, … … 3150 3412 PORT MAP( 3151 3413 3152 Control => Ctrl, 3414 reset => reset, 3415 clk=>clk, 3416 Control => Ctrl_buf, 3153 3417 Data_In(1) => Port1_in(0), 3154 3418 Data_In(2) => Port2_in(0), … … 3189 3453 PORT MAP( 3190 3454 3191 Control => Ctrl, 3455 reset => reset, 3456 clk=>clk, 3457 Control => Ctrl_buf, 3192 3458 Data_In(1) => Port1_in(1), 3193 3459 Data_In(2) => Port2_in(1), … … 3228 3494 PORT MAP( 3229 3495 3230 Control => Ctrl, 3496 reset => reset, 3497 clk=>clk, 3498 Control => Ctrl_buf, 3231 3499 Data_In(1) => Port1_in(2), 3232 3500 Data_In(2) => Port2_in(2), … … 3267 3535 PORT MAP( 3268 3536 3269 Control => Ctrl, 3537 reset => reset, 3538 clk=>clk, 3539 Control => Ctrl_buf, 3270 3540 Data_In(1) => Port1_in(3), 3271 3541 Data_In(2) => Port2_in(3), … … 3306 3576 PORT MAP( 3307 3577 3308 Control => Ctrl, 3578 reset => reset, 3579 clk=>clk, 3580 Control => Ctrl_buf, 3309 3581 Data_In(1) => Port1_in(4), 3310 3582 Data_In(2) => Port2_in(4), … … 3345 3617 PORT MAP( 3346 3618 3347 Control => Ctrl, 3619 reset => reset, 3620 clk=>clk, 3621 Control => Ctrl_buf, 3348 3622 Data_In(1) => Port1_in(5), 3349 3623 Data_In(2) => Port2_in(5), … … 3384 3658 PORT MAP( 3385 3659 3386 Control => Ctrl, 3660 reset => reset, 3661 clk=>clk, 3662 Control => Ctrl_buf, 3387 3663 Data_In(1) => Port1_in(6), 3388 3664 Data_In(2) => Port2_in(6), … … 3423 3699 PORT MAP( 3424 3700 3425 Control => Ctrl, 3701 reset => reset, 3702 clk=>clk, 3703 Control => Ctrl_buf, 3426 3704 Data_In(1) => Port1_in(7), 3427 3705 Data_In(2) => Port2_in(7), … … 3462 3740 PORT MAP( 3463 3741 3464 Control => Ctrl, 3742 reset => reset, 3743 clk=>clk, 3744 Control => Ctrl_buf, 3465 3745 Data_In(1) => Port1_pulse_in, 3466 3746 Data_In(2) => Port2_pulse_in, … … 3508 3788 PORT MAP( 3509 3789 3510 Control => Ctrl, 3790 reset => reset, 3791 clk=>clk, 3792 Control => Ctrl_buf, 3511 3793 Data_In(1) => Port1_in(0), 3512 3794 Data_In(2) => Port2_in(0), … … 3549 3831 PORT MAP( 3550 3832 3551 Control => Ctrl, 3833 reset => reset, 3834 clk=>clk, 3835 Control => Ctrl_buf, 3552 3836 Data_In(1) => Port1_in(1), 3553 3837 Data_In(2) => Port2_in(1), … … 3590 3874 PORT MAP( 3591 3875 3592 Control => Ctrl, 3876 reset => reset, 3877 clk=>clk, 3878 Control => Ctrl_buf, 3593 3879 Data_In(1) => Port1_in(2), 3594 3880 Data_In(2) => Port2_in(2), … … 3631 3917 PORT MAP( 3632 3918 3633 Control => Ctrl, 3919 reset => reset, 3920 clk=>clk, 3921 Control => Ctrl_buf, 3634 3922 Data_In(1) => Port1_in(3), 3635 3923 Data_In(2) => Port2_in(3), … … 3672 3960 PORT MAP( 3673 3961 3674 Control => Ctrl, 3962 reset => reset, 3963 clk=>clk, 3964 Control => Ctrl_buf, 3675 3965 Data_In(1) => Port1_in(4), 3676 3966 Data_In(2) => Port2_in(4), … … 3713 4003 PORT MAP( 3714 4004 3715 Control => Ctrl, 4005 reset => reset, 4006 clk=>clk, 4007 Control => Ctrl_buf, 3716 4008 Data_In(1) => Port1_in(5), 3717 4009 Data_In(2) => Port2_in(5), … … 3754 4046 PORT MAP( 3755 4047 3756 Control => Ctrl, 4048 reset => reset, 4049 clk=>clk, 4050 Control => Ctrl_buf, 3757 4051 Data_In(1) => Port1_in(6), 3758 4052 Data_In(2) => Port2_in(6), … … 3795 4089 PORT MAP( 3796 4090 3797 Control => Ctrl, 4091 reset => reset, 4092 clk=>clk, 4093 Control => Ctrl_buf, 3798 4094 Data_In(1) => Port1_in(7), 3799 4095 Data_In(2) => Port2_in(7), … … 3836 4132 PORT MAP( 3837 4133 3838 Control => Ctrl, 4134 reset => reset, 4135 clk=>clk, 4136 Control => Ctrl_buf, 3839 4137 Data_In(1) => Port1_pulse_in, 3840 4138 Data_In(2) => Port2_pulse_in,
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