1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: |
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4 | -- |
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5 | -- Create Date: 18:01:21 10/23/2012 |
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6 | -- Design Name: |
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7 | -- Module Name: proto_send - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | library IEEE; |
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21 | use IEEE.STD_LOGIC_1164.ALL; |
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22 | USE ieee.numeric_std.ALL; |
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23 | use CoreTypes.all; |
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24 | -- Uncomment the following library declaration if using |
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25 | -- arithmetic functions with Signed or Unsigned values |
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26 | --use IEEE.NUMERIC_STD.ALL; |
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27 | |
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28 | -- Uncomment the following library declaration if instantiating |
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29 | -- any Xilinx primitives in this code. |
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30 | --library UNISIM; |
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31 | --use UNISIM.VComponents.all; |
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32 | |
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33 | entity proto_send is |
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34 | generic (sizemem : natural := 64); |
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35 | port ( |
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36 | clk,reset : in std_logic; |
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37 | fifo_empty,fifo_full : in std_logic; |
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38 | push : out std_logic:='0'; |
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39 | fifo_in : out std_logic_vector(Word-1 downto 0); |
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40 | snd_start : in std_logic; --début de la réception |
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41 | snd_ack :in std_logic; -- acquittement de la réception |
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42 | snd_comp : out std_logic; -- fin de la réception |
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43 | mem :in memory(0 to sizemem-1)); |
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44 | |
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45 | end proto_send; |
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46 | |
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47 | architecture Behavioral of proto_send is |
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48 | type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); |
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49 | signal etsnd : typ_send; |
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50 | signal sfifo_in : std_logic_vector(Word-1 downto 0); |
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51 | signal spush : std_logic:='0'; |
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52 | signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); |
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53 | begin |
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54 | |
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55 | proc_send : process (clk,reset) |
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56 | variable dlen,i: natural range 0 to 255 :=0; |
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57 | begin |
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58 | if reset='1' then |
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59 | etsnd<=s_head; |
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60 | err<=(others =>'0'); |
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61 | else |
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62 | if rising_edge(clk) then -- le process s'exécute sur chaque front |
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63 | -- montant de l'horloge |
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64 | case etsnd is |
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65 | when s_head => |
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66 | sfifo_in<=mem(0); |
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67 | snd_comp<='0'; |
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68 | i:=0; |
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69 | |
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70 | if fifo_empty='1' and snd_start='1' then |
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71 | spush<='1'; |
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72 | snd_comp<='0'; |
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73 | etsnd<=s_len; |
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74 | end if; |
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75 | when s_pulse => |
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76 | spush<='1'; |
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77 | etsnd<=s_len; |
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78 | when s_len => |
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79 | sfifo_in<=mem(1); --8 données |
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80 | i:=i+1; |
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81 | dlen:=to_integer(unsigned(mem(i))); |
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82 | if dlen > 2 then |
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83 | spush<='1'; |
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84 | snd_comp<='0'; |
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85 | etsnd<=s_data; |
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86 | else |
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87 | spush<='1'; |
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88 | snd_comp<='1'; |
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89 | etsnd<=s_end; |
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90 | |
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91 | end if; |
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92 | when s_len2 => |
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93 | snd_comp<='0'; |
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94 | etsnd<=s_data; |
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95 | |
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96 | when s_data => |
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97 | if (fifo_full='0') and (dlen >2) then |
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98 | i:=i+1; |
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99 | sfifo_in<=mem(i); |
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100 | if i>=dlen-1 then --les indices 0 et 1 étant réservés |
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101 | --les données sont comptés à partir de 2 |
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102 | etsnd<=s_end; |
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103 | snd_comp<='1'; |
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104 | spush<='1'; |
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105 | else |
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106 | spush<='1'; |
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107 | end if; |
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108 | |
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109 | else |
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110 | spush<='0'; |
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111 | end if; |
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112 | |
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113 | when s_end => |
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114 | spush<='0'; |
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115 | etsnd<=s_head; |
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116 | sfifo_in<=(others=>'-'); |
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117 | if snd_ack='1' then |
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118 | etsnd<=s_head; |
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119 | end if; |
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120 | when others => |
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121 | spush<='0'; |
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122 | etsnd<=s_head; |
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123 | sfifo_in<=(others=>'0'); |
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124 | end case; |
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125 | end if; |
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126 | end if; |
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127 | end process; |
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128 | |
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129 | -- affectation concurentes |
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130 | |
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131 | push<=spush; |
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132 | fifo_in<=sfifo_in; |
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133 | end Behavioral; |
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134 | |
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