source: PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec_hw.tcl @ 84

Last change on this file since 84 was 84, checked in by lambert, 10 years ago

Adding hierarchical subdirectory for every component
File size: 6.4 KB
Line 
1# TCL File Generated by Component Editor 13.1
2# Fri Feb 28 17:02:33 CET 2014
3# DO NOT MODIFY
4
5
6#
7# exg_codec "exg_codec" v1.0
8#  2014.02.28.17:02:33
9#
10#
11
12#
13# request TCL package from ACDS 13.1
14#
15package require -exact qsys 13.1
16
17
18#
19# module exg_codec
20#
21set_module_property DESCRIPTION ""
22set_module_property NAME exg_codec
23set_module_property VERSION 1.0
24set_module_property INTERNAL false
25set_module_property OPAQUE_ADDRESS_MAP true
26set_module_property GROUP smartEEG
27set_module_property AUTHOR ""
28set_module_property DISPLAY_NAME exg_codec
29set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30set_module_property EDITABLE true
31set_module_property ANALYZE_HDL AUTO
32set_module_property REPORT_TO_TALKBACK false
33set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36#
37# file sets
38#
39add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40set_fileset_property QUARTUS_SYNTH TOP_LEVEL exg_codec
41set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42add_fileset_file exg_codec.v VERILOG PATH exg_codec.v TOP_LEVEL_FILE
43
44
45#
46# parameters
47#
48add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1
49set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1
50set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE
51set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING
52set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None
53set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true
54
55
56#
57# display items
58#
59
60
61#
62# connection point clock
63#
64add_interface clock clock end
65set_interface_property clock clockRate 0
66set_interface_property clock ENABLED true
67set_interface_property clock EXPORT_OF ""
68set_interface_property clock PORT_NAME_MAP ""
69set_interface_property clock CMSIS_SVD_VARIABLES ""
70set_interface_property clock SVD_ADDRESS_GROUP ""
71
72add_interface_port clock clk clk Input 1
73
74
75#
76# connection point reset
77#
78add_interface reset reset end
79set_interface_property reset associatedClock clock
80set_interface_property reset synchronousEdges DEASSERT
81set_interface_property reset ENABLED true
82set_interface_property reset EXPORT_OF ""
83set_interface_property reset PORT_NAME_MAP ""
84set_interface_property reset CMSIS_SVD_VARIABLES ""
85set_interface_property reset SVD_ADDRESS_GROUP ""
86
87add_interface_port reset reset reset Input 1
88
89
90#
91# connection point ctrl
92#
93add_interface ctrl avalon end
94set_interface_property ctrl addressUnits WORDS
95set_interface_property ctrl associatedClock clock
96set_interface_property ctrl associatedReset reset
97set_interface_property ctrl bitsPerSymbol 8
98set_interface_property ctrl burstOnBurstBoundariesOnly false
99set_interface_property ctrl burstcountUnits WORDS
100set_interface_property ctrl explicitAddressSpan 0
101set_interface_property ctrl holdTime 0
102set_interface_property ctrl linewrapBursts false
103set_interface_property ctrl maximumPendingReadTransactions 0
104set_interface_property ctrl readLatency 0
105set_interface_property ctrl readWaitTime 1
106set_interface_property ctrl setupTime 0
107set_interface_property ctrl timingUnits Cycles
108set_interface_property ctrl writeWaitTime 0
109set_interface_property ctrl ENABLED true
110set_interface_property ctrl EXPORT_OF ""
111set_interface_property ctrl PORT_NAME_MAP ""
112set_interface_property ctrl CMSIS_SVD_VARIABLES ""
113set_interface_property ctrl SVD_ADDRESS_GROUP ""
114
115add_interface_port ctrl avs_ctrl_address address Input 8
116add_interface_port ctrl avs_ctrl_read read Input 1
117add_interface_port ctrl avs_ctrl_readdata readdata Output 32
118add_interface_port ctrl avs_ctrl_write write Input 1
119add_interface_port ctrl avs_ctrl_writedata writedata Input 32
120add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
121set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
122set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
123set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
124set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
125
126
127#
128# connection point raw_exg
129#
130add_interface raw_exg avalon_streaming end
131set_interface_property raw_exg associatedClock clock
132set_interface_property raw_exg associatedReset reset
133set_interface_property raw_exg dataBitsPerSymbol 8
134set_interface_property raw_exg errorDescriptor ""
135set_interface_property raw_exg firstSymbolInHighOrderBits true
136set_interface_property raw_exg maxChannel 0
137set_interface_property raw_exg readyLatency 0
138set_interface_property raw_exg ENABLED true
139set_interface_property raw_exg EXPORT_OF ""
140set_interface_property raw_exg PORT_NAME_MAP ""
141set_interface_property raw_exg CMSIS_SVD_VARIABLES ""
142set_interface_property raw_exg SVD_ADDRESS_GROUP ""
143
144add_interface_port raw_exg asi_raw_exg_data data Input 32
145add_interface_port raw_exg asi_raw_exg_ready ready Output 1
146add_interface_port raw_exg asi_raw_exg_valid valid Input 1
147
148
149#
150# connection point comp_exg
151#
152add_interface comp_exg avalon_streaming start
153set_interface_property comp_exg associatedClock clock
154set_interface_property comp_exg associatedReset reset
155set_interface_property comp_exg dataBitsPerSymbol 8
156set_interface_property comp_exg errorDescriptor ""
157set_interface_property comp_exg firstSymbolInHighOrderBits true
158set_interface_property comp_exg maxChannel 0
159set_interface_property comp_exg readyLatency 0
160set_interface_property comp_exg ENABLED true
161set_interface_property comp_exg EXPORT_OF ""
162set_interface_property comp_exg PORT_NAME_MAP ""
163set_interface_property comp_exg CMSIS_SVD_VARIABLES ""
164set_interface_property comp_exg SVD_ADDRESS_GROUP ""
165
166add_interface_port comp_exg aso_comp_exg_data data Output 32
167add_interface_port comp_exg aso_comp_exg_ready ready Input 1
168add_interface_port comp_exg aso_comp_exg_valid valid Output 1
169
170
171#
172# connection point raw_exg_out
173#
174add_interface raw_exg_out avalon_streaming start
175set_interface_property raw_exg_out associatedClock clock
176set_interface_property raw_exg_out associatedReset reset
177set_interface_property raw_exg_out dataBitsPerSymbol 8
178set_interface_property raw_exg_out errorDescriptor ""
179set_interface_property raw_exg_out firstSymbolInHighOrderBits true
180set_interface_property raw_exg_out maxChannel 0
181set_interface_property raw_exg_out readyLatency 0
182set_interface_property raw_exg_out ENABLED true
183set_interface_property raw_exg_out EXPORT_OF ""
184set_interface_property raw_exg_out PORT_NAME_MAP ""
185set_interface_property raw_exg_out CMSIS_SVD_VARIABLES ""
186set_interface_property raw_exg_out SVD_ADDRESS_GROUP ""
187
188add_interface_port raw_exg_out aso_raw_exg_data data Output 32
189add_interface_port raw_exg_out aso_raw_exg_ready ready Input 1
190add_interface_port raw_exg_out aso_raw_exg_valid valid Output 1
191
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