source: PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec_hw.tcl @ 87

Last change on this file since 87 was 87, checked in by lambert, 10 years ago

Adding generation simulation support for verilog
File size: 6.6 KB
Line 
1# TCL File Generated by Component Editor 13.1
2# Mon Mar 03 15:32:05 CET 2014
3# DO NOT MODIFY
4
5
6#
7# exg_codec "exg_codec" v1.0
8#  2014.03.03.15:32:05
9#
10#
11
12#
13# request TCL package from ACDS 13.1
14#
15package require -exact qsys 13.1
16
17
18#
19# module exg_codec
20#
21set_module_property DESCRIPTION ""
22set_module_property NAME exg_codec
23set_module_property VERSION 1.0
24set_module_property INTERNAL false
25set_module_property OPAQUE_ADDRESS_MAP true
26set_module_property GROUP smartEEG
27set_module_property AUTHOR ""
28set_module_property DISPLAY_NAME exg_codec
29set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30set_module_property EDITABLE true
31set_module_property ANALYZE_HDL AUTO
32set_module_property REPORT_TO_TALKBACK false
33set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36#
37# file sets
38#
39add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40set_fileset_property QUARTUS_SYNTH TOP_LEVEL exg_codec
41set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42add_fileset_file exg_codec.v VERILOG PATH exg_codec.v TOP_LEVEL_FILE
43
44add_fileset SIM_VERILOG SIM_VERILOG "" ""
45set_fileset_property SIM_VERILOG TOP_LEVEL exg_codec
46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
47add_fileset_file exg_codec.v VERILOG PATH exg_codec.v
48
49
50#
51# parameters
52#
53add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1
54set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1
55set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE
56set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING
57set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None
58set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true
59
60
61#
62# display items
63#
64
65
66#
67# connection point clock
68#
69add_interface clock clock end
70set_interface_property clock clockRate 0
71set_interface_property clock ENABLED true
72set_interface_property clock EXPORT_OF ""
73set_interface_property clock PORT_NAME_MAP ""
74set_interface_property clock CMSIS_SVD_VARIABLES ""
75set_interface_property clock SVD_ADDRESS_GROUP ""
76
77add_interface_port clock clk clk Input 1
78
79
80#
81# connection point reset
82#
83add_interface reset reset end
84set_interface_property reset associatedClock clock
85set_interface_property reset synchronousEdges DEASSERT
86set_interface_property reset ENABLED true
87set_interface_property reset EXPORT_OF ""
88set_interface_property reset PORT_NAME_MAP ""
89set_interface_property reset CMSIS_SVD_VARIABLES ""
90set_interface_property reset SVD_ADDRESS_GROUP ""
91
92add_interface_port reset reset reset Input 1
93
94
95#
96# connection point ctrl
97#
98add_interface ctrl avalon end
99set_interface_property ctrl addressUnits WORDS
100set_interface_property ctrl associatedClock clock
101set_interface_property ctrl associatedReset reset
102set_interface_property ctrl bitsPerSymbol 8
103set_interface_property ctrl burstOnBurstBoundariesOnly false
104set_interface_property ctrl burstcountUnits WORDS
105set_interface_property ctrl explicitAddressSpan 0
106set_interface_property ctrl holdTime 0
107set_interface_property ctrl linewrapBursts false
108set_interface_property ctrl maximumPendingReadTransactions 0
109set_interface_property ctrl readLatency 0
110set_interface_property ctrl readWaitTime 1
111set_interface_property ctrl setupTime 0
112set_interface_property ctrl timingUnits Cycles
113set_interface_property ctrl writeWaitTime 0
114set_interface_property ctrl ENABLED true
115set_interface_property ctrl EXPORT_OF ""
116set_interface_property ctrl PORT_NAME_MAP ""
117set_interface_property ctrl CMSIS_SVD_VARIABLES ""
118set_interface_property ctrl SVD_ADDRESS_GROUP ""
119
120add_interface_port ctrl avs_ctrl_address address Input 8
121add_interface_port ctrl avs_ctrl_read read Input 1
122add_interface_port ctrl avs_ctrl_readdata readdata Output 32
123add_interface_port ctrl avs_ctrl_write write Input 1
124add_interface_port ctrl avs_ctrl_writedata writedata Input 32
125add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
126set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
127set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
128set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
129set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
130
131
132#
133# connection point raw_exg
134#
135add_interface raw_exg avalon_streaming end
136set_interface_property raw_exg associatedClock clock
137set_interface_property raw_exg associatedReset reset
138set_interface_property raw_exg dataBitsPerSymbol 8
139set_interface_property raw_exg errorDescriptor ""
140set_interface_property raw_exg firstSymbolInHighOrderBits true
141set_interface_property raw_exg maxChannel 0
142set_interface_property raw_exg readyLatency 0
143set_interface_property raw_exg ENABLED true
144set_interface_property raw_exg EXPORT_OF ""
145set_interface_property raw_exg PORT_NAME_MAP ""
146set_interface_property raw_exg CMSIS_SVD_VARIABLES ""
147set_interface_property raw_exg SVD_ADDRESS_GROUP ""
148
149add_interface_port raw_exg asi_raw_exg_data data Input 32
150add_interface_port raw_exg asi_raw_exg_ready ready Output 1
151add_interface_port raw_exg asi_raw_exg_valid valid Input 1
152
153
154#
155# connection point comp_exg
156#
157add_interface comp_exg avalon_streaming start
158set_interface_property comp_exg associatedClock clock
159set_interface_property comp_exg associatedReset reset
160set_interface_property comp_exg dataBitsPerSymbol 8
161set_interface_property comp_exg errorDescriptor ""
162set_interface_property comp_exg firstSymbolInHighOrderBits true
163set_interface_property comp_exg maxChannel 0
164set_interface_property comp_exg readyLatency 0
165set_interface_property comp_exg ENABLED true
166set_interface_property comp_exg EXPORT_OF ""
167set_interface_property comp_exg PORT_NAME_MAP ""
168set_interface_property comp_exg CMSIS_SVD_VARIABLES ""
169set_interface_property comp_exg SVD_ADDRESS_GROUP ""
170
171add_interface_port comp_exg aso_comp_exg_data data Output 32
172add_interface_port comp_exg aso_comp_exg_ready ready Input 1
173add_interface_port comp_exg aso_comp_exg_valid valid Output 1
174
175
176#
177# connection point raw_exg_out
178#
179add_interface raw_exg_out avalon_streaming start
180set_interface_property raw_exg_out associatedClock clock
181set_interface_property raw_exg_out associatedReset reset
182set_interface_property raw_exg_out dataBitsPerSymbol 8
183set_interface_property raw_exg_out errorDescriptor ""
184set_interface_property raw_exg_out firstSymbolInHighOrderBits true
185set_interface_property raw_exg_out maxChannel 0
186set_interface_property raw_exg_out readyLatency 0
187set_interface_property raw_exg_out ENABLED true
188set_interface_property raw_exg_out EXPORT_OF ""
189set_interface_property raw_exg_out PORT_NAME_MAP ""
190set_interface_property raw_exg_out CMSIS_SVD_VARIABLES ""
191set_interface_property raw_exg_out SVD_ADDRESS_GROUP ""
192
193add_interface_port raw_exg_out aso_raw_exg_data data Output 32
194add_interface_port raw_exg_out aso_raw_exg_ready ready Input 1
195add_interface_port raw_exg_out aso_raw_exg_valid valid Output 1
196
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