source: PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec @ 87

Name Size Rev Age Author Last Change
../
exg_codec.v 1.9 KB ​ 84   11 years lambert Adding hierarchical subdirectory for every component
exg_codec_hw.tcl 6.6 KB ​ 87   11 years lambert Adding generation simulation support for verilog
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