source: PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec @ 96

Name Size Rev Age Author Last Change
../
exg_codec.v 2.3 KB ​ 89   12 years szahmed Added Headline comments for Verilog files explaining their brief …
exg_codec_hw.tcl 6.6 KB ​ 87   12 years lambert Adding generation simulation support for verilog
Note: See TracBrowser for help on using the repository browser.